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Thu, 27 Nov 2025 04:22:15 -0800 (PST) Date: Thu, 27 Nov 2025 12:22:09 +0000 In-Reply-To: <20251127122210.4111702-1-tabba@google.com> Mime-Version: 1.0 References: <20251127122210.4111702-1-tabba@google.com> X-Mailer: git-send-email 2.52.0.487.g5c8c507ade-goog Message-ID: <20251127122210.4111702-5-tabba@google.com> Subject: [PATCH v1 4/5] arm64: Inject UNDEF when accessing MTE sysregs with MTE disabled From: Fuad Tabba To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, tabba@google.com Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251127_042217_866362_F46E6170 X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When MTE hardware is present but disabled via software (arm64.nomte or CONFIG_ARM64_MTE=n), HCR_EL2.ATA is cleared to prevent use of MTE instructions. However, this alone doesn't fully emulate hardware that lacks MTE support. With HCR_EL2.ATA cleared, accesses to certain MTE system registers trap to EL2 with exception class ESR_ELx_EC_SYS64. To faithfully emulate hardware without MTE (where such accesses would cause an Undefined Instruction exception), inject UNDEF into the host. Signed-off-by: Fuad Tabba --- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 44 ++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 29430c031095..f542e4c17156 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -686,6 +686,46 @@ static void handle_host_smc(struct kvm_cpu_context *host_ctxt) kvm_skip_host_instr(); } +static void inject_undef64(void) +{ + unsigned long sctlr, vbar, old, new; + u64 offset, esr; + + vbar = read_sysreg_el1(SYS_VBAR); + sctlr = read_sysreg_el1(SYS_SCTLR); + old = read_sysreg_el2(SYS_SPSR); + new = get_except64_cpsr(old, system_supports_mte(), sctlr, PSR_MODE_EL1h); + offset = get_except64_offset(old, PSR_MODE_EL1h, except_type_sync); + esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT) | ESR_ELx_IL; + + write_sysreg_el1(esr, SYS_ESR); + write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR); + write_sysreg_el1(old, SYS_SPSR); + write_sysreg_el2(vbar + offset, SYS_ELR); + write_sysreg_el2(new, SYS_SPSR); +} + +static bool handle_host_mte(u64 esr) +{ + /* If we're here for any reason other than MTE, then it's a bug. */ + + if (read_sysreg(HCR_EL2) & HCR_ATA) + return false; + + switch (esr_sys64_to_sysreg(esr)) { + case SYS_RGSR_EL1: + case SYS_GCR_EL1: + case SYS_TFSR_EL1: + case SYS_TFSRE0_EL1: + break; + default: + return false; + } + + inject_undef64(); + return true; +} + void handle_trap(struct kvm_cpu_context *host_ctxt) { u64 esr = read_sysreg_el2(SYS_ESR); @@ -701,6 +741,10 @@ void handle_trap(struct kvm_cpu_context *host_ctxt) case ESR_ELx_EC_DABT_LOW: handle_host_mem_abort(host_ctxt); break; + case ESR_ELx_EC_SYS64: + if (handle_host_mte(esr)) + break; + fallthrough; default: BUG(); } -- 2.52.0.487.g5c8c507ade-goog