From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5EFE0D216BE for ; Thu, 4 Dec 2025 16:59:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6Y9Ch57tOKhVufF9cmzjO6tWSgN0ZIChZXqQm0qwLh4=; b=dw9Rdb024Fs0E1HYZ3KsxvVfeX xsVHclWYP0lTPDhduMDJSLbR1r1b4QJzDHB/uhZ6sGrA/t4UW2rfq/W/5XnUSQguo4VENaz4dnUbU xIaczAoE3B7878kggCd0IFAzVqZi4R9eFQt9buMJPrtpQUsDamMLUCWTVMHwxssxfOo4EEQSTwr0A e0o+5WBIyT0nXvzjvopMeAyI7gaxychnG2HzKe0yiyMEYYlUdgv9qKtK4Xmm07mATGfQw8wmglzAP CFwITZJGukx3ZGbOKu3x3aj2bsUs6fNbCtPFNrd7RRtOZuUhVmsebdgoCZGOx61W+RPBawBvRfJQl wzwX/thQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vRCff-00000008KY2-1aI9; Thu, 04 Dec 2025 16:59:11 +0000 Received: from mxout4.routing.net ([2a03:2900:1:a::9]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vRCfa-00000008KVT-3ygH; Thu, 04 Dec 2025 16:59:08 +0000 Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout4.routing.net (Postfix) with ESMTP id CC2E6100610; Thu, 4 Dec 2025 16:59:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=routing; t=1764867543; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6Y9Ch57tOKhVufF9cmzjO6tWSgN0ZIChZXqQm0qwLh4=; b=AEkizTfiq+Ek0zhA8odeSzVQ01CK8NowWwnLNofbxgIf8NQOiqBN3e6iZHihAcezr70xAY qjjuN+KebBZ0GrCLyWJr/CqszVvyuIVMBrbysheqLU7G85Uc3B6RY+f8YV2I7HsvPa0zzJ 2ks6ySFc/4vnaiWRn1q1MjIYRbiWilw= Received: from frank-u24.. (fttx-pool-157.180.225.155.bambit.de [157.180.225.155]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id 894C21226EB; Thu, 4 Dec 2025 16:59:02 +0000 (UTC) From: Frank Wunderlich To: Felix Fietkau , Sean Wang , Lorenzo Bianconi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Daniel Golle , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Mason Chang Subject: [RFC v2 1/3] net: ethernet: mtk_eth_soc: Add register definitions for RSS and LRO Date: Thu, 4 Dec 2025 17:58:43 +0100 Message-ID: <20251204165849.8214-2-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251204165849.8214-1-linux@fw-web.de> References: <20251204165849.8214-1-linux@fw-web.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251204_085907_134834_1A34844C X-CRM114-Status: GOOD ( 10.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mason Chang Add definitions for Receive Side Scaling and Large Receive Offload support. Signed-off-by: Mason Chang Signed-off-by: Frank Wunderlich --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 23 +++++++++++++++ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 32 +++++++++++++++------ 2 files changed, 46 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index e68997a29191..243ff16fd15e 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -50,13 +50,18 @@ static const struct mtk_reg_map mtk_reg_map = { .rx_ptr = 0x0900, .rx_cnt_cfg = 0x0904, .pcrx_ptr = 0x0908, + .lro_ctrl_dw0 = 0x0980, .glo_cfg = 0x0a04, .rst_idx = 0x0a08, .delay_irq = 0x0a0c, .irq_status = 0x0a20, .irq_mask = 0x0a28, .adma_rx_dbg0 = 0x0a38, + .lro_alt_score_delta = 0x0a4c, .int_grp = 0x0a50, + .lro_rx1_dly_int = 0x0a70, + .lro_ring_dip_dw0 = 0x0b04, + .lro_ring_ctrl_dw1 = 0x0b28, }, .qdma = { .qtx_cfg = 0x1800, @@ -113,6 +118,7 @@ static const struct mtk_reg_map mt7986_reg_map = { .tx_irq_mask = 0x461c, .tx_irq_status = 0x4618, .pdma = { + .rss_glo_cfg = 0x2800, .rx_ptr = 0x4100, .rx_cnt_cfg = 0x4104, .pcrx_ptr = 0x4108, @@ -123,6 +129,12 @@ static const struct mtk_reg_map mt7986_reg_map = { .irq_mask = 0x4228, .adma_rx_dbg0 = 0x4238, .int_grp = 0x4250, + .int_grp3 = 0x422c, + .lro_ctrl_dw0 = 0x4180, + .lro_alt_score_delta = 0x424c, + .lro_rx1_dly_int = 0x4270, + .lro_ring_dip_dw0 = 0x4304, + .lro_ring_ctrl_dw1 = 0x4328, }, .qdma = { .qtx_cfg = 0x4400, @@ -170,10 +182,21 @@ static const struct mtk_reg_map mt7988_reg_map = { .glo_cfg = 0x6a04, .rst_idx = 0x6a08, .delay_irq = 0x6a0c, + .rx_cfg = 0x6a10, .irq_status = 0x6a20, .irq_mask = 0x6a28, .adma_rx_dbg0 = 0x6a38, .int_grp = 0x6a50, + .int_grp3 = 0x6a58, + .tx_delay_irq = 0x6ab0, + .rx_delay_irq = 0x6ac0, + .lro_ctrl_dw0 = 0x6c08, + .lro_alt_score_delta = 0x6c1c, + .lro_ring_dip_dw0 = 0x6c14, + .lro_ring_ctrl_dw1 = 0x6c38, + .lro_alt_dbg = 0x6c40, + .lro_alt_dbg_data = 0x6c44, + .rss_glo_cfg = 0x7000, }, .qdma = { .qtx_cfg = 0x4400, diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 0168e2fbc619..334625814b97 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -1143,16 +1143,30 @@ struct mtk_reg_map { u32 tx_irq_mask; u32 tx_irq_status; struct { - u32 rx_ptr; /* rx base pointer */ - u32 rx_cnt_cfg; /* rx max count configuration */ - u32 pcrx_ptr; /* rx cpu pointer */ - u32 glo_cfg; /* global configuration */ - u32 rst_idx; /* reset index */ - u32 delay_irq; /* delay interrupt */ - u32 irq_status; /* interrupt status */ - u32 irq_mask; /* interrupt mask */ + u32 rx_ptr; /* rx base pointer */ + u32 rx_cnt_cfg; /* rx max count configuration */ + u32 pcrx_ptr; /* rx cpu pointer */ + u32 pdrx_ptr; /* rx dma pointer */ + u32 glo_cfg; /* global configuration */ + u32 rst_idx; /* reset index */ + u32 rx_cfg; /* rx dma configuration */ + u32 delay_irq; /* delay interrupt */ + u32 irq_status; /* interrupt status */ + u32 irq_mask; /* interrupt mask */ u32 adma_rx_dbg0; - u32 int_grp; + u32 int_grp; /* interrupt group1 */ + u32 int_grp3; /* interrupt group3 */ + u32 tx_delay_irq; /* tx delay interrupt */ + u32 rx_delay_irq; /* rx delay interrupt */ + u32 lro_ctrl_dw0; /* lro ctrl dword0 */ + u32 lro_alt_score_delta; /* lro auto-learn score delta */ + u32 lro_rx1_dly_int; /* lro rx ring1 delay interrupt */ + u32 lro_ring_dip_dw0; /* lro ring dip dword0 */ + u32 lro_ring_ctrl_dw1; /* lro ring ctrl dword1 */ + u32 lro_alt_dbg; /* lro auto-learn debug */ + u32 lro_alt_dbg_data; /* lro auto-learn debug data */ + u32 rss_glo_cfg; /* rss global configuration */ + } pdma; struct { u32 qtx_cfg; /* tx queue configuration */ -- 2.43.0