[PATCH v8 0/2] Add Google Tensor SoC USB PHY support

[PATCH v8 0/2] Add Google Tensor SoC USB PHY support

[Roy Luo]

This series introduces USB PHY support for the Google Tensor G5
SoC (codename: Laguna), a new generation of Google silicon first
launched with Pixel 10 devices.

The Tensor G5 represents a significant architectural overhaul compared
to previous Tensor generations (e.g., gs101), which were based on Samsung
Exynos IP. Although the G5 still utilizes Synopsys IP for the USB
components, the custom top-level integration introduces a completely new
design for clock, reset scheme, register interfaces and programming
sequence, necessitating new drivers and device tree bindings.

The USB subsystem on Tensor G5 integrates a Synopsys DWC3 USB 3.1
DRD-Single Port controller with hibernation support, and a custom PHY
block comprising Synopsys eUSB2 and USB 3.2/DP combo PHYs. The controller
support is sent as a separate patch series.

Co-developed-by: Joy Chakraborty <joychakr@google.com>
Signed-off-by: Joy Chakraborty <joychakr@google.com>
Co-developed-by: Naveen Kumar <mnkumar@google.com>
Signed-off-by: Naveen Kumar <mnkumar@google.com>
Signed-off-by: Roy Luo <royluo@google.com>
---
Changes in v8:
- Update the Kconfig dependency to depends on ARCH_GOOGLE || COMPILE_TEST
  Note that ARCH_GOOGLE does not exist yet but will eventually
  be there when the following patch lands
  https://lore.kernel.org/r/20251111112158.3.I35b9e835ac49ab408e5ca3e0983930a1f1395814@changeid/
- Mention SoC codename Laguna in Kconfig description.
- Sort the header alphabetically and sort the variables using the
  reverse christmas tree ordering.
- Add driver and binding files to the Tensor SoC MAINTAINER entry.
- Add detailed comment for phy_mutex
Link to v7: https://lore.kernel.org/r/20251121-phyb4-v7-0-df644fa62180@google.com

Changes in v7:
- Change the device tree binding example node name to usb-phy to follow
 the hyphen-separated naming convention and remove label.
Link to v6: https://lore.kernel.org/r/20251120-phyb4-v6-0-b6694e1f0caf@google.com

Changes in v6:
- Use "lga" as SoC name instead of "gs5" to align with Tensor G5 device
  tree https://lore.kernel.org/lkml/20251111192422.4180216-1-dianders@chromium.org 
- Add "usb2_core" to the reg property to define the MMIO space for
  the eUSB 2.0 PHY IP.
- Rename "usb3_top" reg as "usbdp_top" and update the description to
  reflect its nature as a top-level wrapper and align with internal
  documentation.
- Use syscon to access the "usb2_cfg" MMIO space.
- Remove minItems for clocks and resets, making all listed clocks and
  resets (including USB3) mandatory.
Link to v5: https://lore.kernel.org/linux-phy/20251029214032.3175261-1-royluo@google.com

Changes in v5:
- Add usb3 registers/clks/resets to binding as suggested by Krzysztof
  Kozlowski. This ensures completeness of the binding, though the
  driver has not yet ultilized the resources. The usb3 clks and resets
  are optional if usb2-only operation is desired, this is denoted by
  minItems and descriptions in the clocks and resets properties.
  Additionally, rename existing binding entries for consistency and to
  better differntiate between usb2 and usb3.
- Move the description of the phy select to phy-cells in binding as
  suggested by Krzysztof Kozlowski.
Link to v4: https://lore.kernel.org/linux-phy/20251017235159.2417576-1-royluo@google.com

Changes in v4:
- Separate controller and phy changes into two distinct patch series.
- Remove usb2only mode configuration and the corresponding usb_top_cfg
  reg (moved to controller)
- Add more descriptions to dp_top reg to indicate it's not DP specific.
- Add u2phy_apb clk/reset
Link to v3: https://lore.kernel.org/linux-usb/20251010201607.1190967-1-royluo@google.com

Changes in v3:
- Align binding file name with the compatible string
- Simplify the compatible property in binding to a single const value.
- Add descriptive comments and use item list in binding.
- Rename binding entries for clarity and brevity.
Link to v2: https://lore.kernel.org/linux-usb/20251008060000.3136021-1-royluo@google.com

Changes in v2:
- Reorder patches to present bindings first.
- Update dt binding compatible strings to be SoC-specific (google,gs5-*).
- Better describe the hardware in dt binding commit messages and
  descriptions.
- Adjust PHY driver commit subjects to use correct prefixes ("phy:").
- Move PHY driver from a subdirectory to drivers/phy/.
Link to v1: https://lore.kernel.org/linux-usb/20251006232125.1833979-1-royluo@google.com/

---
Roy Luo (2):
      dt-bindings: phy: google: Add Google Tensor G5 USB PHY
      phy: Add Google Tensor SoC USB PHY driver

 .../bindings/phy/google,lga-usb-phy.yaml           | 133 ++++++++++
 MAINTAINERS                                        |   2 +
 drivers/phy/Kconfig                                |  11 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-google-usb.c                       | 295 +++++++++++++++++++++
 5 files changed, 442 insertions(+)
---
base-commit: 43dfc13ca972988e620a6edb72956981b75ab6b0
change-id: 20251119-phyb4-2e03a7c449c4

Best regards,
-- 
Roy Luo <royluo@google.com>

[PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Roy Luo]

Document the device tree bindings for the USB PHY interfaces integrated
with the DWC3 controller on Google Tensor SoCs, starting with G5
generation (Laguna). The USB PHY on Tensor G5 includes two integrated
Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
PHY IP.

Due to a complete architectural overhaul in the Google Tensor G5, the
existing Samsung/Exynos USB PHY binding for older generations of Google
silicons such as gs101 are no longer compatible, necessitating this new
device tree binding.

Signed-off-by: Roy Luo <royluo@google.com>
---
 .../bindings/phy/google,lga-usb-phy.yaml           | 133 +++++++++++++++++++++
 MAINTAINERS                                        |   1 +
 2 files changed, 134 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..427e2e3425f645f40c0813e29d6efe4f62b20609
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025, Google LLC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/google,lga-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor Series G5 (Laguna) USB PHY
+
+maintainers:
+  - Roy Luo <royluo@google.com>
+
+description:
+  Describes the USB PHY interfaces integrated with the DWC3 USB controller on
+  Google Tensor SoCs, starting with the G5 generation (laguna).
+  Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP
+  and USB3.2/DisplayPort combo PHY IP.
+
+properties:
+  compatible:
+    const: google,lga-usb-phy
+
+  reg:
+    items:
+      - description: USB3.2/DisplayPort combo PHY core registers.
+      - description: USB3.2/DisplayPort combo PHY Type-C Assist registers.
+      - description: eUSB 2.0 PHY core registers.
+      - description: Top-level wrapper registers for the integrated PHYs.
+
+  reg-names:
+    items:
+      - const: usb3_core
+      - const: usb3_tca
+      - const: usb2_core
+      - const: usbdp_top
+
+  "#phy-cells":
+    description: |
+      The phandle's argument in the PHY specifier selects one of the three
+      following PHY interfaces.
+      - 0 for USB high-speed.
+      - 1 for USB super-speed.
+      - 2 for DisplayPort.
+    const: 1
+
+  clocks:
+    items:
+      - description: USB2 PHY clock.
+      - description: USB2 PHY APB clock.
+      - description: USB3.2/DisplayPort combo PHY clock.
+      - description: USB3.2/DisplayPort combo PHY firmware clock.
+
+  clock-names:
+    items:
+      - const: usb2
+      - const: usb2_apb
+      - const: usb3
+      - const: usb3_fw
+
+  resets:
+    items:
+      - description: USB2 PHY reset.
+      - description: USB2 PHY APB reset.
+      - description: USB3.2/DisplayPort combo PHY reset.
+
+  reset-names:
+    items:
+      - const: usb2
+      - const: usb2_apb
+      - const: usb3
+
+  power-domains:
+    maxItems: 1
+
+  orientation-switch:
+    type: boolean
+    description:
+      Indicates the PHY as a handler of USB Type-C orientation changes
+
+  google,usb-cfg-csr:
+    description:
+      A phandle to a syscon node used to access the USB configuration
+      registers. These registers are the top-level wrapper of the USB
+      subsystem and provide control and status for the integrated USB
+      controller and USB PHY.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to the syscon node.
+          - description: USB2 PHY configuration register offset.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - "#phy-cells"
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - orientation-switch
+  - google,usb-cfg-csr
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        usb-phy@c410000 {
+            compatible = "google,lga-usb-phy";
+            reg = <0 0x0c410000 0 0x20000>,
+                  <0 0x0c430000 0 0x1000>,
+                  <0 0x0c440000 0 0x10000>,
+                  <0 0x0c637000 0 0xa0>;
+            reg-names = "usb3_core", "usb3_tca", "usb2_core", "usbdp_top";
+            #phy-cells = <1>;
+            clocks = <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>,
+                     <&hsion_usb3_phy_clk>, <&hsion_usb3_phy_fw_clk>;
+            clock-names = "usb2", "usb2_apb", "usb3", "usb3_fw";
+            resets = <&hsion_resets_usb2_phy>,
+                     <&hsion_resets_u2phy_apb>,
+                     <&hsion_resets_usb3_phy>;
+            reset-names = "usb2", "usb2_apb", "usb3";
+            power-domains = <&hsio_n_usb_pd>;
+            orientation-switch;
+            google,usb-cfg-csr = <&usb_cfg_csr 0x14>;
+        };
+    };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 772af0072fff0921000c6fe27c018666c1579e48..27e6f9e20f5e83b861c6a04dededb93b8561715c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10661,6 +10661,7 @@ S:	Maintained
 P:	Documentation/process/maintainer-soc-clean-dts.rst
 C:	irc://irc.oftc.net/pixel6-kernel-dev
 F:	Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+F:	Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
 F:	Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml
 F:	arch/arm64/boot/dts/exynos/google/
 F:	drivers/clk/samsung/clk-gs101.c

-- 
2.52.0.223.gf5cc29aaa4-goog

[PATCH v8 2/2] phy: Add Google Tensor SoC USB PHY driver

[Roy Luo]

Support the USB PHY found on Google Tensor G5 (Laguna). This
particular USB PHY supports both high-speed and super-speed
operations, and is integrated with the SNPS DWC3 controller that's
also on the SoC. This initial patch specifically adds functionality
for high-speed.

Co-developed-by: Joy Chakraborty <joychakr@google.com>
Signed-off-by: Joy Chakraborty <joychakr@google.com>
Co-developed-by: Naveen Kumar <mnkumar@google.com>
Signed-off-by: Naveen Kumar <mnkumar@google.com>
Signed-off-by: Roy Luo <royluo@google.com>
---
 MAINTAINERS                  |   1 +
 drivers/phy/Kconfig          |  11 ++
 drivers/phy/Makefile         |   1 +
 drivers/phy/phy-google-usb.c | 295 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 308 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 27e6f9e20f5e83b861c6a04dededb93b8561715c..50ffe42c7c373914aa96314430f35843efc1dc07 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10665,6 +10665,7 @@ F:	Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
 F:	Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml
 F:	arch/arm64/boot/dts/exynos/google/
 F:	drivers/clk/samsung/clk-gs101.c
+F:	drivers/phy/phy-google-usb.c
 F:	drivers/phy/samsung/phy-gs101-ufs.c
 F:	include/dt-bindings/clock/google,gs101.h
 K:	[gG]oogle.?[tT]ensor
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0aa0597773433f04d2a9ba77474d2a..c6fbf83de656349f5c9be27a18748b9bd327f683 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -101,6 +101,17 @@ config PHY_NXP_PTN3222
 	  schemes. It supports all three USB 2.0 data rates: Low Speed, Full
 	  Speed and High Speed.
 
+config PHY_GOOGLE_USB
+	tristate "Google Tensor SoC USB PHY driver"
+	depends on ARCH_GOOGLE || COMPILE_TEST
+	select GENERIC_PHY
+	help
+	  Enable support for the USB PHY on Google Tensor SoCs, starting with
+	  the G5 generation (Laguna). This driver provides the PHY interfaces
+	  to interact with the SNPS eUSB2 and USB 3.2/DisplayPort Combo PHY,
+	  both of which are integrated with the DWC3 USB DRD controller.
+	  This driver currently supports USB high-speed.
+
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494283d7fd05dd670ebd1b12df8b1a1..aeaaaf988554a24bb572d8b34b54638a6a3aed73 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2)		+= phy-snps-eusb2.o
 obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o
 obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o
 obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o
+obj-$(CONFIG_PHY_GOOGLE_USB)		+= phy-google-usb.o
 obj-y					+= allwinner/	\
 					   amlogic/	\
 					   broadcom/	\
diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c
new file mode 100644
index 0000000000000000000000000000000000000000..97e345fdab9b3679e7a76f6957ae3814ef3420e8
--- /dev/null
+++ b/drivers/phy/phy-google-usb.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * phy-google-usb.c - Google USB PHY driver
+ *
+ * Copyright (C) 2025, Google LLC
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/usb/typec_mux.h>
+
+#define USBCS_USB2PHY_CFG19_OFFSET 0x0
+#define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8)
+
+#define USBCS_USB2PHY_CFG21_OFFSET 0x8
+#define USBCS_USB2PHY_CFG21_PHY_ENABLE BIT(12)
+#define USBCS_USB2PHY_CFG21_REF_FREQ_SEL GENMASK(15, 13)
+#define USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL BIT(19)
+
+#define USBCS_PHY_CFG1_OFFSET 0x28
+#define USBCS_PHY_CFG1_SYS_VBUSVALID BIT(17)
+
+enum google_usb_phy_id {
+	GOOGLE_USB2_PHY,
+	GOOGLE_USB_PHY_NUM,
+};
+
+struct google_usb_phy_instance {
+	int index;
+	struct phy *phy;
+	int num_clks;
+	struct clk_bulk_data *clks;
+	int num_rsts;
+	struct reset_control_bulk_data *rsts;
+};
+
+struct google_usb_phy {
+	struct device *dev;
+	struct regmap *usb_cfg_regmap;
+	unsigned int usb2_cfg_offset;
+	void __iomem *usbdp_top_base;
+	struct google_usb_phy_instance insts[GOOGLE_USB_PHY_NUM];
+	/*
+	 * Protect phy registers from concurrent access, specifically via
+	 * google_usb_set_orientation callback.
+	 */
+	struct mutex phy_mutex;
+	struct typec_switch_dev *sw;
+	enum typec_orientation orientation;
+};
+
+static inline struct google_usb_phy *to_google_usb_phy(struct google_usb_phy_instance *inst)
+{
+	return container_of(inst, struct google_usb_phy, insts[inst->index]);
+}
+
+static void set_vbus_valid(struct google_usb_phy *gphy)
+{
+	u32 reg;
+
+	if (gphy->orientation == TYPEC_ORIENTATION_NONE) {
+		reg = readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET);
+		reg &= ~USBCS_PHY_CFG1_SYS_VBUSVALID;
+		writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET);
+	} else {
+		reg = readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET);
+		reg |= USBCS_PHY_CFG1_SYS_VBUSVALID;
+		writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET);
+	}
+}
+
+static int google_usb_set_orientation(struct typec_switch_dev *sw,
+				      enum typec_orientation orientation)
+{
+	struct google_usb_phy *gphy = typec_switch_get_drvdata(sw);
+
+	dev_dbg(gphy->dev, "set orientation %d\n", orientation);
+
+	gphy->orientation = orientation;
+
+	if (pm_runtime_suspended(gphy->dev))
+		return 0;
+
+	guard(mutex)(&gphy->phy_mutex);
+
+	set_vbus_valid(gphy);
+
+	return 0;
+}
+
+static int google_usb2_phy_init(struct phy *_phy)
+{
+	struct google_usb_phy_instance *inst = phy_get_drvdata(_phy);
+	struct google_usb_phy *gphy = to_google_usb_phy(inst);
+	u32 reg;
+	int ret = 0;
+
+	dev_dbg(gphy->dev, "initializing usb2 phy\n");
+
+	guard(mutex)(&gphy->phy_mutex);
+
+	regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_CFG21_OFFSET, &reg);
+	reg &= ~USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL;
+	reg &= ~USBCS_USB2PHY_CFG21_REF_FREQ_SEL;
+	reg |= FIELD_PREP(USBCS_USB2PHY_CFG21_REF_FREQ_SEL, 0);
+	regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_CFG21_OFFSET, reg);
+
+	regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_CFG19_OFFSET, &reg);
+	reg &= ~USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV;
+	reg |= FIELD_PREP(USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV, 368);
+	regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_CFG19_OFFSET, reg);
+
+	set_vbus_valid(gphy);
+
+	ret = clk_bulk_prepare_enable(inst->num_clks, inst->clks);
+	if (ret)
+		return ret;
+
+	ret = reset_control_bulk_deassert(inst->num_rsts, inst->rsts);
+	if (ret) {
+		clk_bulk_disable_unprepare(inst->num_clks, inst->clks);
+		return ret;
+	}
+
+	regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_CFG21_OFFSET, &reg);
+	reg |= USBCS_USB2PHY_CFG21_PHY_ENABLE;
+	regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_CFG21_OFFSET, reg);
+
+	return ret;
+}
+
+static int google_usb2_phy_exit(struct phy *_phy)
+{
+	struct google_usb_phy_instance *inst = phy_get_drvdata(_phy);
+	struct google_usb_phy *gphy = to_google_usb_phy(inst);
+	u32 reg;
+
+	dev_dbg(gphy->dev, "exiting usb2 phy\n");
+
+	guard(mutex)(&gphy->phy_mutex);
+
+	regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_CFG21_OFFSET, &reg);
+	reg &= ~USBCS_USB2PHY_CFG21_PHY_ENABLE;
+	regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_CFG21_OFFSET, reg);
+
+	reset_control_bulk_assert(inst->num_rsts, inst->rsts);
+	clk_bulk_disable_unprepare(inst->num_clks, inst->clks);
+
+	return 0;
+}
+
+static const struct phy_ops google_usb2_phy_ops = {
+	.init		= google_usb2_phy_init,
+	.exit		= google_usb2_phy_exit,
+};
+
+static struct phy *google_usb_phy_xlate(struct device *dev,
+					const struct of_phandle_args *args)
+{
+	struct google_usb_phy *gphy = dev_get_drvdata(dev);
+
+	if (args->args[0] >= GOOGLE_USB_PHY_NUM) {
+		dev_err(dev, "invalid PHY index requested from DT\n");
+		return ERR_PTR(-ENODEV);
+	}
+	return gphy->insts[args->args[0]].phy;
+}
+
+static int google_usb_phy_probe(struct platform_device *pdev)
+{
+	struct typec_switch_desc sw_desc = { };
+	struct google_usb_phy_instance *inst;
+	struct phy_provider *phy_provider;
+	struct device *dev = &pdev->dev;
+	struct google_usb_phy *gphy;
+	struct phy *phy;
+	u32 args[1];
+	int ret;
+
+	gphy = devm_kzalloc(dev, sizeof(*gphy), GFP_KERNEL);
+	if (!gphy)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, gphy);
+	gphy->dev = dev;
+
+	ret = devm_mutex_init(dev, &gphy->phy_mutex);
+	if (ret)
+		return ret;
+
+	gphy->usb_cfg_regmap =
+		syscon_regmap_lookup_by_phandle_args(dev->of_node,
+						     "google,usb-cfg-csr",
+						     ARRAY_SIZE(args), args);
+	if (IS_ERR(gphy->usb_cfg_regmap)) {
+		return dev_err_probe(dev, PTR_ERR(gphy->usb_cfg_regmap),
+				     "invalid usb cfg csr\n");
+	}
+
+	gphy->usb2_cfg_offset = args[0];
+
+	gphy->usbdp_top_base = devm_platform_ioremap_resource_byname(pdev,
+								     "usbdp_top");
+	if (IS_ERR(gphy->usbdp_top_base))
+		return dev_err_probe(dev, PTR_ERR(gphy->usbdp_top_base),
+				    "invalid usbdp top\n");
+
+	inst = &gphy->insts[GOOGLE_USB2_PHY];
+	inst->index = GOOGLE_USB2_PHY;
+	phy = devm_phy_create(dev, NULL, &google_usb2_phy_ops);
+	if (IS_ERR(phy))
+		return dev_err_probe(dev, PTR_ERR(phy),
+				     "failed to create usb2 phy instance\n");
+	inst->phy = phy;
+	phy_set_drvdata(phy, inst);
+
+	inst->num_clks = 2;
+	inst->clks = devm_kcalloc(dev, inst->num_clks, sizeof(*inst->clks), GFP_KERNEL);
+	if (!inst->clks)
+		return -ENOMEM;
+	inst->clks[0].id = "usb2";
+	inst->clks[1].id = "usb2_apb";
+	ret = devm_clk_bulk_get(dev, inst->num_clks, inst->clks);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to get u2 phy clks\n");
+
+	inst->num_rsts = 2;
+	inst->rsts = devm_kcalloc(dev, inst->num_rsts, sizeof(*inst->rsts), GFP_KERNEL);
+	if (!inst->rsts)
+		return -ENOMEM;
+	inst->rsts[0].id = "usb2";
+	inst->rsts[1].id = "usb2_apb";
+	ret = devm_reset_control_bulk_get_exclusive(dev, inst->num_rsts, inst->rsts);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to get u2 phy resets\n");
+
+	phy_provider = devm_of_phy_provider_register(dev, google_usb_phy_xlate);
+	if (IS_ERR(phy_provider))
+		return dev_err_probe(dev, PTR_ERR(phy_provider),
+				     "failed to register phy provider\n");
+
+	pm_runtime_enable(dev);
+
+	sw_desc.fwnode = dev_fwnode(dev);
+	sw_desc.drvdata = gphy;
+	sw_desc.name = fwnode_get_name(dev_fwnode(dev));
+	sw_desc.set = google_usb_set_orientation;
+
+	gphy->sw = typec_switch_register(dev, &sw_desc);
+	if (IS_ERR(gphy->sw))
+		return dev_err_probe(dev, PTR_ERR(gphy->sw),
+				     "failed to register typec switch\n");
+
+	return 0;
+}
+
+static void google_usb_phy_remove(struct platform_device *pdev)
+{
+	struct google_usb_phy *gphy = dev_get_drvdata(&pdev->dev);
+
+	typec_switch_unregister(gphy->sw);
+	pm_runtime_disable(&pdev->dev);
+}
+
+static const struct of_device_id google_usb_phy_of_match[] = {
+	{
+		.compatible = "google,lga-usb-phy",
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, google_usb_phy_of_match);
+
+static struct platform_driver google_usb_phy = {
+	.probe	= google_usb_phy_probe,
+	.remove = google_usb_phy_remove,
+	.driver = {
+		.name		= "google-usb-phy",
+		.of_match_table	= google_usb_phy_of_match,
+	}
+};
+
+module_platform_driver(google_usb_phy);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Google USB phy driver");

-- 
2.52.0.223.gf5cc29aaa4-goog

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Krzysztof Kozlowski]

On 05/12/2025 04:54, Roy Luo wrote:
> Document the device tree bindings for the USB PHY interfaces integrated
> with the DWC3 controller on Google Tensor SoCs, starting with G5
> generation (Laguna). The USB PHY on Tensor G5 includes two integrated
> Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
> PHY IP.
> 
> Due to a complete architectural overhaul in the Google Tensor G5, the
> existing Samsung/Exynos USB PHY binding for older generations of Google
> silicons such as gs101 are no longer compatible, necessitating this new
> device tree binding.
> 
> Signed-off-by: Roy Luo <royluo@google.com>

Why intentionally dropping the tag? How are you handling this patchset?
Rewrite every time from scratch?

<form letter>
This is a friendly reminder during the review process.

It looks like you received a tag and forgot to add it.

If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
of patchset, under or above your Signed-off-by tag, unless patch changed
significantly (e.g. new properties added to the DT bindings). Tag is
"received", when provided in a message replied to you on the mailing
list. Tools like b4 can help here. However, there's no need to repost
patches *only* to add the tags. The upstream maintainer will do that for
tags received on the version they apply.

Please read:
https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577

If a tag was not added on purpose, please state why and what changed.
</form letter>

Best regards,
Krzysztof

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Roy Luo]

On Fri, Dec 5, 2025 at 9:13 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 05/12/2025 04:54, Roy Luo wrote:
> > Document the device tree bindings for the USB PHY interfaces integrated
> > with the DWC3 controller on Google Tensor SoCs, starting with G5
> > generation (Laguna). The USB PHY on Tensor G5 includes two integrated
> > Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
> > PHY IP.
> >
> > Due to a complete architectural overhaul in the Google Tensor G5, the
> > existing Samsung/Exynos USB PHY binding for older generations of Google
> > silicons such as gs101 are no longer compatible, necessitating this new
> > device tree binding.
> >
> > Signed-off-by: Roy Luo <royluo@google.com>
>
> Why intentionally dropping the tag? How are you handling this patchset?
> Rewrite every time from scratch?

Hi Krzysztof,

I dropped the tag because a new file is being modified in this version,
Although it's just MAINTAINER file but I thought you might also want
to take a look. I wasn't sure if modifying a new file qualifies as
"substantial" so I erred on the side of caution. I should've called it
out specifically in the change log. Sorry for the inconvenience.

Regards,
Roy Luo

>
> <form letter>
> This is a friendly reminder during the review process.
>
> It looks like you received a tag and forgot to add it.
>
> If you do not know the process, here is a short explanation:
> Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
> of patchset, under or above your Signed-off-by tag, unless patch changed
> significantly (e.g. new properties added to the DT bindings). Tag is
> "received", when provided in a message replied to you on the mailing
> list. Tools like b4 can help here. However, there's no need to repost
> patches *only* to add the tags. The upstream maintainer will do that for
> tags received on the version they apply.
>
> Please read:
> https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577
>
> If a tag was not added on purpose, please state why and what changed.
> </form letter>
>
> Best regards,
> Krzysztof

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Krzysztof Kozlowski]

On 05/12/2025 19:47, Roy Luo wrote:
> On Fri, Dec 5, 2025 at 9:13 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 05/12/2025 04:54, Roy Luo wrote:
>>> Document the device tree bindings for the USB PHY interfaces integrated
>>> with the DWC3 controller on Google Tensor SoCs, starting with G5
>>> generation (Laguna). The USB PHY on Tensor G5 includes two integrated
>>> Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
>>> PHY IP.
>>>
>>> Due to a complete architectural overhaul in the Google Tensor G5, the
>>> existing Samsung/Exynos USB PHY binding for older generations of Google
>>> silicons such as gs101 are no longer compatible, necessitating this new
>>> device tree binding.
>>>
>>> Signed-off-by: Roy Luo <royluo@google.com>
>>
>> Why intentionally dropping the tag? How are you handling this patchset?
>> Rewrite every time from scratch?
> 
> Hi Krzysztof,
> 
> I dropped the tag because a new file is being modified in this version,
> Although it's just MAINTAINER file but I thought you might also want
> to take a look. I wasn't sure if modifying a new file qualifies as
> "substantial" so I erred on the side of caution. I should've called it
> out specifically in the change log. Sorry for the inconvenience.

1. so just squeeze that change into second patch and no need to ask for
re-review
2. You did not read my complain fully, look:

> 
> Regards,
> Roy Luo
> 
>>
>> <form letter>
>> This is a friendly reminder during the review process.
>>
>> It looks like you received a tag and forgot to add it.
>>
>> If you do not know the process, here is a short explanation:
>> Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
>> of patchset, under or above your Signed-off-by tag, unless patch changed
>> significantly (e.g. new properties added to the DT bindings). Tag is
>> "received", when provided in a message replied to you on the mailing
>> list. Tools like b4 can help here. However, there's no need to repost
>> patches *only* to add the tags. The upstream maintainer will do that for
>> tags received on the version they apply.
>>
>> Please read:
>> https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577
>>
>> If a tag was not added on purpose, please state why and what changed.

Where did you address this? You dropped the tag silently.


Best regards,
Krzysztof

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Roy Luo]

On Fri, Dec 5, 2025 at 10:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 05/12/2025 19:47, Roy Luo wrote:
> > On Fri, Dec 5, 2025 at 9:13 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On 05/12/2025 04:54, Roy Luo wrote:
> >>> Document the device tree bindings for the USB PHY interfaces integrated
> >>> with the DWC3 controller on Google Tensor SoCs, starting with G5
> >>> generation (Laguna). The USB PHY on Tensor G5 includes two integrated
> >>> Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
> >>> PHY IP.
> >>>
> >>> Due to a complete architectural overhaul in the Google Tensor G5, the
> >>> existing Samsung/Exynos USB PHY binding for older generations of Google
> >>> silicons such as gs101 are no longer compatible, necessitating this new
> >>> device tree binding.
> >>>
> >>> Signed-off-by: Roy Luo <royluo@google.com>
> >>
> >> Why intentionally dropping the tag? How are you handling this patchset?
> >> Rewrite every time from scratch?
> >
> > Hi Krzysztof,
> >
> > I dropped the tag because a new file is being modified in this version,
> > Although it's just MAINTAINER file but I thought you might also want
> > to take a look. I wasn't sure if modifying a new file qualifies as
> > "substantial" so I erred on the side of caution. I should've called it
> > out specifically in the change log. Sorry for the inconvenience.
>
> 1. so just squeeze that change into second patch and no need to ask for
> re-review

That's a fair point. I will be more mindful of the review overhead
going forward.

> 2. You did not read my complain fully, look:
>
> >
> > Regards,
> > Roy Luo
> >
> >>
> >> <form letter>
> >> This is a friendly reminder during the review process.
> >>
> >> It looks like you received a tag and forgot to add it.
> >>
> >> If you do not know the process, here is a short explanation:
> >> Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
> >> of patchset, under or above your Signed-off-by tag, unless patch changed
> >> significantly (e.g. new properties added to the DT bindings). Tag is
> >> "received", when provided in a message replied to you on the mailing
> >> list. Tools like b4 can help here. However, there's no need to repost
> >> patches *only* to add the tags. The upstream maintainer will do that for
> >> tags received on the version they apply.
> >>
> >> Please read:
> >> https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577
> >>
> >> If a tag was not added on purpose, please state why and what changed.
>
> Where did you address this? You dropped the tag silently.

Why: a new file is being modified.
What changed: MAINTAINER
What's not changed:
Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml

Could you consider re-reviewing this patch?

Thanks,
Roy Luo

>
>
> Best regards,
> Krzysztof

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Krzysztof Kozlowski]

On 05/12/2025 20:11, Roy Luo wrote:
> On Fri, Dec 5, 2025 at 10:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 05/12/2025 19:47, Roy Luo wrote:
>>> On Fri, Dec 5, 2025 at 9:13 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>
>>>> On 05/12/2025 04:54, Roy Luo wrote:
>>>>> Document the device tree bindings for the USB PHY interfaces integrated
>>>>> with the DWC3 controller on Google Tensor SoCs, starting with G5
>>>>> generation (Laguna). The USB PHY on Tensor G5 includes two integrated
>>>>> Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
>>>>> PHY IP.
>>>>>
>>>>> Due to a complete architectural overhaul in the Google Tensor G5, the
>>>>> existing Samsung/Exynos USB PHY binding for older generations of Google
>>>>> silicons such as gs101 are no longer compatible, necessitating this new
>>>>> device tree binding.
>>>>>
>>>>> Signed-off-by: Roy Luo <royluo@google.com>
>>>>
>>>> Why intentionally dropping the tag? How are you handling this patchset?
>>>> Rewrite every time from scratch?
>>>
>>> Hi Krzysztof,
>>>
>>> I dropped the tag because a new file is being modified in this version,
>>> Although it's just MAINTAINER file but I thought you might also want
>>> to take a look. I wasn't sure if modifying a new file qualifies as
>>> "substantial" so I erred on the side of caution. I should've called it
>>> out specifically in the change log. Sorry for the inconvenience.
>>
>> 1. so just squeeze that change into second patch and no need to ask for
>> re-review
> 
> That's a fair point. I will be more mindful of the review overhead
> going forward.
> 
>> 2. You did not read my complain fully, look:
>>
>>>
>>> Regards,
>>> Roy Luo
>>>
>>>>
>>>> <form letter>
>>>> This is a friendly reminder during the review process.
>>>>
>>>> It looks like you received a tag and forgot to add it.
>>>>
>>>> If you do not know the process, here is a short explanation:
>>>> Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
>>>> of patchset, under or above your Signed-off-by tag, unless patch changed
>>>> significantly (e.g. new properties added to the DT bindings). Tag is
>>>> "received", when provided in a message replied to you on the mailing
>>>> list. Tools like b4 can help here. However, there's no need to repost
>>>> patches *only* to add the tags. The upstream maintainer will do that for
>>>> tags received on the version they apply.
>>>>
>>>> Please read:
>>>> https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577
>>>>
>>>> If a tag was not added on purpose, please state why and what changed.
>>
>> Where did you address this? You dropped the tag silently.
> 
> Why: a new file is being modified.
> What changed: MAINTAINER
> What's not changed:
> Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml

I don't know if you still did not get the problem or you think that I
really need that clear answer. So no, I do not need that clear answer, I
understood with first reply, but you kept explaining instead of
admitting that your changelog needs fixes. So I still do not believe you
understood the problem here and you might repeat the mistake.

I think you need someone in Google to coach in this process, because I
even gave you the exact link describing the process and what was
expected. I even pointed specific paragraph, so you don't need to read
entire file!

I assume you understood what should be done instead in this patchset.
Anyway, my previous tag applies if there were no bindings changes, but I
wasted too much time here to care anymore. The expectation from big
companies is they do not ask community to coach on basic submission
process. It's quite unfair to my spare, personal time after work,
considering how much big company is making. Big company should invest in
this coaching.


Best regards,
Krzysztof

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Roy Luo]

On Fri, Dec 5, 2025 at 11:26 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 05/12/2025 20:11, Roy Luo wrote:
> > On Fri, Dec 5, 2025 at 10:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On 05/12/2025 19:47, Roy Luo wrote:
> >>> On Fri, Dec 5, 2025 at 9:13 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>>>
> >>>> On 05/12/2025 04:54, Roy Luo wrote:
> >>>>> Document the device tree bindings for the USB PHY interfaces integrated
> >>>>> with the DWC3 controller on Google Tensor SoCs, starting with G5
> >>>>> generation (Laguna). The USB PHY on Tensor G5 includes two integrated
> >>>>> Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
> >>>>> PHY IP.
> >>>>>
> >>>>> Due to a complete architectural overhaul in the Google Tensor G5, the
> >>>>> existing Samsung/Exynos USB PHY binding for older generations of Google
> >>>>> silicons such as gs101 are no longer compatible, necessitating this new
> >>>>> device tree binding.
> >>>>>
> >>>>> Signed-off-by: Roy Luo <royluo@google.com>
> >>>>
> >>>> Why intentionally dropping the tag? How are you handling this patchset?
> >>>> Rewrite every time from scratch?
> >>>
> >>> Hi Krzysztof,
> >>>
> >>> I dropped the tag because a new file is being modified in this version,
> >>> Although it's just MAINTAINER file but I thought you might also want
> >>> to take a look. I wasn't sure if modifying a new file qualifies as
> >>> "substantial" so I erred on the side of caution. I should've called it
> >>> out specifically in the change log. Sorry for the inconvenience.
> >>
> >> 1. so just squeeze that change into second patch and no need to ask for
> >> re-review
> >
> > That's a fair point. I will be more mindful of the review overhead
> > going forward.
> >
> >> 2. You did not read my complain fully, look:
> >>
> >>>
> >>> Regards,
> >>> Roy Luo
> >>>
> >>>>
> >>>> <form letter>
> >>>> This is a friendly reminder during the review process.
> >>>>
> >>>> It looks like you received a tag and forgot to add it.
> >>>>
> >>>> If you do not know the process, here is a short explanation:
> >>>> Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
> >>>> of patchset, under or above your Signed-off-by tag, unless patch changed
> >>>> significantly (e.g. new properties added to the DT bindings). Tag is
> >>>> "received", when provided in a message replied to you on the mailing
> >>>> list. Tools like b4 can help here. However, there's no need to repost
> >>>> patches *only* to add the tags. The upstream maintainer will do that for
> >>>> tags received on the version they apply.
> >>>>
> >>>> Please read:
> >>>> https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577
> >>>>
> >>>> If a tag was not added on purpose, please state why and what changed.
> >>
> >> Where did you address this? You dropped the tag silently.
> >
> > Why: a new file is being modified.
> > What changed: MAINTAINER
> > What's not changed:
> > Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
>
> I don't know if you still did not get the problem or you think that I
> really need that clear answer. So no, I do not need that clear answer, I
> understood with first reply, but you kept explaining instead of
> admitting that your changelog needs fixes. So I still do not believe you
> understood the problem here and you might repeat the mistake.

I admitted that my changelog needs fixes in my first reply.
"I should've called it out specifically in the change log. Sorry for the
inconvenience.".
Maybe you think I didn't read through because my reply was placed
before the <form letter> section, but that's a misunderstanding.
I did read through the paragraph, that's why I mentioned the
changelog in my first reply.

I also misunderstood your question of "Where did you address
this?". If you were asking where this should have been addressed,
obviously the answer is to address it in the changelog,
but I thought that was already made clear in the first reply and
you might be asking for a clear answer.

>
> I think you need someone in Google to coach in this process, because I
> even gave you the exact link describing the process and what was
> expected. I even pointed specific paragraph, so you don't need to read
> entire file!

I appreciate you pointing out the specific paragraph, I understand
you're going above and beyond here. I did read and understand
what should've been done instead for this patch.

>
> I assume you understood what should be done instead in this patchset.
> Anyway, my previous tag applies if there were no bindings changes, but I
> wasted too much time here to care anymore. The expectation from big
> companies is they do not ask community to coach on basic submission
> process. It's quite unfair to my spare, personal time after work,
> considering how much big company is making. Big company should invest in
> this coaching.
>
>
> Best regards,
> Krzysztof

Thank you for the feedback. I understand your frustration, and I
apologize for taking up your time. I will be sure to be more thorough
in the future.

Thanks,
Roy Luo

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Roy Luo]

On Fri, Dec 5, 2025 at 12:18 PM Roy Luo <royluo@google.com> wrote:
>
> On Fri, Dec 5, 2025 at 11:26 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > I assume you understood what should be done instead in this patchset.
> > Anyway, my previous tag applies if there were no bindings changes, but I
> > wasted too much time here to care anymore. The expectation from big
> > companies is they do not ask community to coach on basic submission
> > process. It's quite unfair to my spare, personal time after work,
> > considering how much big company is making. Big company should invest in
> > this coaching.
> >
> >
> > Best regards,
> > Krzysztof
>
> Thank you for the feedback. I understand your frustration, and I
> apologize for taking up your time. I will be sure to be more thorough
> in the future.
>
> Thanks,
> Roy Luo

To confirm my takeaway: for this patch, the changes I introduced
were not significant enough to remove your 'Reviewed-by' tag,
and I should have kept it. Moving forward, I will calibrate my
criteria for what changes are considered 'significant' (essentially
any changes to binding), and more importantly, always document
the rationale for dropping or keeping tags in the changelog when
I make non-trivial changes to patches.

I plan to send a new version for this patchset and the controller
patchset [1] next week with your tag re-added, please let me
know if you disagree.

[1] https://lore.kernel.org/linux-usb/20251205-controller-v9-0-9f158b18f979@google.com

Thanks,
Roy Luo

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Krzysztof Kozlowski]

On 05/12/2025 21:18, Roy Luo wrote:
> On Fri, Dec 5, 2025 at 11:26 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 05/12/2025 20:11, Roy Luo wrote:
>>> On Fri, Dec 5, 2025 at 10:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>
>>>> On 05/12/2025 19:47, Roy Luo wrote:
>>>>> On Fri, Dec 5, 2025 at 9:13 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>>>
>>>>>> On 05/12/2025 04:54, Roy Luo wrote:
>>>>>>> Document the device tree bindings for the USB PHY interfaces integrated
>>>>>>> with the DWC3 controller on Google Tensor SoCs, starting with G5
>>>>>>> generation (Laguna). The USB PHY on Tensor G5 includes two integrated
>>>>>>> Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
>>>>>>> PHY IP.
>>>>>>>
>>>>>>> Due to a complete architectural overhaul in the Google Tensor G5, the
>>>>>>> existing Samsung/Exynos USB PHY binding for older generations of Google
>>>>>>> silicons such as gs101 are no longer compatible, necessitating this new
>>>>>>> device tree binding.
>>>>>>>
>>>>>>> Signed-off-by: Roy Luo <royluo@google.com>
>>>>>>
>>>>>> Why intentionally dropping the tag? How are you handling this patchset?
>>>>>> Rewrite every time from scratch?
>>>>>
>>>>> Hi Krzysztof,
>>>>>
>>>>> I dropped the tag because a new file is being modified in this version,
>>>>> Although it's just MAINTAINER file but I thought you might also want
>>>>> to take a look. I wasn't sure if modifying a new file qualifies as
>>>>> "substantial" so I erred on the side of caution. I should've called it
>>>>> out specifically in the change log. Sorry for the inconvenience.
>>>>
>>>> 1. so just squeeze that change into second patch and no need to ask for
>>>> re-review
>>>
>>> That's a fair point. I will be more mindful of the review overhead
>>> going forward.
>>>
>>>> 2. You did not read my complain fully, look:
>>>>
>>>>>
>>>>> Regards,
>>>>> Roy Luo
>>>>>
>>>>>>
>>>>>> <form letter>
>>>>>> This is a friendly reminder during the review process.
>>>>>>
>>>>>> It looks like you received a tag and forgot to add it.
>>>>>>
>>>>>> If you do not know the process, here is a short explanation:
>>>>>> Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
>>>>>> of patchset, under or above your Signed-off-by tag, unless patch changed
>>>>>> significantly (e.g. new properties added to the DT bindings). Tag is
>>>>>> "received", when provided in a message replied to you on the mailing
>>>>>> list. Tools like b4 can help here. However, there's no need to repost
>>>>>> patches *only* to add the tags. The upstream maintainer will do that for
>>>>>> tags received on the version they apply.
>>>>>>
>>>>>> Please read:
>>>>>> https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577
>>>>>>
>>>>>> If a tag was not added on purpose, please state why and what changed.
>>>>
>>>> Where did you address this? You dropped the tag silently.
>>>
>>> Why: a new file is being modified.
>>> What changed: MAINTAINER
>>> What's not changed:
>>> Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
>>
>> I don't know if you still did not get the problem or you think that I
>> really need that clear answer. So no, I do not need that clear answer, I
>> understood with first reply, but you kept explaining instead of
>> admitting that your changelog needs fixes. So I still do not believe you
>> understood the problem here and you might repeat the mistake.
> 
> I admitted that my changelog needs fixes in my first reply.
> "I should've called it out specifically in the change log. Sorry for the
> inconvenience.".
> Maybe you think I didn't read through because my reply was placed
> before the <form letter> section, but that's a misunderstanding.
> I did read through the paragraph, that's why I mentioned the
> changelog in my first reply.
> 
> I also misunderstood your question of "Where did you address
> this?". If you were asking where this should have been addressed,
> obviously the answer is to address it in the changelog,
> but I thought that was already made clear in the first reply and
> you might be asking for a clear answer.
> 
>>
>> I think you need someone in Google to coach in this process, because I
>> even gave you the exact link describing the process and what was
>> expected. I even pointed specific paragraph, so you don't need to read
>> entire file!
> 
> I appreciate you pointing out the specific paragraph, I understand
> you're going above and beyond here. I did read and understand
> what should've been done instead for this patch.


Ack, understood. Apologies for my previous over agitated email. That was
not professional of me.

Best regards,
Krzysztof

Re: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Krzysztof Kozlowski]

On Fri, Dec 05, 2025 at 03:54:11AM +0000, Roy Luo wrote:
> Document the device tree bindings for the USB PHY interfaces integrated
> with the DWC3 controller on Google Tensor SoCs, starting with G5
> generation (Laguna). The USB PHY on Tensor G5 includes two integrated
> Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
> PHY IP.
> 
> Due to a complete architectural overhaul in the Google Tensor G5, the
> existing Samsung/Exynos USB PHY binding for older generations of Google
> silicons such as gs101 are no longer compatible, necessitating this new
> device tree binding.
> 
> Signed-off-by: Roy Luo <royluo@google.com>
> ---
>  .../bindings/phy/google,lga-usb-phy.yaml           | 133 +++++++++++++++++++++
>  MAINTAINERS                                        |   1 +
>  2 files changed, 134 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof