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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2025 15:23:42.1858 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: adf91eb1-faea-4be0-a515-08de39926ef6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001B6.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8350 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251212_072353_142949_5CCA9FEE X-CRM114-Status: GOOD ( 10.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Sascha Bischoff The VGIC-v3 code relied on hand-written definitions for the ICH_VMCR_EL2 register. This register, and the associated fields, is now generated as part of the sysreg framework. Move to using the generated definitions instead of the hand-written ones. There are no functional changes as part of this change. Signed-off-by: Sascha Bischoff --- arch/arm64/include/asm/sysreg.h | 21 --------- arch/arm64/kvm/hyp/vgic-v3-sr.c | 64 ++++++++++++---------------- arch/arm64/kvm/vgic/vgic-v3-nested.c | 8 ++-- arch/arm64/kvm/vgic/vgic-v3.c | 48 ++++++++++----------- 4 files changed, 54 insertions(+), 87 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 9df51accbb025..b3b8b8cd7bf1e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -560,7 +560,6 @@ #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) -#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) =20 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) @@ -988,26 +987,6 @@ #define ICH_LR_PRIORITY_SHIFT 48 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) =20 -/* ICH_VMCR_EL2 bit definitions */ -#define ICH_VMCR_ACK_CTL_SHIFT 2 -#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) -#define ICH_VMCR_FIQ_EN_SHIFT 3 -#define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) -#define ICH_VMCR_CBPR_SHIFT 4 -#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) -#define ICH_VMCR_EOIM_SHIFT 9 -#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) -#define ICH_VMCR_BPR1_SHIFT 18 -#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) -#define ICH_VMCR_BPR0_SHIFT 21 -#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) -#define ICH_VMCR_PMR_SHIFT 24 -#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) -#define ICH_VMCR_ENG0_SHIFT 0 -#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) -#define ICH_VMCR_ENG1_SHIFT 1 -#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) - /* * Permission Indirection Extension (PIE) permission encodings. * Encodings with the _O suffix, have overlays applied (Permission Overlay= Extension). diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-s= r.c index 0b670a033fd87..24a2074f3a8cf 100644 --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c @@ -569,11 +569,11 @@ static int __vgic_v3_highest_priority_lr(struct kvm_v= cpu *vcpu, u32 vmcr, continue; =20 /* Group-0 interrupt, but Group-0 disabled? */ - if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK)) + if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_EL2_VENG0_MASK)) continue; =20 /* Group-1 interrupt, but Group-1 disabled? */ - if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK)) + if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_EL2_VENG1_MASK)) continue; =20 /* Not the highest priority? */ @@ -646,19 +646,19 @@ static int __vgic_v3_get_highest_active_priority(void= ) =20 static unsigned int __vgic_v3_get_bpr0(u32 vmcr) { - return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; + return FIELD_GET(ICH_VMCR_EL2_VBPR0, vmcr); } =20 static unsigned int __vgic_v3_get_bpr1(u32 vmcr) { unsigned int bpr; =20 - if (vmcr & ICH_VMCR_CBPR_MASK) { + if (vmcr & ICH_VMCR_EL2_VCBPR_MASK) { bpr =3D __vgic_v3_get_bpr0(vmcr); if (bpr < 7) bpr++; } else { - bpr =3D (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; + bpr =3D FIELD_GET(ICH_VMCR_EL2_VBPR1, vmcr); } =20 return bpr; @@ -758,7 +758,7 @@ static void __vgic_v3_read_iar(struct kvm_vcpu *vcpu, u= 32 vmcr, int rt) if (grp !=3D !!(lr_val & ICH_LR_GROUP)) goto spurious; =20 - pmr =3D (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; + pmr =3D FIELD_GET(ICH_VMCR_EL2_VPMR, vmcr); lr_prio =3D (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT; if (pmr <=3D lr_prio) goto spurious; @@ -806,7 +806,7 @@ static int ___vgic_v3_write_dir(struct kvm_vcpu *vcpu, = u32 vmcr, int rt) int lr; =20 /* EOImode =3D=3D 0, nothing to be done here */ - if (!(vmcr & ICH_VMCR_EOIM_MASK)) + if (!FIELD_GET(ICH_VMCR_EL2_VEOIM_MASK, vmcr)) return 1; =20 /* No deactivate to be performed on an LPI */ @@ -849,7 +849,7 @@ static void __vgic_v3_write_eoir(struct kvm_vcpu *vcpu,= u32 vmcr, int rt) } =20 /* EOImode =3D=3D 1 and not an LPI, nothing to be done here */ - if ((vmcr & ICH_VMCR_EOIM_MASK) && !(vid >=3D VGIC_MIN_LPI)) + if (FIELD_GET(ICH_VMCR_EL2_VEOIM_MASK, vmcr) && !(vid >=3D VGIC_MIN_LPI)) return; =20 lr_prio =3D (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT; @@ -865,12 +865,12 @@ static void __vgic_v3_write_eoir(struct kvm_vcpu *vcp= u, u32 vmcr, int rt) =20 static void __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt= ) { - vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK)); + vcpu_set_reg(vcpu, rt, !!FIELD_GET(ICH_VMCR_EL2_VENG0_MASK, vmcr)); } =20 static void __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt= ) { - vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK)); + vcpu_set_reg(vcpu, rt, !!FIELD_GET(ICH_VMCR_EL2_VENG1_MASK, vmcr)); } =20 static void __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int r= t) @@ -878,9 +878,9 @@ static void __vgic_v3_write_igrpen0(struct kvm_vcpu *vc= pu, u32 vmcr, int rt) u64 val =3D vcpu_get_reg(vcpu, rt); =20 if (val & 1) - vmcr |=3D ICH_VMCR_ENG0_MASK; + vmcr |=3D ICH_VMCR_EL2_VENG0_MASK; else - vmcr &=3D ~ICH_VMCR_ENG0_MASK; + vmcr &=3D ~ICH_VMCR_EL2_VENG0_MASK; =20 __vgic_v3_write_vmcr(vmcr); } @@ -890,9 +890,9 @@ static void __vgic_v3_write_igrpen1(struct kvm_vcpu *vc= pu, u32 vmcr, int rt) u64 val =3D vcpu_get_reg(vcpu, rt); =20 if (val & 1) - vmcr |=3D ICH_VMCR_ENG1_MASK; + vmcr |=3D ICH_VMCR_EL2_VENG1_MASK; else - vmcr &=3D ~ICH_VMCR_ENG1_MASK; + vmcr &=3D ~ICH_VMCR_EL2_VENG1_MASK; =20 __vgic_v3_write_vmcr(vmcr); } @@ -916,10 +916,8 @@ static void __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu= , u32 vmcr, int rt) if (val < bpr_min) val =3D bpr_min; =20 - val <<=3D ICH_VMCR_BPR0_SHIFT; - val &=3D ICH_VMCR_BPR0_MASK; - vmcr &=3D ~ICH_VMCR_BPR0_MASK; - vmcr |=3D val; + vmcr &=3D ~ICH_VMCR_EL2_VBPR0_MASK; + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VBPR0, val); =20 __vgic_v3_write_vmcr(vmcr); } @@ -929,17 +927,15 @@ static void __vgic_v3_write_bpr1(struct kvm_vcpu *vcp= u, u32 vmcr, int rt) u64 val =3D vcpu_get_reg(vcpu, rt); u8 bpr_min =3D __vgic_v3_bpr_min(); =20 - if (vmcr & ICH_VMCR_CBPR_MASK) + if (FIELD_GET(ICH_VMCR_EL2_VCBPR_MASK, val)) return; =20 /* Enforce BPR limiting */ if (val < bpr_min) val =3D bpr_min; =20 - val <<=3D ICH_VMCR_BPR1_SHIFT; - val &=3D ICH_VMCR_BPR1_MASK; - vmcr &=3D ~ICH_VMCR_BPR1_MASK; - vmcr |=3D val; + vmcr &=3D ~ICH_VMCR_EL2_VBPR1_MASK; + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VBPR1, val); =20 __vgic_v3_write_vmcr(vmcr); } @@ -1029,19 +1025,15 @@ static void __vgic_v3_read_hppir(struct kvm_vcpu *v= cpu, u32 vmcr, int rt) =20 static void __vgic_v3_read_pmr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) { - vmcr &=3D ICH_VMCR_PMR_MASK; - vmcr >>=3D ICH_VMCR_PMR_SHIFT; - vcpu_set_reg(vcpu, rt, vmcr); + vcpu_set_reg(vcpu, rt, FIELD_GET(ICH_VMCR_EL2_VPMR, vmcr)); } =20 static void __vgic_v3_write_pmr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) { u32 val =3D vcpu_get_reg(vcpu, rt); =20 - val <<=3D ICH_VMCR_PMR_SHIFT; - val &=3D ICH_VMCR_PMR_MASK; - vmcr &=3D ~ICH_VMCR_PMR_MASK; - vmcr |=3D val; + vmcr &=3D ~ICH_VMCR_EL2_VPMR_MASK; + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VPMR, val); =20 write_gicreg(vmcr, ICH_VMCR_EL2); } @@ -1064,9 +1056,9 @@ static void __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu= , u32 vmcr, int rt) /* A3V */ val |=3D ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT; /* EOImode */ - val |=3D ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR= _EL1_EOImode_SHIFT; + val |=3D FIELD_GET(ICH_VMCR_EL2_VEOIM, vmcr) << ICC_CTLR_EL1_EOImode_SHIF= T; /* CBPR */ - val |=3D (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; + val |=3D FIELD_GET(ICH_VMCR_EL2_VCBPR, vmcr); =20 vcpu_set_reg(vcpu, rt, val); } @@ -1076,14 +1068,14 @@ static void __vgic_v3_write_ctlr(struct kvm_vcpu *v= cpu, u32 vmcr, int rt) u32 val =3D vcpu_get_reg(vcpu, rt); =20 if (val & ICC_CTLR_EL1_CBPR_MASK) - vmcr |=3D ICH_VMCR_CBPR_MASK; + vmcr |=3D ICH_VMCR_EL2_VCBPR_MASK; else - vmcr &=3D ~ICH_VMCR_CBPR_MASK; + vmcr &=3D ~ICH_VMCR_EL2_VCBPR_MASK; =20 if (val & ICC_CTLR_EL1_EOImode_MASK) - vmcr |=3D ICH_VMCR_EOIM_MASK; + vmcr |=3D ICH_VMCR_EL2_VEOIM_MASK; else - vmcr &=3D ~ICH_VMCR_EOIM_MASK; + vmcr &=3D ~ICH_VMCR_EL2_VEOIM_MASK; =20 write_gicreg(vmcr, ICH_VMCR_EL2); } diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgi= c-v3-nested.c index 61b44f3f2bf14..c9e35ec671173 100644 --- a/arch/arm64/kvm/vgic/vgic-v3-nested.c +++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c @@ -202,16 +202,16 @@ u64 vgic_v3_get_misr(struct kvm_vcpu *vcpu) if ((hcr & ICH_HCR_EL2_NPIE) && !mi_state.pend) reg |=3D ICH_MISR_EL2_NP; =20 - if ((hcr & ICH_HCR_EL2_VGrp0EIE) && (vmcr & ICH_VMCR_ENG0_MASK)) + if ((hcr & ICH_HCR_EL2_VGrp0EIE) && (vmcr & ICH_VMCR_EL2_VENG0_MASK)) reg |=3D ICH_MISR_EL2_VGrp0E; =20 - if ((hcr & ICH_HCR_EL2_VGrp0DIE) && !(vmcr & ICH_VMCR_ENG0_MASK)) + if ((hcr & ICH_HCR_EL2_VGrp0DIE) && !(vmcr & ICH_VMCR_EL2_VENG0_MASK)) reg |=3D ICH_MISR_EL2_VGrp0D; =20 - if ((hcr & ICH_HCR_EL2_VGrp1EIE) && (vmcr & ICH_VMCR_ENG1_MASK)) + if ((hcr & ICH_HCR_EL2_VGrp1EIE) && (vmcr & ICH_VMCR_EL2_VENG1_MASK)) reg |=3D ICH_MISR_EL2_VGrp1E; =20 - if ((hcr & ICH_HCR_EL2_VGrp1DIE) && !(vmcr & ICH_VMCR_ENG1_MASK)) + if ((hcr & ICH_HCR_EL2_VGrp1DIE) && !(vmcr & ICH_VMCR_EL2_VENG1_MASK)) reg |=3D ICH_MISR_EL2_VGrp1D; =20 return reg; diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index 1d6dd1b545bdd..2afc041672311 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -41,9 +41,9 @@ void vgic_v3_configure_hcr(struct kvm_vcpu *vcpu, if (!als->nr_sgi) cpuif->vgic_hcr |=3D ICH_HCR_EL2_vSGIEOICount; =20 - cpuif->vgic_hcr |=3D (cpuif->vgic_vmcr & ICH_VMCR_ENG0_MASK) ? + cpuif->vgic_hcr |=3D (cpuif->vgic_vmcr & ICH_VMCR_EL2_VENG0_MASK) ? ICH_HCR_EL2_VGrp0DIE : ICH_HCR_EL2_VGrp0EIE; - cpuif->vgic_hcr |=3D (cpuif->vgic_vmcr & ICH_VMCR_ENG1_MASK) ? + cpuif->vgic_hcr |=3D (cpuif->vgic_vmcr & ICH_VMCR_EL2_VENG1_MASK) ? ICH_HCR_EL2_VGrp1DIE : ICH_HCR_EL2_VGrp1EIE; =20 /* @@ -215,7 +215,7 @@ void vgic_v3_deactivate(struct kvm_vcpu *vcpu, u64 val) * We only deal with DIR when EOIMode=3D=3D1, and only for SGI, * PPI or SPI. */ - if (!(cpuif->vgic_vmcr & ICH_VMCR_EOIM_MASK) || + if (!(cpuif->vgic_vmcr & ICH_VMCR_EL2_VEOIM_MASK) || val >=3D vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS) return; =20 @@ -408,25 +408,23 @@ void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct v= gic_vmcr *vmcrp) u32 vmcr; =20 if (model =3D=3D KVM_DEV_TYPE_ARM_VGIC_V2) { - vmcr =3D (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) & - ICH_VMCR_ACK_CTL_MASK; - vmcr |=3D (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) & - ICH_VMCR_FIQ_EN_MASK; + vmcr =3D FIELD_PREP(ICH_VMCR_EL2_VAckCtl, vmcrp->ackctl); + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VFIQEn, vmcrp->fiqen); } else { /* * When emulating GICv3 on GICv3 with SRE=3D1 on the * VFIQEn bit is RES1 and the VAckCtl bit is RES0. */ - vmcr =3D ICH_VMCR_FIQ_EN_MASK; + vmcr =3D ICH_VMCR_EL2_VFIQEn_MASK; } =20 - vmcr |=3D (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK; - vmcr |=3D (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK; - vmcr |=3D (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK; - vmcr |=3D (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK; - vmcr |=3D (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; - vmcr |=3D (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK; - vmcr |=3D (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK; + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VCBPR, vmcrp->cbpr); + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VEOIM, vmcrp->eoim); + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VBPR1, vmcrp->abpr); + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VBPR0, vmcrp->bpr); + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VPMR, vmcrp->pmr); + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VENG0, vmcrp->grpen0); + vmcr |=3D FIELD_PREP(ICH_VMCR_EL2_VENG1, vmcrp->grpen1); =20 cpu_if->vgic_vmcr =3D vmcr; } @@ -440,10 +438,8 @@ void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vg= ic_vmcr *vmcrp) vmcr =3D cpu_if->vgic_vmcr; =20 if (model =3D=3D KVM_DEV_TYPE_ARM_VGIC_V2) { - vmcrp->ackctl =3D (vmcr & ICH_VMCR_ACK_CTL_MASK) >> - ICH_VMCR_ACK_CTL_SHIFT; - vmcrp->fiqen =3D (vmcr & ICH_VMCR_FIQ_EN_MASK) >> - ICH_VMCR_FIQ_EN_SHIFT; + vmcrp->ackctl =3D FIELD_GET(ICH_VMCR_EL2_VAckCtl, vmcr); + vmcrp->fiqen =3D FIELD_GET(ICH_VMCR_EL2_VFIQEn, vmcr); } else { /* * When emulating GICv3 on GICv3 with SRE=3D1 on the @@ -453,13 +449,13 @@ void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct v= gic_vmcr *vmcrp) vmcrp->ackctl =3D 0; } =20 - vmcrp->cbpr =3D (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; - vmcrp->eoim =3D (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT; - vmcrp->abpr =3D (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; - vmcrp->bpr =3D (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; - vmcrp->pmr =3D (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; - vmcrp->grpen0 =3D (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT; - vmcrp->grpen1 =3D (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT; + vmcrp->cbpr =3D FIELD_GET(ICH_VMCR_EL2_VCBPR, vmcr); + vmcrp->eoim =3D FIELD_GET(ICH_VMCR_EL2_VEOIM, vmcr); + vmcrp->abpr =3D FIELD_GET(ICH_VMCR_EL2_VBPR1, vmcr); + vmcrp->bpr =3D FIELD_GET(ICH_VMCR_EL2_VBPR0, vmcr); + vmcrp->pmr =3D FIELD_GET(ICH_VMCR_EL2_VPMR, vmcr); + vmcrp->grpen0 =3D FIELD_GET(ICH_VMCR_EL2_VENG0, vmcr); + vmcrp->grpen1 =3D FIELD_GET(ICH_VMCR_EL2_VENG1, vmcr); } =20 #define INITIAL_PENDBASER_VALUE \ --=20 2.34.1