From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31ADFD59D99 for ; Mon, 15 Dec 2025 03:50:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Lgne43yw7zvx4ot4RAuH5mrg8q7mjaZX4v2mJkJp9Rg=; b=JFhOf+5fdDyaIFj7UV8RlGEurz uNgnHDTbH3fwhMToKhPyih6KlEk/TIQma5yFwWLsa8wniy/jJHBzJ+FJ82+MKwASLUAuExCXrwVPM coD4C9PUk+Gzo/yJ6lmyfL0ITiX9EA5D7oyO66Z0d0v5Pz9CHZvPlGmlTqFyn7Aje4bNlMnbpi9lu iwhuFWkHRUgzxnW0Xu1kAPfb18lc+j+5pcyB0Dm5QSi3/nitCrq8NDdcQ+hvDJp9uWCFrVxqdStNp RZvgHci4sYutksslBs2eKUcBHkQJoxPnEFr8MZ0MlN+uG5IgS/UMw4vw80sj0f02Bb+Z2v9/sxz2c ZqJWa2zA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vUzbg-00000002zze-1XI9; Mon, 15 Dec 2025 03:50:44 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vUzb1-00000002zfd-35vx; Mon, 15 Dec 2025 03:50:05 +0000 X-UUID: 1f604b8cd96911f09f706fa2197c6ceb-20251214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Lgne43yw7zvx4ot4RAuH5mrg8q7mjaZX4v2mJkJp9Rg=; b=DMgJPBrwQQQIUSzLFLvxpETudiVqD+vZRVtFX6KwmWCTwZnCWiM1LRddeIrLwQHdS+aYb8dMaiJnsueoSZ48aUvFxI7HSZWJEue38MjDgxo6lbZ9aRICou3DsdIiz6mO521WkbGj8LiEc65o6CLtCWPrrTg+GDO6jQwwg2pQY/4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:9437f4ed-b33a-4128-92b7-55a99a32bfec,IP:0,UR L:0,TC:0,Content:-25,EDM:-20,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-45 X-CID-META: VersionHash:a9d874c,CLOUDID:59d0c402-1fa9-44eb-b231-4afc61466396,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:1,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 1f604b8cd96911f09f706fa2197c6ceb-20251214 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1645123124; Sun, 14 Dec 2025 20:49:56 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 15 Dec 2025 11:49:52 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 15 Dec 2025 11:49:52 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v4 11/21] clk: mediatek: Add MT8189 dvfsrc clock support Date: Mon, 15 Dec 2025 11:49:20 +0800 Message-ID: <20251215034944.2973003-12-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> References: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251214_195003_857539_3C9CE9FD X-CRM114-Status: GOOD ( 17.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Irving-CH Lin Add support for the MT8189 dvfsrc clock controller, which provides clock gate control for dram dvfs. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 10 +++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dvfsrc.c | 54 ++++++++++++++++++++++++ 3 files changed, 65 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-dvfsrc.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index c707b224dccd..76c9391bee69 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -860,6 +860,16 @@ config COMMON_CLK_MT8189_DBGAO vcore debug system clocks. If you want to control its clocks, say Y or M to include this driver in your kernel build. +config COMMON_CLK_MT8189_DVFSRC + tristate "Clock driver for MediaTek MT8189 dvfsrc" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the dvfsrc + on MediaTek MT8189 SoCs. This includes enabling and disabling + vcore dvfs clocks. If you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index eabe2cab4b8d..3a8dad865c97 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -128,6 +128,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o obj-$(CONFIG_COMMON_CLK_MT8189_CAM) += clk-mt8189-cam.o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o +obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dvfsrc.c b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c new file mode 100644 index 000000000000..f8ab656af6e6 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs dvfsrc_top_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +#define GATE_DVFSRC_TOP_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &dvfsrc_top_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, _flags) + +static const struct mtk_gate dvfsrc_top_clks[] = { + GATE_DVFSRC_TOP_FLAGS(CLK_DVFSRC_TOP_DVFSRC_EN, "dvfsrc_dvfsrc_en", + "clk26m", 0, CLK_IS_CRITICAL), +}; + +static const struct mtk_clk_desc dvfsrc_top_mcd = { + .clks = dvfsrc_top_clks, + .num_clks = ARRAY_SIZE(dvfsrc_top_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dvfsrc[] = { + { .compatible = "mediatek,mt8189-dvfsrc-top", .data = &dvfsrc_top_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dvfsrc); + +static struct platform_driver clk_mt8189_dvfsrc_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8189-dvfsrc", + .of_match_table = of_match_clk_mt8189_dvfsrc, + }, +}; + +module_platform_driver(clk_mt8189_dvfsrc_drv); +MODULE_DESCRIPTION("MediaTek MT8189 dvfsrc clocks driver"); +MODULE_LICENSE("GPL"); -- 2.45.2