From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F623D41D74 for ; Mon, 15 Dec 2025 03:52:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Gy92obh8Ukix7BUauEXFxVr7F2CXq0uko5Tmi9maIEg=; b=brks5FbipImQbXMFU34aNVBomE H49TTTBO0/tqQvMPuYWPbaUAR2jse2cwPRf/2HX+l5VjFAwEBjZw9v8hDt1MXWgaB5NywUigt8bkW ckRYKw9sL1/9Lydt0OtYwB1cUXQGbivPHKtnMXU982a1azi2Clrnnac1HqeDJ2fEiEIob5ceC9V+u tu2kBuQBFacqauJZHS5g4U+k29dlb/nzXEcDzS+2tWGsLJk/wEie+RFcf9TIhzSube9qKI+ISpwTy hYfTKpjCazEXNvOS5pVUGW/0J5VpuadzAcJUvIVrJHLBDXOxrp/5//h84autn1eSELdwyvboHJExB cCawkqWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vUzch-000000030Za-2X3e; Mon, 15 Dec 2025 03:51:47 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vUzb3-00000002zeU-1L9E; Mon, 15 Dec 2025 03:50:12 +0000 X-UUID: 1f0a1ad2d96911f0a52f393f94899d25-20251214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Gy92obh8Ukix7BUauEXFxVr7F2CXq0uko5Tmi9maIEg=; b=MAw9v5ImBzkuZvnPKf8aIkAdkLDqKfY1OE3QxYMwHqBF2pYda1eaVKOZqYzk8m+Z7W8c9oe2NJlSP8HUEiV5Hx2yEuDlUey3ab4VEy5XJ5WXEs9o5mCX0cZuLj4NSinWWflJ+Buce+ThW28hoUsq0NsFFue/SA3Nb+8DWnRXLP4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:ce1d5e83-96c9-4e2b-8c62-9a9de4e0089e,IP:0,UR L:0,TC:0,Content:-25,EDM:-20,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-45 X-CID-META: VersionHash:a9d874c,CLOUDID:cd078528-e3a2-4f78-a442-8c73c4eb9e9d,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:1,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 1f0a1ad2d96911f0a52f393f94899d25-20251214 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1021903179; Sun, 14 Dec 2025 20:49:56 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 15 Dec 2025 11:49:53 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 15 Dec 2025 11:49:53 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v4 15/21] clk: mediatek: Add MT8189 mfg clock support Date: Mon, 15 Dec 2025 11:49:24 +0800 Message-ID: <20251215034944.2973003-16-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> References: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251214_195005_456301_2E23AB96 X-CRM114-Status: GOOD ( 17.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Irving-CH Lin Add support for the MT8189 mfg clock controller, which provides clock gate control for the GPU. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 11 ++++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-mfg.c | 53 +++++++++++++++++++++++++++ 3 files changed, 65 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-mfg.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index ef962f5816a8..316d010b503a 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -906,6 +906,17 @@ config COMMON_CLK_MT8189_MDPSYS chipset, ensuring that the display system operates efficiently and effectively. +config COMMON_CLK_MT8189_MFG + tristate "Clock driver for MediaTek MT8189 mfg" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this option to support the manufacturing clocks for the MediaTek + MT8189 chipset. This driver provides the necessary clock framework + integration for manufacturing tests and operations that are specific to + the MT8189 chipset. Enabling this will allow the manufacturing mode of + the chipset to function correctly with the appropriate clock settings. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 9b23e4c5e019..07f11760cf68 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -132,6 +132,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8189_IMG) += clk-mt8189-img.o obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) += clk-mt8189-mdpsys.o +obj-$(CONFIG_COMMON_CLK_MT8189_MFG) += clk-mt8189-mfg.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-mfg.c b/drivers/clk/mediatek/clk-mt8189-mfg.c new file mode 100644 index 000000000000..a09bf8f2e017 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-mfg.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mfg_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate mfg_clks[] = { + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel_mfgpll", 0), +}; + +static const struct mtk_clk_desc mfg_mcd = { + .clks = mfg_clks, + .num_clks = ARRAY_SIZE(mfg_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_mfg[] = { + { .compatible = "mediatek,mt8189-mfgcfg", .data = &mfg_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_mfg); + +static struct platform_driver clk_mt8189_mfg_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8189-mfg", + .of_match_table = of_match_clk_mt8189_mfg, + }, +}; + +module_platform_driver(clk_mt8189_mfg_drv); +MODULE_DESCRIPTION("MediaTek MT8189 mfg clocks driver"); +MODULE_LICENSE("GPL"); -- 2.45.2