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Thu, 18 Dec 2025 21:37:16 -0800 (PST) Received: from Barrys-MBP.hub ([47.72.129.29]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d4d895sm9930215ad.54.2025.12.18.21.37.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Dec 2025 21:37:15 -0800 (PST) From: Barry Song <21cnbao@gmail.com> To: catalin.marinas@arm.com, m.szyprowski@samsung.com, robin.murphy@arm.com, will@kernel.org Subject: [PATCH 1/6] arm64: Provide dcache_by_myline_op_nosync helper Date: Fri, 19 Dec 2025 13:36:53 +0800 Message-Id: <20251219053658.84978-2-21cnbao@gmail.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20251219053658.84978-1-21cnbao@gmail.com> References: <20251219053658.84978-1-21cnbao@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251218_213718_021751_D7519916 X-CRM114-Status: GOOD ( 12.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: v-songbaohua@oppo.com, zhengtangquan@oppo.com, ryan.roberts@arm.com, anshuman.khandual@arm.com, maz@kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, surenb@google.com, ardb@kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Barry Song dcache_by_myline_op ensures completion of the data cache operations for a region, while dcache_by_myline_op_nosync only issues them without waiting. This enables deferred synchronization so completion for multiple regions can be handled together later. Cc: Catalin Marinas Cc: Will Deacon Cc: Marek Szyprowski Cc: Robin Murphy Cc: Ada Couprie Diaz Cc: Ard Biesheuvel Cc: Marc Zyngier Cc: Anshuman Khandual Cc: Ryan Roberts Cc: Suren Baghdasaryan Cc: Tangquan Zheng Signed-off-by: Barry Song --- arch/arm64/include/asm/assembler.h | 79 ++++++++++++++++++++++-------- 1 file changed, 59 insertions(+), 20 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index f0ca7196f6fa..7d84a9ca7880 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -366,22 +366,7 @@ alternative_else alternative_endif .endm -/* - * Macro to perform a data cache maintenance for the interval - * [start, end) with dcache line size explicitly provided. - * - * op: operation passed to dc instruction - * domain: domain used in dsb instruction - * start: starting virtual address of the region - * end: end virtual address of the region - * linesz: dcache line size - * fixup: optional label to branch to on user fault - * Corrupts: start, end, tmp - */ - .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup - sub \tmp, \linesz, #1 - bic \start, \start, \tmp -.Ldcache_op\@: + .macro __dcache_op_line op, start .ifc \op, cvau __dcache_op_workaround_clean_cache \op, \start .else @@ -399,14 +384,54 @@ alternative_endif .endif .endif .endif - add \start, \start, \linesz - cmp \start, \end - b.lo .Ldcache_op\@ - dsb \domain + .endm + +/* + * Macro to perform a data cache maintenance for the interval + * [start, end) with dcache line size explicitly provided. + * + * op: operation passed to dc instruction + * domain: domain used in dsb instruction + * start: starting virtual address of the region + * end: end virtual address of the region + * linesz: dcache line size + * fixup: optional label to branch to on user fault + * Corrupts: start, end, tmp + */ + .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup + sub \tmp, \linesz, #1 + bic \start, \start, \tmp +.Ldcache_op\@: + __dcache_op_line \op, \start + add \start, \start, \linesz + cmp \start, \end + b.lo .Ldcache_op\@ + dsb \domain _cond_uaccess_extable .Ldcache_op\@, \fixup .endm +/* + * Macro to perform a data cache maintenance for the interval + * [start, end) with dcache line size explicitly provided. + * It won't wait for the completion of the dc operation. + * + * op: operation passed to dc instruction + * start: starting virtual address of the region + * end: end virtual address of the region + * linesz: dcache line size + * Corrupts: start, end, tmp + */ + .macro dcache_by_myline_op_nosync op, start, end, linesz, tmp + sub \tmp, \linesz, #1 + bic \start, \start, \tmp +.Ldcache_op\@: + __dcache_op_line \op, \start + add \start, \start, \linesz + cmp \start, \end + b.lo .Ldcache_op\@ + .endm + /* * Macro to perform a data cache maintenance for the interval * [start, end) @@ -423,6 +448,20 @@ alternative_endif dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup .endm +/* + * Macro to perform a data cache maintenance for the interval + * [start, end). It won’t wait for the dc operation to complete. + * + * op: operation passed to dc instruction + * start: starting virtual address of the region + * end: end virtual address of the region + * Corrupts: start, end, tmp1, tmp2 + */ + .macro dcache_by_line_op_nosync op, start, end, tmp1, tmp2 + dcache_line_size \tmp1, \tmp2 + dcache_by_myline_op_nosync \op, \start, \end, \tmp1, \tmp2 + .endm + /* * Macro to perform an instruction cache maintenance for the interval * [start, end) -- 2.39.3 (Apple Git-146)