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Sat, 20 Dec 2025 23:59:34 -0800 (PST) Received: from Barrys-MBP.hub ([47.72.129.29]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c1e79a17fdesm6226424a12.8.2025.12.20.23.59.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 20 Dec 2025 23:59:34 -0800 (PST) From: Barry Song <21cnbao@gmail.com> To: robin.murphy@arm.com Subject: [PATCH 3/6] arm64: Provide dcache_inval_poc_nosync helper Date: Sun, 21 Dec 2025 15:59:25 +0800 Message-Id: <20251221075925.65445-1-21cnbao@gmail.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <99bb1797-06ba-440d-b173-db62d5f54e08@arm.com> References: <99bb1797-06ba-440d-b173-db62d5f54e08@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251220_235936_274101_14D2F35F X-CRM114-Status: GOOD ( 16.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: v-songbaohua@oppo.com, zhengtangquan@oppo.com, ryan.roberts@arm.com, will@kernel.org, anshuman.khandual@arm.com, catalin.marinas@arm.com, 21cnbao@gmail.com, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, maz@kernel.org, surenb@google.com, ardb@kernel.org, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 19, 2025 at 8:50 PM Robin Murphy wrote: [...] > > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > > index 4a7c7e03785d..8c1043c9b9e5 100644 > > --- a/arch/arm64/mm/cache.S > > +++ b/arch/arm64/mm/cache.S > > @@ -132,17 +132,7 @@ alternative_else_nop_endif > >       ret > >   SYM_FUNC_END(dcache_clean_pou) > >   > > -/* > > - *   dcache_inval_poc(start, end) > > - * > > - *   Ensure that any D-cache lines for the interval [start, end) > > - *   are invalidated. Any partial lines at the ends of the interval are > > - *   also cleaned to PoC to prevent data loss. > > - * > > - *   - start   - kernel start address of region > > - *   - end     - kernel end address of region > > - */ > > -SYM_FUNC_START(__pi_dcache_inval_poc) > > +.macro _dcache_inval_poc_impl, do_sync > >       dcache_line_size x2, x3 > >       sub     x3, x2, #1 > >       tst     x1, x3                          // end cache line aligned? > > @@ -158,11 +148,42 @@ SYM_FUNC_START(__pi_dcache_inval_poc) > >   3:  add     x0, x0, x2 > >       cmp     x0, x1 > >       b.lo    2b > > +.if \do_sync > >       dsb     sy > > +.endif > > Similarly, don't bother with complication like this, just put the DSB in > the one place it needs to be. > Thanks, Robin — great suggestion. I assume it can be: diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 4a7c7e03785d..99a093d3aecb 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -132,17 +132,7 @@ alternative_else_nop_endif ret SYM_FUNC_END(dcache_clean_pou) -/* - * dcache_inval_poc(start, end) - * - * Ensure that any D-cache lines for the interval [start, end) - * are invalidated. Any partial lines at the ends of the interval are - * also cleaned to PoC to prevent data loss. - * - * - start - kernel start address of region - * - end - kernel end address of region - */ -SYM_FUNC_START(__pi_dcache_inval_poc) +.macro raw_dcache_inval_poc_macro dcache_line_size x2, x3 sub x3, x2, #1 tst x1, x3 // end cache line aligned? @@ -158,11 +148,41 @@ SYM_FUNC_START(__pi_dcache_inval_poc) 3: add x0, x0, x2 cmp x0, x1 b.lo 2b +.endm + +/* + * dcache_inval_poc(start, end) + * + * Ensure that any D-cache lines for the interval [start, end) + * are invalidated. Any partial lines at the ends of the interval are + * also cleaned to PoC to prevent data loss. + * + * - start - kernel start address of region + * - end - kernel end address of region + */ +SYM_FUNC_START(__pi_dcache_inval_poc) + raw_dcache_inval_poc_macro dsb sy ret SYM_FUNC_END(__pi_dcache_inval_poc) SYM_FUNC_ALIAS(dcache_inval_poc, __pi_dcache_inval_poc) +/* + * dcache_inval_poc_nosync(start, end) + * + * Issue the instructions of D-cache lines for the interval [start, end) + * for invalidation. Not necessarily cleaned to PoC till an explicit dsb + * sy is issued later + * + * - start - kernel start address of region + * - end - kernel end address of region + */ +SYM_FUNC_START(__pi_dcache_inval_poc_nosync) + raw_dcache_inval_poc_macro + ret +SYM_FUNC_END(__pi_dcache_inval_poc_nosync) +SYM_FUNC_ALIAS(dcache_inval_poc_nosync, __pi_dcache_inval_poc_nosync) + /* * dcache_clean_poc(start, end) * -- Does it look good to you? Thanks Barry