[PATCH v1] i2c: rk3x: Add support for SCL output enable debounce

[PATCH v1] i2c: rk3x: Add support for SCL output enable debounce

[Anand Moon]

From: David Wu <david.wu@rock-chips.com>

As per the RK3399 and RK3588 datasheets Rockchip I2C controllers feature
a SCL_OE_DB register (0x24). This register is used to configure the
debounce time for the SCL output enable signal, which helps prevent
glitches and ensures timing compliance during bus handover or slave clock
stretching.

Introduce a 'has_scl_oe_debounce' flag to rk3x_i2c_soc_data to
distinguish between hardware versions. For supported SoCs, calculate
the debounce counter dynamically based on the current clock rate
and program it during divider adaptation.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
v1: This change have been pulled from linux-radxa kernel.
---
 drivers/i2c/busses/i2c-rk3x.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index d4e9196445c0..31d7d6487613 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -35,6 +35,7 @@
 #define REG_IEN        0x18 /* interrupt enable */
 #define REG_IPD        0x1c /* interrupt pending */
 #define REG_FCNT       0x20 /* finished count */
+#define REG_SCL_OE_DB  0x24 /* Slave hold scl debounce */
 
 /* Data buffer offsets */
 #define TXBUFFER_BASE 0x100
@@ -164,6 +165,7 @@ enum rk3x_i2c_state {
  * @calc_timings: Callback function for i2c timing information calculated
  */
 struct rk3x_i2c_soc_data {
+	bool has_scl_oe_debounce;
 	int grf_offset;
 	int (*calc_timings)(unsigned long, struct i2c_timings *,
 			    struct rk3x_i2c_calced_timings *);
@@ -875,6 +877,7 @@ static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
 {
 	struct i2c_timings *t = &i2c->t;
 	struct rk3x_i2c_calced_timings calc;
+	unsigned long period, time_hold = (WAIT_TIMEOUT / 2) * 1000000;
 	u64 t_low_ns, t_high_ns;
 	unsigned long flags;
 	u32 val;
@@ -892,6 +895,13 @@ static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
 	i2c_writel(i2c, val, REG_CON);
 	i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
 		   REG_CLKDIV);
+
+	if (i2c->soc_data->has_scl_oe_debounce) {
+		period = DIV_ROUND_UP(1000000000, clk_rate);
+		val = DIV_ROUND_UP(time_hold, period);
+		i2c_writel(i2c, val, REG_SCL_OE_DB);
+	}
+
 	spin_unlock_irqrestore(&i2c->lock, flags);
 
 	clk_disable(i2c->pclk);
@@ -1198,6 +1208,7 @@ static const struct rk3x_i2c_soc_data rk3288_soc_data = {
 static const struct rk3x_i2c_soc_data rk3399_soc_data = {
 	.grf_offset = -1,
 	.calc_timings = rk3x_i2c_v1_calc_timings,
+	.has_scl_oe_debounce = true,
 };
 
 static const struct of_device_id rk3x_i2c_match[] = {

base-commit: 805f9a061372164d43ddef771d7cd63e3ba6d845
-- 
2.50.1

Re: [PATCH v1] i2c: rk3x: Add support for SCL output enable debounce

[Heiko Stübner]

Am Samstag, 3. Januar 2026, 06:25:04 Mitteleuropäische Normalzeit schrieb Anand Moon:
> From: David Wu <david.wu@rock-chips.com>
> 
> As per the RK3399 and RK3588 datasheets Rockchip I2C controllers feature
> a SCL_OE_DB register (0x24). This register is used to configure the
> debounce time for the SCL output enable signal, which helps prevent
> glitches and ensures timing compliance during bus handover or slave clock
> stretching.
> 
> Introduce a 'has_scl_oe_debounce' flag to rk3x_i2c_soc_data to
> distinguish between hardware versions. For supported SoCs, calculate
> the debounce counter dynamically based on the current clock rate
> and program it during divider adaptation.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> Signed-off-by: David Wu <david.wu@rock-chips.com>

Signed-off-by lines are in the wrong order.

Original author first, then yours as you're the one handling
the patch last.


Also, does this fix a problem for you, or is this more a case of
"this looks useful"?

Thanks
Heiko

Re: [PATCH v1] i2c: rk3x: Add support for SCL output enable debounce

[Anand Moon]

Hi Heiko,

Thanks for your review comment.

On Sat, 3 Jan 2026 at 16:09, Heiko Stübner <heiko@sntech.de> wrote:
>
> Am Samstag, 3. Januar 2026, 06:25:04 Mitteleuropäische Normalzeit schrieb Anand Moon:
> > From: David Wu <david.wu@rock-chips.com>
> >
> > As per the RK3399 and RK3588 datasheets Rockchip I2C controllers feature
> > a SCL_OE_DB register (0x24). This register is used to configure the
> > debounce time for the SCL output enable signal, which helps prevent
> > glitches and ensures timing compliance during bus handover or slave clock
> > stretching.
> >
> > Introduce a 'has_scl_oe_debounce' flag to rk3x_i2c_soc_data to
> > distinguish between hardware versions. For supported SoCs, calculate
> > the debounce counter dynamically based on the current clock rate
> > and program it during divider adaptation.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > Signed-off-by: David Wu <david.wu@rock-chips.com>
>
> Signed-off-by lines are in the wrong order.
>
> Original author first, then yours as you're the one handling
> the patch last.
>
Ok, I will fix this in the next version, with a new feedback,
>
> Also, does this fix a problem for you, or is this more a case of
> "this looks useful"?
>
Actually, I am investigating a boot reset issue on the Radxa Rock 5B,
Specifically related to the fusb302 Type-C driver. So I was looking for
type-c fusb302 module to communicate with the I2C protocol.
I submitted small changes for this, waiting for feedback

> Thanks
> Heiko

Thanks
-Anand