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Fri, 9 Jan 2026 06:07:28 -0600 Date: Fri, 9 Jan 2026 06:07:28 -0600 From: Nishanth Menon To: Michael Walle , Stephen Boyd CC: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Vignesh Raghavendra" , Tero Kristo , Andrew Davis , Santosh Shilimkar , Michael Turquette , Stephen Boyd , Kevin Hilman , Randolph Sapp , , , , , Subject: Re: [PATCH v2 2/4] clk: keystone: don't cache clock rate Message-ID: <20260109120728.2wku6akxof2ddn4h@tastiness> References: <20251223124729.2482877-1-mwalle@kernel.org> <20251223124729.2482877-3-mwalle@kernel.org> <20251230201233.n36d5fiensqyb6fc@splice> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|SJ1PR10MB6002:EE_ X-MS-Office365-Filtering-Correlation-Id: bf842820-675c-4bfa-5274-08de4f77a998 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013|34020700016|12100799066; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2026 12:07:29.7261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf842820-675c-4bfa-5274-08de4f77a998 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR10MB6002 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260109_040739_568332_FCF281A9 X-CRM114-Status: GOOD ( 35.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 08:55-20260102, Michael Walle wrote: > On Tue Dec 30, 2025 at 9:12 PM CET, Nishanth Menon wrote: > > On 13:47-20251223, Michael Walle wrote: > >> The TISCI firmware will return 0 if the clock or consumer is not > >> enabled although there is a stored value in the firmware. IOW a call to > >> set rate will work but at get rate will always return 0 if the clock is > >> disabled. > >> The clk framework will try to cache the clock rate when it's requested > >> by a consumer. If the clock or consumer is not enabled at that point, > >> the cached value is 0, which is wrong. Thus, disable the cache > >> altogether. > >> > >> Signed-off-by: Michael Walle > >> Reviewed-by: Kevin Hilman > >> Reviewed-by: Randolph Sapp > >> --- > >> drivers/clk/keystone/sci-clk.c | 8 ++++++++ > >> 1 file changed, 8 insertions(+) > >> > >> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c > >> index 9d5071223f4c..0a1565fdbb3b 100644 > >> --- a/drivers/clk/keystone/sci-clk.c > >> +++ b/drivers/clk/keystone/sci-clk.c > >> @@ -333,6 +333,14 @@ static int _sci_clk_build(struct sci_clk_provider *provider, > >> > >> init.ops = &sci_clk_ops; > >> init.num_parents = sci_clk->num_parents; > >> + > >> + /* > >> + * A clock rate query to the SCI firmware will return 0 if either the > >> + * clock itself is disabled or the attached device/consumer is disabled. > >> + * This makes it inherently unsuitable for the caching of the clk > >> + * framework. > >> + */ > >> + init.flags = CLK_GET_RATE_NOCACHE; > >> sci_clk->hw.init = &init; > >> > >> ret = devm_clk_hw_register(provider->dev, &sci_clk->hw); > >> -- > >> 2.47.3 > >> > > > > Reviewed-by: Nishanth Menon > > > > I wish there was a better scheme, but inherently, just like SCMI and > > other systems where power management co-processor controls clocks, there > > is no real feasible caching scheme I can think of. I wonder if Stephen > > or others have a thought on this? > > > > That said, I wonder if we need fixes tag to this? I am sure there are > > other clocks susceptible to this as well. I wonder if > > commit 3c13933c6033 ("clk: keystone: sci-clk: add support for > > dynamically probing clocks") is the appropriate tag? > > >From my previous versions of this patch: > > > Regarding a Fixes: tag. I didn't include one because it might have a > > slight performance impact because the firmware has to be queried > > every time now and it doesn't have been a problem for now. OTOH I've > > enabled tracing during boot and there were just a handful > > clock_{get/set}_rate() calls. > > I'm still undecided if this needs a Fixes tag or not. Strictly > speaking it would need one. Although, I'm not sure it's the one > you mentioned, because the culprit is the "we return 0 if the clock > or it's consumer is disabled", which then caches the wrong value. > So it is probably the very first commit b745c0794e2f ("clk: > keystone: Add sci-clk driver support"). Stephen: Can you pick the patch or suggest improvements? -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D https://ti.com/opensource