Re: [PATCH v3 10/36] KVM: arm64: gic-v5: Detect implemented PPIs on boot

[Jonathan Cameron <jonathan.cameron@huawei.com>]

On Fri, 9 Jan 2026 17:04:42 +0000
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:

> As part of booting the system and initialising KVM, create and
> populate a mask of the implemented PPIs. This mask allows future PPI
> operations (such as save/restore or state, or syncing back into the
> shadow state) to only consider PPIs that are actually implemented on
> the host.
> 
> The set of implemented virtual PPIs matches the set of implemented
> physical PPIs for a GICv5 host. Therefore, this mask represents all
> PPIs that could ever by used by a GICv5-based guest on a specific
> host.
> 
> Only architected PPIs are currently supported in KVM with
> GICv5. Moreover, as KVM only supports a subset of all possible PPIS
> (Timers, PMU, GICv5 SW_PPI) the PPI mask only includes these PPIs, if
> present. The timers are always assumed to be present; if we have KVM
> we have EL2, which means that we have the EL1 & EL2 Timer PPIs. If we
> have a PMU (v3), then the PMUIRQ is present. The GICv5 SW_PPI is
> always assumed to be present.
> 
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
One minor comment below.

> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index 23d0a495d855e..85f9ee5b0ccad 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
> @@ -8,6 +8,8 @@
>  
>  #include "vgic.h"
>  
> +static struct vgic_v5_ppi_caps *ppi_caps;
> +
>  /*
>   * Probe for a vGICv5 compatible interrupt controller, returning 0 on success.
>   * Currently only supports GICv3-based VMs on a GICv5 host, and hence only
> @@ -53,3 +55,37 @@ int vgic_v5_probe(const struct gic_kvm_info *info)
>  
>  	return 0;
>  }
> +
> +/*
> + * Not all PPIs are guaranteed to be implemented for GICv5. Deterermine which
> + * ones are, and generate a mask.
> + */
> +void vgic_v5_get_implemented_ppis(void)
> +{
> +	if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF))
> +		return;
> +
> +	/* Never freed again */
> +	ppi_caps = kzalloc(sizeof(*ppi_caps), GFP_KERNEL);
> +	if (!ppi_caps)
> +		return;
> +
> +	ppi_caps->impl_ppi_mask[0] = 0;
> +	ppi_caps->impl_ppi_mask[1] = 0;

You just kzalloc() the structure so these are already 0.  Given
it's so close I'm not sure there is any 'documentation' value in setting
them here.

> +
> +	/*
> +	 * If we have KVM, we have EL2, which means that we have support for the
> +	 * EL1 and EL2 P & V timers.
> +	 */
> +	ppi_caps->impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_CNTHP);
> +	ppi_caps->impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_CNTV);
> +	ppi_caps->impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_CNTHV);
> +	ppi_caps->impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_CNTP);
> +
> +	/* The SW_PPI should be available */
> +	ppi_caps->impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_SW_PPI);
> +
> +	/* The PMUIRQ is available if we have the PMU */
> +	if (system_supports_pmuv3())
> +		ppi_caps->impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_PMUIRQ);
> +}