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Mon, 12 Jan 2026 21:49:39 -0800 From: Ashish Mhetre To: , , , , , , CC: , , , , , , , , , Ashish Mhetre Subject: [PATCH V8 3/4] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support Date: Tue, 13 Jan 2026 05:49:34 +0000 Message-ID: <20260113054935.1945785-4-amhetre@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260113054935.1945785-1-amhetre@nvidia.com> References: <20260113054935.1945785-1-amhetre@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE33:EE_|IA1PR12MB8556:EE_ X-MS-Office365-Filtering-Correlation-Id: 3dbb1341-4443-414a-fe66-08de526792a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?k/7oG5C7QS4HdHUHhrzoFMglg9pRbgp0Nqj1JJlinQQuS4l3Z1RpYxU/HnJ0?= =?us-ascii?Q?fkT6VCm5UQepiR1Zd1QWMBR0v1ECwa0h9zjWcpf8m1il3EXc0j34QYJNc17x?= =?us-ascii?Q?/hyFxY0r3h4OPsHCYw1RPL6Ed4BG9NK4en8P5lrYH0Gnd5tu0qeDuE4CEwHX?= =?us-ascii?Q?h+RPmrIfAy/K/18ZfI/UARtI54xlq86NHKLleQYC7PJ9ufhOLbhY5XIq17ou?= =?us-ascii?Q?nNQehVrNlqh0D+Tq2/Rsojv6zGVkqYF7E7jbiKxOYl/juDNYkhJoxgf/wwY4?= =?us-ascii?Q?BkS1G31ykKMMXYecLu3w4ZhfBTaqHhhD6amqhIoGLQXoMUmzZ1nPYzyqrpUm?= =?us-ascii?Q?asAeNPdraGeRjcr+O0gpnERlClswYwRh8XAA+SOOkVasuYXpOnC00S8UMjdk?= =?us-ascii?Q?xHiZ+/P57r/+4w3FGhmL+wpi/Ko8Jf6IFofzDqKwyTZwmRSDEI6zR25v1VSh?= =?us-ascii?Q?17F/rJ4NpW8aS58seX5nWnPFNKJmr+JJtcOVdGuWW2G2QYGsrTAa77VsfRjZ?= =?us-ascii?Q?Stn2hbtScQo2JRL7TsBKr4qU3EFPw3qR4KHcS4U2BSg6IsVmqhcepKTK8J+3?= =?us-ascii?Q?fH57FZH/tPUOOWc3vnQ+eO7VggZAoTCqyFJyUJSVB/k5hlCtA3K52nJBxa4U?= =?us-ascii?Q?OwsCK/yq+kmkOfGTFXJ4NRCAXSUb55T5rmb11bL+SGTPtq0EgyRPuW2pNHD7?= =?us-ascii?Q?2tYYyCpLRwmFYHfzGvOknJDIq20STpa4zsiAC6iu7WkLdMfWAENS33VrvOZP?= =?us-ascii?Q?p8fjl06LxZMr1ajLkX09fJlRgsGqfSqoiJ4uXUo9w+5V1AaLbfjbVOOtGylx?= =?us-ascii?Q?DCstymVR7XMFlVRcgJ/m5vPslawubFqPURWOL/6iNMzf88OGS8YAFwcStH/1?= =?us-ascii?Q?ixV6qjcdU6fWYUR3NMX5nFqTlOoTsKfdjhSqMyjf1f0J5XcsKlDgWHt71SQK?= =?us-ascii?Q?ZM6yNvyrFPE4p/uOMEb3vHqk68F+Z0DJDL8TBl975PtUtkwcXAQExt/RpkHw?= =?us-ascii?Q?eDp/pSevZWR47Hfrr3LPZhe42ikH/Dd7P3xsgv3r6VMuuPSd2u7drq74Pz+g?= =?us-ascii?Q?UGSuxuLp/QNPNH5Iu8H41x+hBTubLpoP4HyMOl7KgTvj/AUlqSnwK3PNE6xv?= =?us-ascii?Q?ZLmT0p2aC7Blut13xSX3m4kgQp+6PUrTh/L/w+qeq2T/t2OPlqhIvMNtZwng?= =?us-ascii?Q?G2+JYA/bsOYeATRTKOzsODyGTqk74j7+kaUH9kGYWCdfwQOB2Fq8ujGeEnys?= =?us-ascii?Q?Kzck1lE7I8l3AmucHGNu1naJbThtn7nA1rlJ8TT6cIBY97EJoqZeNJcERzlW?= =?us-ascii?Q?typ5ypno2dJFt/W5EwAjvTR9bLgAhRDJjQdAQHJ2bR5R329uwG/QYLpJxZWu?= =?us-ascii?Q?8AIECRLKQSyBIDS1gFr2Gilir9WktldotSb2uDaiHwjhH0BRKt+CBfZA4XQX?= =?us-ascii?Q?4njcHi0tTepFF011MEj7aDNgrupx53OcTXPAunrYBKXaklg3MMGLpBOdShVy?= =?us-ascii?Q?I4yzxmRgaGLeulYVWkRrcJ6cZuHmGVCY7tP+gW6Sq0mcI+2GEFJU2NqWO9+w?= =?us-ascii?Q?G9zV77IF3UwW0AHjhds=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 05:49:52.7619 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3dbb1341-4443-414a-fe66-08de526792a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8556 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260112_215002_693628_E658F6FB X-CRM114-Status: GOOD ( 15.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add a new device tree binding document for nvidia,tegra264-cmdqv. Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv property. This property is a phandle to the CMDQV device node, allowing the SMMU driver to associate with its corresponding CMDQV instance. Restrict this property usage to Nvidia Tegra264 only. Reviewed-by: Rob Herring (Arm) Acked-by: Nicolin Chen Signed-off-by: Ashish Mhetre --- .../bindings/iommu/arm,smmu-v3.yaml | 27 +++++++++++- .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 +++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..82957334bea2 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -20,7 +20,12 @@ properties: $nodename: pattern: "^iommu@[0-9a-f]*" compatible: - const: arm,smmu-v3 + oneOf: + - const: arm,smmu-v3 + - items: + - enum: + - nvidia,tegra264-smmu + - const: arm,smmu-v3 reg: maxItems: 1 @@ -58,6 +63,15 @@ properties: msi-parent: true + nvidia,cmdqv: + description: | + A phandle to its pairing CMDQV extension for an implementation on NVIDIA + Tegra SoC. + + If this property is absent, CMDQ-Virtualization won't be used and SMMU + will only use its own CMDQ. + $ref: /schemas/types.yaml#/definitions/phandle + hisilicon,broken-prefetch-cmd: type: boolean description: Avoid sending CMD_PREFETCH_* commands to the SMMU. @@ -69,6 +83,17 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silicon that doesn't support SMMU page1 register space. +allOf: + - if: + not: + properties: + compatible: + contains: + const: nvidia,tegra264-smmu + then: + properties: + nvidia,cmdqv: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml new file mode 100644 index 000000000000..3f5006a59805 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 CMDQV + +description: + The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation + on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU. + +maintainers: + - Nicolin Chen + +properties: + compatible: + const: nvidia,tegra264-cmdqv + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + cmdqv@5200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x5200000 0x830000>; + interrupts = ; + }; -- 2.25.1