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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oupton@kernel.org>,
	Zenghui Yu <yuzenghui@huawei.com>, Will Deacon <will@kernel.org>,
	Quentin Perret <qperret@google.com>,
	Fuad Tabba <tabba@google.com>
Subject: [PATCH 2/6] KVM: arm64: Add KVM_PGTABLE_S2_AS_S1 flag
Date: Mon, 19 Jan 2026 10:56:47 +0000	[thread overview]
Message-ID: <20260119105651.255693-3-maz@kernel.org> (raw)
In-Reply-To: <20260119105651.255693-1-maz@kernel.org>

Plumb the MT_S2{,_FWB}_AS_S1 memory types into the KVM_S2_MEMATTR()
macro with a new KVM_PGTABLE_S2_AS_S1 flag.

Nobody selects it yet.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/kvm_pgtable.h |  2 ++
 arch/arm64/kvm/hyp/pgtable.c         | 13 ++++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h
index fc02de43c68dd..9ce51a637da0a 100644
--- a/arch/arm64/include/asm/kvm_pgtable.h
+++ b/arch/arm64/include/asm/kvm_pgtable.h
@@ -232,10 +232,12 @@ struct kvm_pgtable_mm_ops {
  * @KVM_PGTABLE_S2_NOFWB:	Don't enforce Normal-WB even if the CPUs have
  *				ARM64_HAS_STAGE2_FWB.
  * @KVM_PGTABLE_S2_IDMAP:	Only use identity mappings.
+ * @KVM_PGTABLE_S2_AS_S1:	Final memory attributes are that of Stage-1.
  */
 enum kvm_pgtable_stage2_flags {
 	KVM_PGTABLE_S2_NOFWB			= BIT(0),
 	KVM_PGTABLE_S2_IDMAP			= BIT(1),
+	KVM_PGTABLE_S2_AS_S1			= BIT(2),
 };
 
 /**
diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
index 947ac1a951a5b..3c5f399b1b986 100644
--- a/arch/arm64/kvm/hyp/pgtable.c
+++ b/arch/arm64/kvm/hyp/pgtable.c
@@ -659,7 +659,18 @@ void kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu,
 	}
 }
 
-#define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt))
+#define KVM_S2_MEMATTR(pgt, attr)					\
+	({								\
+		kvm_pte_t __attr;					\
+		if((pgt)->flags & KVM_PGTABLE_S2_AS_S1)			\
+			__attr = PAGE_S2_MEMATTR(AS_S1,			\
+						 stage2_has_fwb(pgt));	\
+		else							\
+			__attr = PAGE_S2_MEMATTR(attr,			\
+						 stage2_has_fwb(pgt));	\
+									\
+		__attr;							\
+	})
 
 static int stage2_set_xn_attr(enum kvm_pgtable_prot prot, kvm_pte_t *attr)
 {
-- 
2.47.3



  parent reply	other threads:[~2026-01-19 10:57 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-19 10:56 [PATCH 0/6] KVM: arm64: ... and FWB for all Marc Zyngier
2026-01-19 10:56 ` [PATCH 1/6] arm64: Add MT_S2{,_FWB}_AS_S1 encodings Marc Zyngier
2026-01-22 15:07   ` Fuad Tabba
2026-01-19 10:56 ` Marc Zyngier [this message]
2026-01-22 15:08   ` [PATCH 2/6] KVM: arm64: Add KVM_PGTABLE_S2_AS_S1 flag Fuad Tabba
2026-01-22 17:05     ` Will Deacon
2026-01-19 10:56 ` [PATCH 3/6] KVM: arm64: Make stage2_pte_cacheable() return false when S2_AS_S1 is set Marc Zyngier
2026-01-22 15:04   ` Will Deacon
2026-01-23 13:21     ` Marc Zyngier
2026-01-19 10:56 ` [PATCH 4/6] KVM: arm64: Switch pKVM host S2 over to KVM_PGTABLE_S2_AS_S1 Marc Zyngier
2026-01-22 15:09   ` Fuad Tabba
2026-01-19 10:56 ` [PATCH 5/6] KVM: arm64: Kill KVM_PGTABLE_S2_NOFWB Marc Zyngier
2026-01-22 15:09   ` Fuad Tabba
2026-01-19 10:56 ` [PATCH 6/6] KVM: arm64: Simplify PAGE_S2_MEMATTR Marc Zyngier
2026-01-22 15:03   ` Will Deacon
2026-01-21 16:23 ` [PATCH 0/6] KVM: arm64: ... and FWB for all Joey Gouly
2026-01-21 18:13 ` Fuad Tabba
2026-01-23 12:22 ` Alexandru Elisei
2026-01-23 12:37   ` Marc Zyngier
2026-01-23 15:17     ` Alexandru Elisei

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