From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DACBFCCF2E5 for ; Mon, 19 Jan 2026 11:15:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5r9gb7E4aaeu5qGCVYzf1lsVzuhXz7l7Gcf0eTaAlaY=; b=cld8LD7Ypo9Xo+OIkUw1IO+wqt LkTOjKOeXeHqrAfXxdZqLKdEzrqHYA6m8owAcJUSIchIrwgVrOvG/+27fyo26aWSKv93oj8jZsX79 k5l0BDMyDI2E7HtwxnImudeNKvorNfrzh1v5cMgtd1KY3EYvO7b7zzAEEdzQ0RrSr8LEBoU9PGVN3 ol+EaxPPiOyYe1D83jqkEMFFkaDDeQGmXeU8L2ArZFC7q5KHDd6IjjUUq4l6Fav8MQxQMYTn04Gbv b4bD89PXFewyQIIxHOP8QLSZyx9crEELK9IgT9n1nYFvlk6aGwN32lCs5VMvXBs/oxIu5Q5WjjT+e Y0jMSO/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vhnE5-00000001rxk-3qbO; Mon, 19 Jan 2026 11:15:17 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vhnE3-00000001rxN-2eAG for linux-arm-kernel@lists.infradead.org; Mon, 19 Jan 2026 11:15:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 74FFB1517; Mon, 19 Jan 2026 03:15:05 -0800 (PST) Received: from localhost (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A11043F740; Mon, 19 Jan 2026 03:15:11 -0800 (PST) Date: Mon, 19 Jan 2026 11:15:09 +0000 From: Leo Yan To: James Clark Cc: Suzuki K Poulose , Mike Leach , John Garry , Will Deacon , Leo Yan , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Thomas Falcon , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] perf cs-etm: Fix decoding for sparse CPU maps Message-ID: <20260119111509.GD1286628@e132581.arm.com> References: <20260119-james-perf-coresight-cpu-map-segfault-v2-0-56b956a629ee@linaro.org> <20260119-james-perf-coresight-cpu-map-segfault-v2-1-56b956a629ee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260119-james-perf-coresight-cpu-map-segfault-v2-1-56b956a629ee@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260119_031515_824471_6D96D308 X-CRM114-Status: GOOD ( 30.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jan 19, 2026 at 10:18:35AM +0000, Coresight ML wrote: > The ETM decoder incorrectly assumed that auxtrace queue indices were > equivalent to CPU number. This assumption is used for inserting records > into the queue, and for fetching queues when given a CPU number. This > assumption held when Perf always opened a dummy event on every CPU, even > if the user provided a subset of CPUs on the commandline, resulting in > the indices aligning. > > For example: > > # event : name = cs_etm//u, , id = { 2451, 2452 }, type = 11 (cs_etm), size = 136, config = 0x4010, { sample_period, samp> > # event : name = dummy:u, , id = { 2453, 2454, 2455, 2456 }, type = 1 (PERF_TYPE_SOFTWARE), size = 136, config = 0x9 (PER> > > 0 0 0x200 [0xd0]: PERF_RECORD_ID_INDEX nr: 6 > ... id: 2451 idx: 2 cpu: 2 tid: -1 > ... id: 2452 idx: 3 cpu: 3 tid: -1 > ... id: 2453 idx: 0 cpu: 0 tid: -1 > ... id: 2454 idx: 1 cpu: 1 tid: -1 > ... id: 2455 idx: 2 cpu: 2 tid: -1 > ... id: 2456 idx: 3 cpu: 3 tid: -1 > > Since commit 811082e4b668 ("perf parse-events: Support user CPUs mixed > with threads/processes") the dummy event no longer behaves in this way, > making the ETM event indices start from 0 on the first CPU recorded > regardless of its ID: > > # event : name = cs_etm//u, , id = { 771, 772 }, type = 11 (cs_etm), size = 144, config = 0x4010, { sample_period, sample> > # event : name = dummy:u, , id = { 773, 774 }, type = 1 (PERF_TYPE_SOFTWARE), size = 144, config = 0x9 (PERF_COUNT_SW_DUM> > > 0 0 0x200 [0x90]: PERF_RECORD_ID_INDEX nr: 4 > ... id: 771 idx: 0 cpu: 2 tid: -1 > ... id: 772 idx: 1 cpu: 3 tid: -1 > ... id: 773 idx: 0 cpu: 2 tid: -1 > ... id: 774 idx: 1 cpu: 3 tid: -1 Seems to me that this patch works around the issue by using the CPU ID instead, but event->auxtrace.idx is broken. Should we store the correct index in event->auxtrace.idx (e.g., in the __perf_event__synthesize_id_index()) ? Thanks, Leo > This causes the following segfault when decoding: > > $ perf record -e cs_etm//u -C 2,3 -- true > $ perf report > > perf: Segmentation fault > -------- backtrace -------- > #0 0xaaaabf9fd020 in ui__signal_backtrace setup.c:110 > #1 0xffffab5c7930 in __kernel_rt_sigreturn [vdso][930] > #2 0xaaaabfb68d30 in cs_etm_decoder__reset cs-etm-decoder.c:85 > #3 0xaaaabfb65930 in cs_etm__get_data_block cs-etm.c:2032 > #4 0xaaaabfb666fc in cs_etm__run_per_cpu_timeless_decoder cs-etm.c:2551 > #5 0xaaaabfb6692c in (cs_etm__process_timeless_queues cs-etm.c:2612 > #6 0xaaaabfb63390 in cs_etm__flush_events cs-etm.c:921 > #7 0xaaaabfb324c0 in auxtrace__flush_events auxtrace.c:2915 > #8 0xaaaabfaac378 in __perf_session__process_events session.c:2285 > #9 0xaaaabfaacc9c in perf_session__process_events session.c:2442 > #10 0xaaaabf8d3d90 in __cmd_report builtin-report.c:1085 > #11 0xaaaabf8d6944 in cmd_report builtin-report.c:1866 > #12 0xaaaabf95ebfc in run_builtin perf.c:351 > #13 0xaaaabf95eeb0 in handle_internal_command perf.c:404 > #14 0xaaaabf95f068 in run_argv perf.c:451 > #15 0xaaaabf95f390 in main perf.c:558 > #16 0xffffaab97400 in __libc_start_call_main libc_start_call_main.h:74 > #17 0xffffaab974d8 in __libc_start_main@@GLIBC_2.34 libc-start.c:128 > #18 0xaaaabf8aa8f0 in _start perf[7a8f0] > > Fix it by inserting into the queues based on CPU number, rather than > using the index. > > Fixes: 811082e4b668 ("perf parse-events: Support user CPUs mixed with threads/processes") > Signed-off-by: James Clark > --- > tools/perf/util/cs-etm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c > index 25d56e0f1c07..12b55c2bc2ca 100644 > --- a/tools/perf/util/cs-etm.c > +++ b/tools/perf/util/cs-etm.c > @@ -3086,7 +3086,7 @@ static int cs_etm__queue_aux_fragment(struct perf_session *session, off_t file_o > > if (aux_offset >= auxtrace_event->offset && > aux_offset + aux_size <= auxtrace_event->offset + auxtrace_event->size) { > - struct cs_etm_queue *etmq = etm->queues.queue_array[auxtrace_event->idx].priv; > + struct cs_etm_queue *etmq = cs_etm__get_queue(etm, auxtrace_event->cpu); > > /* > * If this AUX event was inside this buffer somewhere, create a new auxtrace event > @@ -3095,6 +3095,7 @@ static int cs_etm__queue_aux_fragment(struct perf_session *session, off_t file_o > auxtrace_fragment.auxtrace = *auxtrace_event; > auxtrace_fragment.auxtrace.size = aux_size; > auxtrace_fragment.auxtrace.offset = aux_offset; > + auxtrace_fragment.auxtrace.idx = etmq->queue_nr; > file_offset += aux_offset - auxtrace_event->offset + auxtrace_event->header.size; > > pr_debug3("CS ETM: Queue buffer size: %#"PRI_lx64" offset: %#"PRI_lx64 > > -- > 2.34.1 > > _______________________________________________ > CoreSight mailing list -- coresight@lists.linaro.org > To unsubscribe send an email to coresight-leave@lists.linaro.org