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Wysocki" , Viresh Kumar , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sebin Francis , Bryan Brattlof , , , , Subject: Re: [PATCH v2 2/3] cpufreq: ti-cpufreq: add support for AM62L3 SoC Message-ID: <20260120110025.sflker5d236ineqi@lcpd911> References: <20260116-am62l-cpufreq-v2-0-eac7e2e78d29@ti.com> <20260116-am62l-cpufreq-v2-2-eac7e2e78d29@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|PH7PR10MB6202:EE_ X-MS-Office365-Filtering-Correlation-Id: 350bcdc0-04a6-42fa-ba0d-08de58131faf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?aLv8miNG+Qc433LCizT9XMDnFxtqelLcKgEx+HhMj1lTxa4pq0fVsZI4y63f?= =?us-ascii?Q?GlkMA7JVC+NyNNMZoCTmQwhpiwAFkwddlTWC4FxfMvNLiZRKqBD0S51LhBXm?= =?us-ascii?Q?kUbzIuHITbGhVJA6YiNhVoy3ILydSUD2OCVKrgD8r2QA3Peo6LvFOxJgw1Lf?= =?us-ascii?Q?/UsqIsIAU/ZFrCRAPNYvZLz3kv3ZL/sSb2X8gc8Xx/5xszYosV5oiZ+4ST7+?= =?us-ascii?Q?E3pUbuFPxTYAxCNFJM9C8wOhv53Bm8ugxJztFg3zvuBuBV+DvVsg8Ti2o/om?= =?us-ascii?Q?MwGXuw6Fx2PAgbaP+AE0xYXYC1ZYUT7EqWDPdemWCp/+Lf0OrC0wOKzUuejF?= =?us-ascii?Q?beYoqp6+K+c6ZddVXrv3VVGniJP/8TIAII+xuO2EbEMWlMt4kamUgAh9TZHS?= =?us-ascii?Q?KZzzFJCmmU/7kdsQ/sgZ9/L0RDE32V3tfYrFFOgLzDAHF/h+PnVLTSxBsBsi?= =?us-ascii?Q?9X+i0sAk1OLQArkbBNq0WipL5xxvAIUDGcGJpIBNfDtcJYqoUuoWuCo7J0f0?= =?us-ascii?Q?g8Gcu4m1IlEjkX590M0Z+4BVglRUKD9o/BYr64u3/NSaYntP9aG8E8UhfdgN?= =?us-ascii?Q?eLRAVHTR+eyIQ9pNxkVVQzAw6z7MgxbruoSgElwJU+PelHAj4C7WK26HDf4+?= =?us-ascii?Q?hbHMq0q4DejmlQnyKiUMIcteho7qkwRqyEQU7+Bx4C5LxkS6eQz3sxMbFO3p?= =?us-ascii?Q?SRjo3AeWa5xfwwVl+gJgfkvH1o27WXiHwsTSCV2UNsV4N/OsLL3J9CGQ49YD?= =?us-ascii?Q?WGT1N/1nhOgJ+Nd8Rxpj4Jr19qWJUpglESMD6fP+OQnk/oSLf9NJZYMLPD//?= =?us-ascii?Q?3rd2oGq+Iv9hSY3xOXzZMA22DupDY1+uhwelvYoSoRGy129LppDHi1fGCCMo?= =?us-ascii?Q?Eiowzo2y3Rvwh+ny9h7TOh8HaSGewpanACw6Db46ZonRkkZWOo4eSMEFDzdt?= =?us-ascii?Q?TR6nfSwDPPT7wpTP9szb3ZexGGmaM67YVFJaOecFKIM/TpJvNt6iJ/6z+ei/?= =?us-ascii?Q?AmTqIRsaMErUjRpr2LyyNnHdmaATX/NXLE0UBtj0suthfaiQ6ThYr84eNUON?= =?us-ascii?Q?RP3mtOXTN/PFv4DT3lrgRRJJzGc+40ScDFoUQhLnAiyVRkuL+yXV8da5CmgS?= =?us-ascii?Q?SYRfj2PZDC3F5a5wiQ3lu7ZQl72UG/f07evJGKZiIyb2Ila+oKROyX9sIppK?= =?us-ascii?Q?hq9CnNjmSTZxGVHwqEH63ez1U0pM+7WM/SeFE27q7E6CR0xWlqIQ1jl8dx/h?= =?us-ascii?Q?tQI24LuoJQ+miIDYG+MvThqV/j+j0mg/I+ooDxg0ELEIh8xJpYvMidCxNyS9?= =?us-ascii?Q?eH/dWfEosX5xRM/2ZHUUSgsIXfLe8fHTY0FQpDigzEeDNIEDfMq5xIj0yuKB?= =?us-ascii?Q?i9n0fhLVlFn4nVuxObGmnQh/iimFzlW2gt//+sGJa8ngRKI4Y6zXfFCy5JfJ?= =?us-ascii?Q?STWGIvptTotTXgmHQzG3CT6/qlnScFcmVdJ1oYNad9rStNNWo2mQH29qcAj1?= =?us-ascii?Q?3AIQX/nOz+7wAzGXcHJloNKCCqd/x0bvhRoSTrWUUjshFS3xbQcljUhdhXje?= =?us-ascii?Q?2U3FCqplQFXnvfrVZMj1Ta1wYmDvk4tUmiTuavXzALcBF/9aLVeqUUsBK9po?= =?us-ascii?Q?p9YsfYw4+P2cT3MlVc30uJwdNKWHHncyuUYL2K42kJ70wGQNQlXWCZovUpxg?= =?us-ascii?Q?cpTcwQ=3D=3D?= X-Forefront-Antispam-Report: CIP:198.47.23.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet200.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 11:00:29.1178 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 350bcdc0-04a6-42fa-ba0d-08de58131faf X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR10MB6202 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260120_030033_404337_7516AB5B X-CRM114-Status: GOOD ( 24.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Jan 16, 2026 at 15:15:29 -0600, Kendall Willis wrote: > On 1/16/26 04:21, Dhruva Gole wrote: > > Add CPUFreq support for the AM62L3 SoC with the appropriate > > AM62L3 speed grade constants according to the datasheet [1]. > > > > This follows the same architecture-specific implementation pattern > > as other TI SoCs in the AM6x family. > > > > While at it, also sort instances where the SOC family names > > were not sorted alphabetically. > > > > [1] https://www.ti.com/lit/pdf/SPRSPA1 > > > > Signed-off-by: Dhruva Gole > > --- > > drivers/cpufreq/ti-cpufreq.c | 34 +++++++++++++++++++++++++++++++++- > > 1 file changed, 33 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c > > index 6ee76f5fe9c567b0b88797ddb51764a2a5606b16..4e65e96b784ee908716c63316bb54eb1ac1efc49 100644 > > --- a/drivers/cpufreq/ti-cpufreq.c > > +++ b/drivers/cpufreq/ti-cpufreq.c > > @@ -48,6 +48,12 @@ > > #define AM625_SUPPORT_S_MPU_OPP BIT(1) > > #define AM625_SUPPORT_T_MPU_OPP BIT(2) > > +#define AM62L3_EFUSE_E_MPU_OPP 5 > > +#define AM62L3_EFUSE_O_MPU_OPP 15 > > + > > +#define AM62L3_SUPPORT_E_MPU_OPP BIT(0) > > +#define AM62L3_SUPPORT_O_MPU_OPP BIT(1) > > + > > Shouldn't these defines for AM62L be placed after the AM62A defines to > maintain alphabetical order? > > > enum { > > AM62A7_EFUSE_M_MPU_OPP = 13, > > AM62A7_EFUSE_N_MPU_OPP, > > @@ -213,6 +219,22 @@ static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data, > > return calculated_efuse; > > } > > +static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data, > > + unsigned long efuse) > > +{ > > + unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP; > > + > > + switch (efuse) { > > + case AM62L3_EFUSE_O_MPU_OPP: > > + calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP; > > + fallthrough; > > + case AM62L3_EFUSE_E_MPU_OPP: > > + calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP; > > + } > > + > > + return calculated_efuse; > > +} > > + > > static struct ti_cpufreq_soc_data am3x_soc_data = { > > .efuse_xlate = amx3_efuse_xlate, > > .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, > > @@ -313,8 +335,9 @@ static struct ti_cpufreq_soc_data am3517_soc_data = { > > static const struct soc_device_attribute k3_cpufreq_soc[] = { > > { .family = "AM62X", }, > > { .family = "AM62AX", }, > > - { .family = "AM62PX", }, > > { .family = "AM62DX", }, > > + { .family = "AM62LX", }, > > + { .family = "AM62PX", }, > > { /* sentinel */ } > > }; > > @@ -327,6 +350,14 @@ static struct ti_cpufreq_soc_data am625_soc_data = { > > .quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG, > > }; > > +static struct ti_cpufreq_soc_data am62l3_soc_data = { > > + .efuse_xlate = am62l3_efuse_xlate, > > + .efuse_offset = 0x0, > > + .efuse_mask = 0x07c0, > > + .efuse_shift = 0x6, > > + .multi_regulator = false, > > +}; > > + > > Same thing here with the AM62L struct being before the AM62A struct which is > not alphabetical. okay addressing and sending next rev, thanks for reviewing. > > > static struct ti_cpufreq_soc_data am62a7_soc_data = { > > .efuse_xlate = am62a7_efuse_xlate, > > .efuse_offset = 0x0, > > @@ -463,6 +494,7 @@ static const struct of_device_id ti_cpufreq_of_match[] __maybe_unused = { > > { .compatible = "ti,am625", .data = &am625_soc_data, }, > > { .compatible = "ti,am62a7", .data = &am62a7_soc_data, }, > > { .compatible = "ti,am62d2", .data = &am62a7_soc_data, }, > > + { .compatible = "ti,am62l3", .data = &am62l3_soc_data, }, > > { .compatible = "ti,am62p5", .data = &am62p5_soc_data, }, > > /* legacy */ > > { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, > > > > Best, > Kendall Willis > -- Best regards, Dhruva Gole Texas Instruments Incorporated