* [PATCH] KVM: arm64: nv: Return correct RES0 bits for FGT registers
@ 2026-01-21 10:16 Zenghui Yu
2026-01-22 9:07 ` Marc Zyngier
2026-01-22 9:11 ` Marc Zyngier
0 siblings, 2 replies; 3+ messages in thread
From: Zenghui Yu @ 2026-01-21 10:16 UTC (permalink / raw)
To: kvmarm, linux-arm-kernel
Cc: maz, oupton, joey.gouly, suzuki.poulose, zenghui.yu,
wanghaibin.wang
From: "Zenghui Yu (Huawei)" <zenghui.yu@linux.dev>
We had extended the sysreg masking infrastructure to more general
registers, instead of restricting it to VNCR-backed registers, since
commit a0162020095e ("KVM: arm64: Extend masking facility to arbitrary
registers"). Fix kvm_get_sysreg_res0() to reflect this fact.
Note that we're sure that we only deal with FGT registers in
kvm_get_sysreg_res0(), the
if (sr < __VNCR_START__)
is actually a never false, which should probably be removed later.
Fixes: 69c19e047dfe ("KVM: arm64: Add TCR2_EL2 to the sysreg arrays")
Signed-off-by: Zenghui Yu (Huawei) <zenghui.yu@linux.dev>
---
arch/arm64/kvm/emulate-nested.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 834f13fb1fb7..2d04fb56746e 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -2428,7 +2428,7 @@ static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr)
masks = kvm->arch.sysreg_masks;
- return masks->mask[sr - __VNCR_START__].res0;
+ return masks->mask[sr - __SANITISED_REG_START__].res0;
}
static bool check_fgt_bit(struct kvm_vcpu *vcpu, enum vcpu_sysreg sr,
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] KVM: arm64: nv: Return correct RES0 bits for FGT registers
2026-01-21 10:16 [PATCH] KVM: arm64: nv: Return correct RES0 bits for FGT registers Zenghui Yu
@ 2026-01-22 9:07 ` Marc Zyngier
2026-01-22 9:11 ` Marc Zyngier
1 sibling, 0 replies; 3+ messages in thread
From: Marc Zyngier @ 2026-01-22 9:07 UTC (permalink / raw)
To: Zenghui Yu
Cc: kvmarm, linux-arm-kernel, oupton, joey.gouly, suzuki.poulose,
wanghaibin.wang
On Wed, 21 Jan 2026 10:16:31 +0000,
Zenghui Yu <zenghui.yu@linux.dev> wrote:
>
> From: "Zenghui Yu (Huawei)" <zenghui.yu@linux.dev>
>
> We had extended the sysreg masking infrastructure to more general
> registers, instead of restricting it to VNCR-backed registers, since
> commit a0162020095e ("KVM: arm64: Extend masking facility to arbitrary
> registers"). Fix kvm_get_sysreg_res0() to reflect this fact.
Huh, what a howler! Thanks a lot for spotting this!
>
> Note that we're sure that we only deal with FGT registers in
> kvm_get_sysreg_res0(), the
>
> if (sr < __VNCR_START__)
>
> is actually a never false, which should probably be removed later.
I think the biggest mistake is to have several places where we perform
sysreg index to array index conversions. We should try to unify that.
>
> Fixes: 69c19e047dfe ("KVM: arm64: Add TCR2_EL2 to the sysreg arrays")
> Signed-off-by: Zenghui Yu (Huawei) <zenghui.yu@linux.dev>
Cc: stable@vger.kernel.org
Thanks again,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] KVM: arm64: nv: Return correct RES0 bits for FGT registers
2026-01-21 10:16 [PATCH] KVM: arm64: nv: Return correct RES0 bits for FGT registers Zenghui Yu
2026-01-22 9:07 ` Marc Zyngier
@ 2026-01-22 9:11 ` Marc Zyngier
1 sibling, 0 replies; 3+ messages in thread
From: Marc Zyngier @ 2026-01-22 9:11 UTC (permalink / raw)
To: kvmarm, linux-arm-kernel, Zenghui Yu
Cc: oupton, joey.gouly, suzuki.poulose, wanghaibin.wang
On Wed, 21 Jan 2026 18:16:31 +0800, Zenghui Yu wrote:
> We had extended the sysreg masking infrastructure to more general
> registers, instead of restricting it to VNCR-backed registers, since
> commit a0162020095e ("KVM: arm64: Extend masking facility to arbitrary
> registers"). Fix kvm_get_sysreg_res0() to reflect this fact.
>
> Note that we're sure that we only deal with FGT registers in
> kvm_get_sysreg_res0(), the
>
> [...]
Applied to next, thanks!
[1/1] KVM: arm64: nv: Return correct RES0 bits for FGT registers
commit: 2eb80a2eee18762a33aa770d742d64fe47852c7e
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-01-21 10:16 [PATCH] KVM: arm64: nv: Return correct RES0 bits for FGT registers Zenghui Yu
2026-01-22 9:07 ` Marc Zyngier
2026-01-22 9:11 ` Marc Zyngier
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