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(unknown [112.65.126.162]) by smtp.qiye.163.com (Hmail) with ESMTP id 31bc9a76c; Fri, 23 Jan 2026 17:53:54 +0800 (GMT+08:00) From: Albert Yang To: Ulf Hansson , Adrian Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ge Gordon , Arnd Bergmann Cc: BST Linux Kernel Upstream Group , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v5 4/6] arm64: dts: bst: enable eMMC controller in C1200 CDCU1.0 board Date: Fri, 23 Jan 2026 17:53:40 +0800 Message-ID: <20260123095342.272505-5-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260123095342.272505-1-yangzh0906@thundersoft.com> References: <20260123095342.272505-1-yangzh0906@thundersoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9bea464d4809cckunm2b675df11c3db7 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZHU9DVkgeSBlITE1PGRkZGFYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSklVTU5VSklNVUpNSVlXWRYaDxIVHRRZQVlPS0hVSktJT09PSFVKS0 tVSkJLS1kG DKIM-Signature: a=rsa-sha256; b=jUSBDXCnvNboLFq2omwmkLk/GN46p2EVluS/JEV4xJatrXsXB7ADBPcrm3KueNFYMFuFU9z9/8II9X9V9EJD+4a4wX3/WWM4S+6lI3WdrlqWh1/ppKQgHcy+GZKm/5g7BeXweLBpm4s4D4pAxy12AI0Tb/wX+JKb08FFRi/KBUg=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=L+fRucl20FdKOFHwR98xnMI2CpradJDFDcAG3Cugf9A=; h=date:mime-version:subject:message-id:from; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260123_015900_500970_84A8B530 X-CRM114-Status: GOOD ( 10.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add eMMC controller support to the BST C1200 device tree: - bstc1200.dtsi: Add mmc0 node for the DWCMSHC SDHCI controller with basic configuration (disabled by default) - bstc1200.dtsi: Add fixed clock definition for MMC controller - bstc1200-cdcu1.0-adas_4c2g.dts: Enable mmc0 with board-specific configuration including 8-bit bus width and reserved SRAM buffer The bounce buffer in reserved SRAM addresses hardware constraints where the eMMC controller cannot access main system memory through SMMU due to a hardware bug, and all DRAM is located outside the 4GB boundary. Signed-off-by: Albert Yang --- Changes for v5: - Split from platform series per Arnd's feedback Changes for v4: - Change compatible to bst,c1200-sdhci - Move bus-width and non-removable to board dts Changes for v3: - Split defconfig into dedicated patch Changes for v2: - Reorganize memory map, standardize interrupt definitions --- .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 18 ++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts index 5eb9ef369d8c..178ad4bf4f0a 100644 --- a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -17,6 +17,25 @@ memory@810000000 { <0x8 0xc0000000 0x1 0x0>, <0xc 0x00000000 0x0 0x40000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mmc0_reserved: mmc0-reserved@5160000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x5160000 0x0 0x10000>; + no-map; + }; + }; +}; + +&mmc0 { + bus-width = <8>; + memory-region = <&mmc0_reserved>; + non-removable; + status = "okay"; }; &uart0 { diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi index dd13c6bfc3c8..9660d8396e27 100644 --- a/arch/arm64/boot/dts/bst/bstc1200.dtsi +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -7,6 +7,12 @@ / { #address-cells = <2>; #size-cells = <2>; + clk_mmc: clock-4000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -72,6 +78,18 @@ uart0: serial@20008000 { status = "disabled"; }; + mmc0: mmc@22200000 { + compatible = "bst,c1200-sdhci"; + reg = <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + clocks = <&clk_mmc>; + clock-names = "core"; + dma-coherent; + interrupts = ; + max-frequency = <200000000>; + status = "disabled"; + }; + gic: interrupt-controller@32800000 { compatible = "arm,gic-v3"; reg = <0x0 0x32800000 0x0 0x10000>, -- 2.43.0