[PATCH v5 0/6] mmc: add support for BST C1200 SDHCI controller

[PATCH v5 0/6] mmc: add support for BST C1200 SDHCI controller

[Albert Yang]

This series adds MMC/eMMC controller support for Black Sesame Technologies
C1200 SoC. BST is a leading automotive-grade computing SoC provider focusing
on intelligent driving, computer vision, and AI capabilities for ADAS and
autonomous driving applications. More information: https://bst.ai

== Background ==

This is the MMC portion split from the original v4 series [1] following
feedback from Arnd Bergmann [2]. The platform support (vendor-prefix,
SoC bindings, Kconfig ARCH_BST, base DTS, defconfig ARCH_BST) has already
been merged into Linux 6.19 through the SoC tree [3].

== Series Overview ==

Patch 1: dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
Patch 2: mmc: sdhci: allow drivers to pre-allocate bounce buffer
Patch 3: mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver
Patch 4: arm64: dts: bst: enable eMMC controller in C1200 CDCU1.0 board
Patch 5: arm64: defconfig: enable BST SDHCI controller
Patch 6: MAINTAINERS: add MMC files to BST entry

== Testing ==

  - checkpatch.pl: PASS (all patches)
  - dt_binding_check: PASS
  - dtbs_check (CHECK_DTBS=y): PASS
  - Build tested with ARCH=arm64 defconfig

== Changes since v4 ==

  - Split: Platform patches merged separately via SoC tree; this series is
    MMC-only, submitted to MMC maintainers

  DT binding (patch 1):
  - Rename file from bst,dwcmshc-sdhci.yaml to bst,c1200-sdhci.yaml
  - Fix example compatible string to match property definition

  Driver (patch 3):
  - Fix compatible string to match dt-bindings (bst,c1200-sdhci)
  - Simplify clock divider calculation with clearer frequency range logic
  - Add linux/bits.h and linux/bitfield.h headers
  - Remove unused linux/ioport.h header
  - Rename SDHCI_TUNING_COUNT to BST_TUNING_COUNT
  - Rename BST_EMMC_CTRL_BIT2 to BST_EMMC_CTRL_RST_N
  - Fix BST_DEFAULT_MAX_FREQ from 2MHz to 200MHz
  - Convert kernel-doc to regular comments (per Adrian Hunter)
  - Add sdhci_bst_free_bounce_buffer() helper (per Adrian Hunter)


== References ==

[1] v4: https://lore.kernel.org/lkml/20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com/
[2] Split: https://lore.kernel.org/lkml/09b1318e-21dc-4354-8733-866b70696295@app.fastmail.com/
[3] Merged via soc-newsoc-6.19

Albert Yang (6):
  dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
  mmc: sdhci: allow drivers to pre-allocate bounce buffer
  mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver
  arm64: dts: bst: enable eMMC controller in C1200 CDCU1.0 board
  arm64: defconfig: enable BST SDHCI controller
  MAINTAINERS: add MMC files to BST entry

 .../bindings/mmc/bst,c1200-sdhci.yaml         |  70 +++
 MAINTAINERS                                   |   2 +
 .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts    |  19 +
 arch/arm64/boot/dts/bst/bstc1200.dtsi         |  18 +
 arch/arm64/configs/defconfig                  |   1 +
 drivers/mmc/host/Kconfig                      |  14 +
 drivers/mmc/host/Makefile                     |   1 +
 drivers/mmc/host/sdhci-of-bst.c               | 521 ++++++++++++++++++
 drivers/mmc/host/sdhci.c                      |   7 +
 9 files changed, 653 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml
 create mode 100644 drivers/mmc/host/sdhci-of-bst.c

base-commit: 0f61b1860cc3f52aef9036d7235ed1f017632193
-- 
2.43.0

[PATCH v5 1/6] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller

[Albert Yang]

Add device tree bindings for the Black Sesame Technologies
DWCMSHC SDHCI controller used in C1200 SoC.

The binding describes a Synopsys DesignWare Cores Mobile Storage
Host Controller with BST-specific extensions including:
- Two register regions (core SDHCI and CRM registers)
- Optional memory-region for bounce buffer support
- Fixed clock input

Signed-off-by: Ge Gordon <gordon.ge@bst.ai>
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---
Changes for v5:
- Rename file from bst,dwcmshc-sdhci.yaml to bst,c1200-sdhci.yaml
- Fix example compatible string to match property definition
- Split from platform series per Arnd's feedback

Changes for v4:
- Change \$ref to sdhci-common.yaml#
- Change compatible to bst,c1200-sdhci

Changes for v3:
- Switch reg schema to explicit items with descriptions
- Improve example with bus node wrapper

Changes for v2:
- Simplify description, correct compatible string
---
 .../bindings/mmc/bst,c1200-sdhci.yaml         | 70 +++++++++++++++++++
 1 file changed, 70 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml

diff --git a/Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml b/Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml
new file mode 100644
index 000000000000..8358bb70c333
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/bst,c1200-sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Black Sesame Technologies DWCMSHC SDHCI Controller
+
+maintainers:
+  - Ge Gordon <gordon.ge@bst.ai>
+
+allOf:
+  - $ref: sdhci-common.yaml#
+
+properties:
+  compatible:
+    const: bst,c1200-sdhci
+
+  reg:
+    items:
+      - description: Core SDHCI registers
+      - description: CRM registers
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: core
+
+  memory-region:
+    maxItems: 1
+
+  dma-coherent: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        mmc@22200000 {
+            compatible = "bst,c1200-sdhci";
+            reg = <0x0 0x22200000 0x0 0x1000>,
+                  <0x0 0x23006000 0x0 0x1000>;
+            interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&clk_mmc>;
+            clock-names = "core";
+            memory-region = <&mmc0_reserved>;
+            max-frequency = <200000000>;
+            bus-width = <8>;
+            non-removable;
+            dma-coherent;
+        };
+    };
-- 
2.43.0

[PATCH v5 2/6] mmc: sdhci: allow drivers to pre-allocate bounce buffer

[Albert Yang]

Allow platform drivers to pre-allocate bounce buffer by checking if
host->bounce_buffer is already set before attempting allocation.

This enables platforms with specific DMA constraints (such as 32-bit
DMA on controllers that cannot access high memory) to use their own
reserved memory regions for the bounce buffer.

Suggested-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>

---
Changes for v5:
- Split from platform series per Arnd's feedback

Changes for v4:
- New patch suggested by Adrian Hunter
---
 drivers/mmc/host/sdhci.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ac7e11f37af7..dc5960e72a38 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -4193,6 +4193,12 @@ static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
 	unsigned int bounce_size;
 	int ret;
 
+	/* Drivers may have already allocated the buffer */
+	if (host->bounce_buffer) {
+		bounce_size = host->bounce_buffer_size;
+		max_blocks = bounce_size / 512;
+		goto out;
+	}
 	/*
 	 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
 	 * has diminishing returns, this is probably because SD/MMC
@@ -4241,6 +4247,7 @@ static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
 
 	host->bounce_buffer_size = bounce_size;
 
+out:
 	/* Lie about this since we're bouncing */
 	mmc->max_segs = max_blocks;
 	mmc->max_seg_size = bounce_size;
-- 
2.43.0

[PATCH v5 3/6] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver

[Albert Yang]

Add SDHCI controller driver for Black Sesame Technologies C1200 SoC.

This driver supports the DWCMSHC SDHCI controller with BST-specific
enhancements including:
- Custom clock management and tuning
- Power management support
- BST-specific register configurations
- Support for eMMC and SD card interfaces
- Hardware limitation workaround for 32-bit DMA addressing

The driver addresses specific hardware constraints where:
- System memory uses 64-bit bus, eMMC controller uses 32-bit bus
- eMMC controller cannot access memory through SMMU due to hardware bug
- All system DRAM is configured outside 4GB boundary (ZONE_DMA32)
- Uses SRAM-based bounce buffer within 32-bit address space

Signed-off-by: Ge Gordon <gordon.ge@bst.ai>
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

---
Changes for v5:
- Split from platform series per Arnd's feedback
- Fix compatible string to match dt-bindings (bst,c1200-sdhci)
- Simplify clock divider calculation with clearer frequency range logic
- Add linux/bits.h and linux/bitfield.h headers
- Remove unused linux/ioport.h header
- Rename SDHCI_TUNING_COUNT to BST_TUNING_COUNT
- Rename BST_EMMC_CTRL_BIT2 to BST_EMMC_CTRL_RST_N
- Fix BST_DEFAULT_MAX_FREQ from 2MHz to 200MHz
- Convert kernel-doc to regular comments (per Adrian Hunter)
- Add sdhci_bst_free_bounce_buffer() helper (per Adrian Hunter)

Changes for v4:
- Rename functions from bst_* to sdhci_bst_*
- Rename driver file to sdhci-of-bst.c
- Replace manual polling with read_poll_timeout()
- Add SDHCI_QUIRK_BROKEN_ADMA quirk
- Add Acked-by: Arnd Bergmann

Changes for v3:
- Simplify dwcmshc_priv structure
- Use devm_platform_ioremap_resource()

Changes for v2:
- Remove COMMON_CLK dependency
- Add ARCH_BST || COMPILE_TEST dependency
- Replace temporary ioremap with persistent mapping
---
 drivers/mmc/host/Kconfig        |  14 +
 drivers/mmc/host/Makefile       |   1 +
 drivers/mmc/host/sdhci-of-bst.c | 521 ++++++++++++++++++++++++++++++++
 3 files changed, 536 insertions(+)
 create mode 100644 drivers/mmc/host/sdhci-of-bst.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6d79cc9a79e2..b37e6e014416 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -429,6 +429,20 @@ config MMC_SDHCI_BCM_KONA
 
 	  If you have a controller with this interface, say Y or M here.
 
+config MMC_SDHCI_BST
+	tristate "SDHCI support for Black Sesame Technologies BST C1200 controller"
+	depends on ARCH_BST || COMPILE_TEST
+	depends on MMC_SDHCI_PLTFM
+	depends on OF
+	help
+	  This selects the Secure Digital Host Controller Interface (SDHCI)
+	  for Black Sesame Technologies BST C1200 SoC. The controller is
+	  based on Synopsys DesignWare Cores Mobile Storage Controller but
+	  requires platform-specific workarounds for hardware limitations.
+
+	  If you have a controller with this interface, say Y or M here.
+	  If unsure, say N.
+
 config MMC_SDHCI_F_SDH30
 	tristate "SDHCI support for Fujitsu Semiconductor F_SDH30"
 	depends on MMC_SDHCI_PLTFM
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 5057fea8afb6..ee412e6b84d6 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXS)		+= mxs-mmc.o
 obj-$(CONFIG_MMC_SDHCI)		+= sdhci.o
 obj-$(CONFIG_MMC_SDHCI_UHS2)	+= sdhci-uhs2.o
 obj-$(CONFIG_MMC_SDHCI_PCI)	+= sdhci-pci.o
+obj-$(CONFIG_MMC_SDHCI_BST)	        += sdhci-of-bst.o
 sdhci-pci-y			+= sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \
 				   sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
 obj-$(CONFIG_MMC_SDHCI_ACPI)	+= sdhci-acpi.o
diff --git a/drivers/mmc/host/sdhci-of-bst.c b/drivers/mmc/host/sdhci-of-bst.c
new file mode 100644
index 000000000000..c124990a64f4
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-bst.c
@@ -0,0 +1,521 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SDHCI driver for Black Sesame Technologies C1200 controller
+ *
+ * Copyright (c) 2025 Black Sesame Technologies
+ */
+
+#include <linux/bits.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+
+/* SDHCI register extensions */
+#define SDHCI_CLOCK_PLL_EN		0x0008
+#define SDHCI_VENDOR_PTR_R		0xE8
+
+/* BST-specific tuning parameters */
+#define BST_TUNING_COUNT		0x20
+
+/* Synopsys vendor specific registers */
+#define SDHC_EMMC_CTRL_R_OFFSET		0x2C
+#define MBIU_CTRL			0x510
+
+/* MBIU burst control bits */
+#define BURST_INCR16_EN			BIT(3)
+#define BURST_INCR8_EN			BIT(2)
+#define BURST_INCR4_EN			BIT(1)
+#define BURST_EN			(BURST_INCR16_EN | BURST_INCR8_EN | BURST_INCR4_EN)
+#define MBIU_BURST_MASK			GENMASK(3, 0)
+
+/* CRM (Clock/Reset/Management) register offsets */
+#define SDEMMC_CRM_BCLK_DIV_CTRL	0x08
+#define SDEMMC_CRM_TIMER_DIV_CTRL	0x0C
+#define SDEMMC_CRM_RX_CLK_CTRL		0x14
+#define SDEMMC_CRM_VOL_CTRL		0x1C
+#define REG_WR_PROTECT			0x88
+#define DELAY_CHAIN_SEL			0x94
+
+/* CRM register values and bit definitions */
+#define REG_WR_PROTECT_KEY		0x1234abcd
+#define BST_VOL_STABLE_ON		BIT(7)
+#define BST_TIMER_DIV_MASK		GENMASK(7, 0)
+#define BST_TIMER_DIV_VAL		0x20
+#define BST_TIMER_LOAD_BIT		BIT(8)
+#define BST_BCLK_EN_BIT			BIT(10)
+#define BST_RX_UPDATE_BIT		BIT(11)
+#define BST_EMMC_CTRL_RST_N		BIT(2)	/* eMMC card reset control */
+
+/* Clock frequency limits */
+#define BST_DEFAULT_MAX_FREQ		200000000UL	/* 200 MHz */
+#define BST_DEFAULT_MIN_FREQ		400000UL	/* 400 kHz */
+
+/* Clock control bit definitions */
+#define BST_CLOCK_DIV_MASK		GENMASK(7, 0)
+#define BST_CLOCK_DIV_SHIFT		8
+#define BST_BCLK_DIV_MASK		GENMASK(9, 0)
+
+/* Clock frequency thresholds */
+#define BST_CLOCK_THRESHOLD_LOW		1500
+
+/* Clock stability polling parameters */
+#define BST_CLK_STABLE_POLL_US		1000	/* Poll interval in microseconds */
+#define BST_CLK_STABLE_TIMEOUT_US	20000	/* Timeout for internal clock stabilization (us) */
+
+struct sdhci_bst_priv {
+	void __iomem *crm_reg_base;
+};
+
+union sdhci_bst_rx_ctrl {
+	struct {
+		u32 rx_revert:1,
+		    rx_clk_sel_sec:1,
+		    rx_clk_div:4,
+		    rx_clk_phase_inner:2,
+		    rx_clk_sel_first:1,
+		    rx_clk_phase_out:2,
+		    rx_clk_en:1,
+		    res0:20;
+	};
+	u32 reg;
+};
+
+static u32 sdhci_bst_crm_read(struct sdhci_pltfm_host *pltfm_host, u32 offset)
+{
+	struct sdhci_bst_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	return readl(priv->crm_reg_base + offset);
+}
+
+static void sdhci_bst_crm_write(struct sdhci_pltfm_host *pltfm_host, u32 offset, u32 value)
+{
+	struct sdhci_bst_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	writel(value, priv->crm_reg_base + offset);
+}
+
+static int sdhci_bst_wait_int_clk(struct sdhci_host *host)
+{
+	u16 clk;
+
+	if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
+			      BST_CLK_STABLE_POLL_US, BST_CLK_STABLE_TIMEOUT_US, false,
+			      host, SDHCI_CLOCK_CONTROL))
+		return -EBUSY;
+	return 0;
+}
+
+static unsigned int sdhci_bst_get_max_clock(struct sdhci_host *host)
+{
+	return BST_DEFAULT_MAX_FREQ;
+}
+
+static unsigned int sdhci_bst_get_min_clock(struct sdhci_host *host)
+{
+	return BST_DEFAULT_MIN_FREQ;
+}
+
+static void sdhci_bst_enable_clk(struct sdhci_host *host, unsigned int clk)
+{
+	struct sdhci_pltfm_host *pltfm_host;
+	unsigned int div;
+	u32 val;
+	union sdhci_bst_rx_ctrl rx_reg;
+
+	pltfm_host = sdhci_priv(host);
+
+	/* Calculate clock divider based on target frequency */
+	if (clk == 0) {
+		div = 0;
+	} else if (clk < BST_DEFAULT_MIN_FREQ) {
+		/* Below minimum: use max divider to get closest to min freq */
+		div = BST_DEFAULT_MAX_FREQ / BST_DEFAULT_MIN_FREQ;
+	} else if (clk <= BST_DEFAULT_MAX_FREQ) {
+		/* Normal range: calculate divider directly */
+		div = BST_DEFAULT_MAX_FREQ / clk;
+	} else {
+		/* Above maximum: no division needed */
+		div = 1;
+	}
+
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+	clk &= ~SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	clk &= ~SDHCI_CLOCK_PLL_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
+	val &= ~BST_TIMER_LOAD_BIT;
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
+
+	val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
+	val &= ~BST_TIMER_DIV_MASK;
+	val |= BST_TIMER_DIV_VAL;
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
+
+	val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
+	val |= BST_TIMER_LOAD_BIT;
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
+
+	val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
+	val &= ~BST_RX_UPDATE_BIT;
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
+
+	rx_reg.reg = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
+
+	rx_reg.rx_revert = 0;
+	rx_reg.rx_clk_sel_sec = 1;
+	rx_reg.rx_clk_div = 4;
+	rx_reg.rx_clk_phase_inner = 2;
+	rx_reg.rx_clk_sel_first = 0;
+	rx_reg.rx_clk_phase_out = 2;
+
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, rx_reg.reg);
+
+	val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
+	val |= BST_RX_UPDATE_BIT;
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
+
+	/* Disable clock first */
+	val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
+	val &= ~BST_BCLK_EN_BIT;
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
+
+	/* Setup clock divider */
+	val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
+	val &= ~BST_BCLK_DIV_MASK;
+	val |= div;
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
+
+	/* Enable clock */
+	val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
+	val |= BST_BCLK_EN_BIT;
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
+
+	/* RMW the clock divider bits to avoid clobbering other fields */
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+	clk &= ~(BST_CLOCK_DIV_MASK << BST_CLOCK_DIV_SHIFT);
+	clk |= (div & BST_CLOCK_DIV_MASK) << BST_CLOCK_DIV_SHIFT;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+	clk |= SDHCI_CLOCK_PLL_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	clk |= SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	clk |= SDHCI_CLOCK_INT_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+}
+
+static void sdhci_bst_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+	/* Turn off card/internal/PLL clocks when clock==0 to avoid idle power */
+	u32 clk_reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+
+	if (!clock) {
+		clk_reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_PLL_EN);
+		sdhci_writew(host, clk_reg, SDHCI_CLOCK_CONTROL);
+		return;
+	}
+	sdhci_bst_enable_clk(host, clock);
+}
+
+/*
+ * sdhci_bst_reset - Reset the SDHCI host controller with special
+ * handling for eMMC card reset control.
+ */
+static void sdhci_bst_reset(struct sdhci_host *host, u8 mask)
+{
+	u16 vendor_ptr, emmc_ctrl_reg;
+	u32 reg;
+
+	if (host->mmc->caps2 & MMC_CAP2_NO_SD) {
+		vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
+		emmc_ctrl_reg = vendor_ptr + SDHC_EMMC_CTRL_R_OFFSET;
+
+		reg = sdhci_readw(host, emmc_ctrl_reg);
+		reg &= ~BST_EMMC_CTRL_RST_N;
+		sdhci_writew(host, reg, emmc_ctrl_reg);
+		sdhci_reset(host, mask);
+		usleep_range(10, 20);
+		reg = sdhci_readw(host, emmc_ctrl_reg);
+		reg |= BST_EMMC_CTRL_RST_N;
+		sdhci_writew(host, reg, emmc_ctrl_reg);
+	} else {
+		sdhci_reset(host, mask);
+	}
+}
+
+/* Set timeout control register to maximum value (0xE) */
+static void sdhci_bst_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
+{
+	sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
+}
+
+/*
+ * sdhci_bst_set_power - Set power mode and voltage, also configures
+ * MBIU burst mode control based on power state.
+ */
+static void sdhci_bst_set_power(struct sdhci_host *host, unsigned char mode,
+				unsigned short vdd)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	u32 reg;
+	u32 val;
+
+	sdhci_set_power(host, mode, vdd);
+
+	if (mode == MMC_POWER_OFF) {
+		/* Disable MBIU burst mode */
+		reg = sdhci_readw(host, MBIU_CTRL);
+		reg &= ~BURST_EN; /* Clear all burst enable bits */
+		sdhci_writew(host, reg, MBIU_CTRL);
+
+		/* Disable CRM BCLK */
+		val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
+		val &= ~BST_BCLK_EN_BIT;
+		sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
+
+		/* Disable RX clock */
+		val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
+		val &= ~BST_RX_UPDATE_BIT;
+		sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
+
+		/* Turn off voltage stable power */
+		val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_VOL_CTRL);
+		val &= ~BST_VOL_STABLE_ON;
+		sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, val);
+	} else {
+		/* Configure burst mode only when powered on */
+		reg = sdhci_readw(host, MBIU_CTRL);
+		reg &= ~MBIU_BURST_MASK; /* Clear burst related bits */
+		reg |= BURST_EN; /* Enable burst mode for better bandwidth */
+		sdhci_writew(host, reg, MBIU_CTRL);
+	}
+}
+
+/*
+ * sdhci_bst_execute_tuning - Execute tuning procedure by trying different
+ * delay chain values and selecting the optimal one.
+ */
+static int sdhci_bst_execute_tuning(struct sdhci_host *host, u32 opcode)
+{
+	struct sdhci_pltfm_host *pltfm_host;
+	int ret = 0, error;
+	int first_start = -1, first_end = -1, best = 0;
+	int second_start = -1, second_end = -1, has_failure = 0;
+	int i;
+
+	pltfm_host = sdhci_priv(host);
+
+	for (i = 0; i < BST_TUNING_COUNT; i++) {
+		/* Protected write */
+		sdhci_bst_crm_write(pltfm_host, REG_WR_PROTECT, REG_WR_PROTECT_KEY);
+		/* Write tuning value */
+		sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << i) - 1);
+
+		/* Wait for internal clock stable before tuning */
+		if (sdhci_bst_wait_int_clk(host)) {
+			dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n");
+			return -EBUSY;
+		}
+
+		ret = mmc_send_tuning(host->mmc, opcode, &error);
+		if (ret != 0) {
+			has_failure = 1;
+		} else {
+			if (has_failure == 0) {
+				if (first_start == -1)
+					first_start = i;
+				first_end = i;
+			} else {
+				if (second_start == -1)
+					second_start = i;
+				second_end = i;
+			}
+		}
+	}
+
+	/* Calculate best tuning value */
+	if (first_end - first_start >= second_end - second_start)
+		best = ((first_end - first_start) >> 1) + first_start;
+	else
+		best = ((second_end - second_start) >> 1) + second_start;
+
+	if (best < 0)
+		best = 0;
+
+	sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << best) - 1);
+	/* Confirm internal clock stable after setting best tuning value */
+	if (sdhci_bst_wait_int_clk(host)) {
+		dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n");
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+/* Enable voltage stable power for voltage switch */
+static void sdhci_bst_voltage_switch(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+	/* Enable voltage stable power */
+	sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, BST_VOL_STABLE_ON);
+}
+
+static const struct sdhci_ops sdhci_bst_ops = {
+	.set_clock		= sdhci_bst_set_clock,
+	.set_bus_width		= sdhci_set_bus_width,
+	.set_uhs_signaling	= sdhci_set_uhs_signaling,
+	.get_min_clock		= sdhci_bst_get_min_clock,
+	.get_max_clock		= sdhci_bst_get_max_clock,
+	.reset			= sdhci_bst_reset,
+	.set_power		= sdhci_bst_set_power,
+	.set_timeout		= sdhci_bst_set_timeout,
+	.platform_execute_tuning = sdhci_bst_execute_tuning,
+	.voltage_switch		= sdhci_bst_voltage_switch,
+};
+
+static const struct sdhci_pltfm_data sdhci_bst_pdata = {
+	.ops = &sdhci_bst_ops,
+	.quirks = SDHCI_QUIRK_BROKEN_ADMA |
+		  SDHCI_QUIRK_DELAY_AFTER_POWER |
+		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+		  SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
+	.quirks2 = SDHCI_QUIRK2_BROKEN_DDR50 |
+		   SDHCI_QUIRK2_TUNING_WORK_AROUND |
+		   SDHCI_QUIRK2_ACMD23_BROKEN,
+};
+
+static void sdhci_bst_free_bounce_buffer(struct sdhci_host *host)
+{
+	if (host->bounce_buffer) {
+		dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size,
+				  host->bounce_buffer, host->bounce_addr);
+		host->bounce_buffer = NULL;
+	}
+	of_reserved_mem_device_release(mmc_dev(host->mmc));
+}
+
+static int sdhci_bst_alloc_bounce_buffer(struct sdhci_host *host)
+{
+	struct mmc_host *mmc = host->mmc;
+	unsigned int bounce_size;
+	int ret;
+
+	/* Fixed SRAM bounce size to 32KB: verified config under 32-bit DMA addressing limit */
+	bounce_size = SZ_32K;
+
+	ret = of_reserved_mem_device_init_by_idx(mmc_dev(mmc), mmc_dev(mmc)->of_node, 0);
+	if (ret) {
+		dev_err(mmc_dev(mmc), "Failed to initialize reserved memory\n");
+		return ret;
+	}
+
+	host->bounce_buffer = dma_alloc_coherent(mmc_dev(mmc), bounce_size,
+						 &host->bounce_addr, GFP_KERNEL);
+	if (!host->bounce_buffer)
+		return -ENOMEM;
+
+	host->bounce_buffer_size = bounce_size;
+
+	return 0;
+}
+
+static int sdhci_bst_probe(struct platform_device *pdev)
+{
+	struct sdhci_pltfm_host *pltfm_host;
+	struct sdhci_host *host;
+	struct sdhci_bst_priv *priv;
+	int err;
+
+	host = sdhci_pltfm_init(pdev, &sdhci_bst_pdata, sizeof(struct sdhci_bst_priv));
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	pltfm_host = sdhci_priv(host);
+	priv = sdhci_pltfm_priv(pltfm_host); /* Get platform private data */
+
+	err = mmc_of_parse(host->mmc);
+	if (err)
+		return err;
+
+	sdhci_get_of_property(pdev);
+
+	/* Get CRM registers from the second reg entry */
+	priv->crm_reg_base = devm_platform_ioremap_resource(pdev, 1);
+	if (IS_ERR(priv->crm_reg_base)) {
+		err = PTR_ERR(priv->crm_reg_base);
+		return err;
+	}
+
+	/*
+	 * Silicon constraints for BST C1200:
+	 * - System RAM base is 0x800000000 (above 32-bit addressable range)
+	 * - The eMMC controller DMA engine is limited to 32-bit addressing
+	 * - SMMU cannot be used on this path due to hardware design flaws
+	 * - These are fixed in silicon and cannot be changed in software
+	 *
+	 * Bus/controller mapping:
+	 * - No registers are available to reprogram the address mapping
+	 * - The 32-bit DMA limit is a hard constraint of the controller IP
+	 *
+	 * Given these constraints, an SRAM-based bounce buffer in the 32-bit
+	 * address space is required to enable eMMC DMA on this platform.
+	 */
+	err = sdhci_bst_alloc_bounce_buffer(host);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to allocate bounce buffer: %d\n", err);
+		return err;
+	}
+
+	err = sdhci_add_host(host);
+	if (err)
+		goto err_free_bounce_buffer;
+
+	return 0;
+
+err_free_bounce_buffer:
+	sdhci_bst_free_bounce_buffer(host);
+
+	return err;
+}
+
+static void sdhci_bst_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+
+	sdhci_bst_free_bounce_buffer(host);
+	sdhci_pltfm_remove(pdev);
+}
+
+static const struct of_device_id sdhci_bst_ids[] = {
+	{ .compatible = "bst,c1200-sdhci" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sdhci_bst_ids);
+
+static struct platform_driver sdhci_bst_driver = {
+	.driver = {
+		.name = "sdhci-bst",
+		.of_match_table = sdhci_bst_ids,
+	},
+	.probe = sdhci_bst_probe,
+	.remove = sdhci_bst_remove,
+};
+module_platform_driver(sdhci_bst_driver);
+
+MODULE_DESCRIPTION("Black Sesame Technologies SDHCI driver (BST)");
+MODULE_AUTHOR("Black Sesame Technologies Co., Ltd.");
+MODULE_LICENSE("GPL");
-- 
2.43.0

[PATCH v5 4/6] arm64: dts: bst: enable eMMC controller in C1200 CDCU1.0 board

[Albert Yang]

Add eMMC controller support to the BST C1200 device tree:

- bstc1200.dtsi: Add mmc0 node for the DWCMSHC SDHCI controller
  with basic configuration (disabled by default)
- bstc1200.dtsi: Add fixed clock definition for MMC controller
- bstc1200-cdcu1.0-adas_4c2g.dts: Enable mmc0 with board-specific
  configuration including 8-bit bus width and reserved SRAM buffer

The bounce buffer in reserved SRAM addresses hardware constraints
where the eMMC controller cannot access main system memory through
SMMU due to a hardware bug, and all DRAM is located outside the
4GB boundary.

Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>

---
Changes for v5:
- Split from platform series per Arnd's feedback

Changes for v4:
- Change compatible to bst,c1200-sdhci
- Move bus-width and non-removable to board dts

Changes for v3:
- Split defconfig into dedicated patch

Changes for v2:
- Reorganize memory map, standardize interrupt definitions
---
 .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts    | 19 +++++++++++++++++++
 arch/arm64/boot/dts/bst/bstc1200.dtsi         | 18 ++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
index 5eb9ef369d8c..178ad4bf4f0a 100644
--- a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
+++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
@@ -17,6 +17,25 @@ memory@810000000 {
 		      <0x8 0xc0000000 0x1 0x0>,
 		      <0xc 0x00000000 0x0 0x40000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		mmc0_reserved: mmc0-reserved@5160000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x5160000 0x0 0x10000>;
+			no-map;
+		};
+	};
+};
+
+&mmc0 {
+	bus-width = <8>;
+	memory-region = <&mmc0_reserved>;
+	non-removable;
+	status = "okay";
 };
 
 &uart0 {
diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
index dd13c6bfc3c8..9660d8396e27 100644
--- a/arch/arm64/boot/dts/bst/bstc1200.dtsi
+++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
@@ -7,6 +7,12 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	clk_mmc: clock-4000000 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <4000000>;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -72,6 +78,18 @@ uart0: serial@20008000 {
 			status = "disabled";
 		};
 
+		mmc0: mmc@22200000 {
+			compatible = "bst,c1200-sdhci";
+			reg = <0x0 0x22200000 0x0 0x1000>,
+			      <0x0 0x23006000 0x0 0x1000>;
+			clocks = <&clk_mmc>;
+			clock-names = "core";
+			dma-coherent;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <200000000>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@32800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x32800000 0x0 0x10000>,
-- 
2.43.0

[PATCH v5 5/6] arm64: defconfig: enable BST SDHCI controller

[Albert Yang]

Enable CONFIG_MMC_SDHCI_BST to support eMMC on Black Sesame
Technologies C1200 boards.

Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>

---
Changes for v5:
- Split from platform series per Arnd's feedback

Changes for v4:
- Move CONFIG_MMC_SDHCI_BST before CONFIG_MMC_SDHCI_F_SDH30

Changes for v3:
- Split from arm64: dts patch

Changes for v2:
- Initial defconfig change included in DTS patch
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 45288ec9eaf7..7f4da3117329 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1222,6 +1222,7 @@ CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_BST=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_OF_ARASAN=y
 CONFIG_MMC_SDHCI_OF_ESDHC=y
-- 
2.43.0

Re: [PATCH v5 5/6] arm64: defconfig: enable BST SDHCI controller

[Krzysztof Kozlowski]

On 23/01/2026 10:53, Albert Yang wrote:
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 45288ec9eaf7..7f4da3117329 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1222,6 +1222,7 @@ CONFIG_MMC_BLOCK_MINORS=32
>  CONFIG_MMC_ARMMMCI=y
>  CONFIG_MMC_SDHCI=y
>  CONFIG_MMC_SDHCI_ACPI=y
> +CONFIG_MMC_SDHCI_BST=y

This is still wrongly ordered. Look at your Kconfig. Run savedefconfig.

Best regards,
Krzysztof

Re: [PATCH v5 5/6] arm64: defconfig: enable BST SDHCI controller

[Albert Yang]

On Sun, 8 Feb 2026 at 12:38, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 23/01/2026 10:53, Albert Yang wrote:
> > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> > index 45288ec9eaf7..7f4da3117329 100644
> > --- a/arch/arm64/configs/defconfig
> > +++ b/arch/arm64/configs/defconfig
> > @@ -1222,6 +1222,7 @@ CONFIG_MMC_BLOCK_MINORS=32
> >  CONFIG_MMC_ARMMMCI=y
> >  CONFIG_MMC_SDHCI=y
> >  CONFIG_MMC_SDHCI_ACPI=y
> > +CONFIG_MMC_SDHCI_BST=y
> 
> This is still wrongly ordered. Look at your Kconfig. Run savedefconfig.

Hi Krzysztof,

Thank you for catching this again. Sorry for the repeated mistake.

I incorrectly placed CONFIG_MMC_SDHCI_BST right after CONFIG_MMC_SDHCI_ACPI,
but in Kconfig, MMC_SDHCI_BST is defined after MMC_SDHCI_BCM_KONA (much later
than MMC_SDHCI_ACPI). I have now run savedefconfig and confirmed the correct
position is between CONFIG_MMC_SDHCI_TEGRA and CONFIG_MMC_SDHCI_F_SDH30:

  CONFIG_MMC_SDHCI_TEGRA=y
 +CONFIG_MMC_SDHCI_BST=y
  CONFIG_MMC_SDHCI_F_SDH30=y

Will fix this in v6 along with the DTS patch, which will be submitted to
the SoC tree as per Ulf's direction.

Best regards,
Albert

[PATCH v5 6/6] MAINTAINERS: add MMC files to BST entry

[Albert Yang]

Add the MMC device tree binding and driver files to the existing
ARM/BST SOC SUPPORT maintainer entry.

Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>

---
Changes for v5:
- Split from platform series per Arnd's feedback

Changes for v4:
- Changed driver file name to sdhci-of-bst.c

Changes for v3:
- Consolidate BST maintainer entries

Changes for v2:
- Initial MAINTAINERS entry in platform patch
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0d044a58cbfe..dc7f716f9811 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2596,7 +2596,9 @@ R:	BST Linux Kernel Upstream Group <bst-upstream@bstai.top>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Supported
 F:	Documentation/devicetree/bindings/arm/bst.yaml
+F:	Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml
 F:	arch/arm64/boot/dts/bst/
+F:	drivers/mmc/host/sdhci-of-bst.c
 
 ARM/CALXEDA HIGHBANK ARCHITECTURE
 M:	Andre Przywara <andre.przywara@arm.com>
-- 
2.43.0

Re: [PATCH v5 0/6] mmc: add support for BST C1200 SDHCI controller

[Ulf Hansson]

On Fri, 23 Jan 2026 at 10:53, Albert Yang <yangzh0906@thundersoft.com> wrote:
>
> This series adds MMC/eMMC controller support for Black Sesame Technologies
> C1200 SoC. BST is a leading automotive-grade computing SoC provider focusing
> on intelligent driving, computer vision, and AI capabilities for ADAS and
> autonomous driving applications. More information: https://bst.ai
>
> == Background ==
>
> This is the MMC portion split from the original v4 series [1] following
> feedback from Arnd Bergmann [2]. The platform support (vendor-prefix,
> SoC bindings, Kconfig ARCH_BST, base DTS, defconfig ARCH_BST) has already
> been merged into Linux 6.19 through the SoC tree [3].
>
> == Series Overview ==
>
> Patch 1: dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
> Patch 2: mmc: sdhci: allow drivers to pre-allocate bounce buffer
> Patch 3: mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver
> Patch 4: arm64: dts: bst: enable eMMC controller in C1200 CDCU1.0 board
> Patch 5: arm64: defconfig: enable BST SDHCI controller
> Patch 6: MAINTAINERS: add MMC files to BST entry
>
> == Testing ==
>
>   - checkpatch.pl: PASS (all patches)
>   - dt_binding_check: PASS
>   - dtbs_check (CHECK_DTBS=y): PASS
>   - Build tested with ARCH=arm64 defconfig
>
> == Changes since v4 ==
>
>   - Split: Platform patches merged separately via SoC tree; this series is
>     MMC-only, submitted to MMC maintainers
>
>   DT binding (patch 1):
>   - Rename file from bst,dwcmshc-sdhci.yaml to bst,c1200-sdhci.yaml
>   - Fix example compatible string to match property definition
>
>   Driver (patch 3):
>   - Fix compatible string to match dt-bindings (bst,c1200-sdhci)
>   - Simplify clock divider calculation with clearer frequency range logic
>   - Add linux/bits.h and linux/bitfield.h headers
>   - Remove unused linux/ioport.h header
>   - Rename SDHCI_TUNING_COUNT to BST_TUNING_COUNT
>   - Rename BST_EMMC_CTRL_BIT2 to BST_EMMC_CTRL_RST_N
>   - Fix BST_DEFAULT_MAX_FREQ from 2MHz to 200MHz
>   - Convert kernel-doc to regular comments (per Adrian Hunter)
>   - Add sdhci_bst_free_bounce_buffer() helper (per Adrian Hunter)
>
>
> == References ==
>
> [1] v4: https://lore.kernel.org/lkml/20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com/
> [2] Split: https://lore.kernel.org/lkml/09b1318e-21dc-4354-8733-866b70696295@app.fastmail.com/
> [3] Merged via soc-newsoc-6.19
>
> Albert Yang (6):
>   dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
>   mmc: sdhci: allow drivers to pre-allocate bounce buffer
>   mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver
>   arm64: dts: bst: enable eMMC controller in C1200 CDCU1.0 board
>   arm64: defconfig: enable BST SDHCI controller
>   MAINTAINERS: add MMC files to BST entry
>
>  .../bindings/mmc/bst,c1200-sdhci.yaml         |  70 +++
>  MAINTAINERS                                   |   2 +
>  .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts    |  19 +
>  arch/arm64/boot/dts/bst/bstc1200.dtsi         |  18 +
>  arch/arm64/configs/defconfig                  |   1 +
>  drivers/mmc/host/Kconfig                      |  14 +
>  drivers/mmc/host/Makefile                     |   1 +
>  drivers/mmc/host/sdhci-of-bst.c               | 521 ++++++++++++++++++
>  drivers/mmc/host/sdhci.c                      |   7 +
>  9 files changed, 653 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml
>  create mode 100644 drivers/mmc/host/sdhci-of-bst.c
>
> base-commit: 0f61b1860cc3f52aef9036d7235ed1f017632193
> --
> 2.43.0
>

Patch 1 to 3 and patch 6 applied for next, thanks!

The DTS patches (patch 4 and patch 5) should be picked up by the SoC maintainer.

Kind regards
Uffe

Re: [PATCH v5 0/6] mmc: add support for BST C1200 SDHCI controller

[Albert Yang]

Hi Ulf,

On Tue, 27 Jan 2026 at 12:01, Ulf Hansson <ulf.hansson@linaro.org> wrote:
>
> Patch 1 to 3 and patch 6 applied for next, thanks!
>
> The DTS patches (patch 4 and patch 5) should be picked up by the SoC maintainer.

Thank you for the review!

I will send the DTS and defconfig patches (original v5 patches 4 and 5)
separately to the SoC maintainers as a v6 series.

Best regards,
Albert