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Tue, 27 Jan 2026 19:37:24 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id 94C9140086; Tue, 27 Jan 2026 19:38:00 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 27 Jan 2026 11:37:59 +0000 Date: Tue, 27 Jan 2026 11:37:58 +0000 From: Jonathan Cameron To: Ryan Roberts CC: Will Deacon , Ard Biesheuvel , Catalin Marinas , Mark Rutland , Linus Torvalds , Oliver Upton , Marc Zyngier , "Dev Jain" , Linu Cherian , , Subject: Re: [PATCH v2 04/13] arm64: mm: Push __TLBI_VADDR() into __tlbi_level() Message-ID: <20260127113758.00005bea@huawei.com> In-Reply-To: <20260119172202.1681510-5-ryan.roberts@arm.com> References: <20260119172202.1681510-1-ryan.roberts@arm.com> <20260119172202.1681510-5-ryan.roberts@arm.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.15] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml500005.china.huawei.com (7.214.145.207) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260127_033809_060383_BD0C471D X-CRM114-Status: GOOD ( 15.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 19 Jan 2026 17:21:51 +0000 Ryan Roberts wrote: > From: Will Deacon > > The __TLBI_VADDR() macro takes an ASID and an address and converts them > into a single argument formatted correctly for a TLB invalidation > instruction. > > Rather than have callers worry about this (especially in the case where > the ASID is zero), push the macro down into __tlbi_level() via a new > __tlbi_level_asid() helper. > > Signed-off-by: Will Deacon > Reviewed-by: Linu Cherian > Signed-off-by: Ryan Roberts One comment inline, but not particularly important given it's about reducing readability of a workaround a little Reviewed-by: Jonathan Cameron > @@ -674,6 +679,7 @@ static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd) > #define huge_pmd_needs_flush huge_pmd_needs_flush > > #undef __tlbi_user > +#undef __TLBI_VADDR > #endif > > #endif > diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c > index 4a609e9b65de..ad4857df4830 100644 > --- a/arch/arm64/kernel/sys_compat.c > +++ b/arch/arm64/kernel/sys_compat.c > @@ -36,7 +36,7 @@ __do_compat_cache_op(unsigned long start, unsigned long end) > * The workaround requires an inner-shareable tlbi. > * We pick the reserved-ASID to minimise the impact. > */ > - __tlbi(aside1is, __TLBI_VADDR(0, 0)); > + __tlbi(aside1is, 0UL); Dropping the explicit ASID sort of looses some meaning here vs the comment just above it. Meh, it's in a work around so most folk will ignore it anyway if reading this code, so I don't mind that much. > dsb(ish); > } >