From: "Stefan Dösinger" <stefandoesinger@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: soc@lists.linux.dev, linus.walleij@linaro.org,
Jun Nie <jun.nie@linaro.org>, Arnd Bergmann <arnd@arndb.de>,
Drew Fustini <fustini@kernel.org>
Subject: [RFC PATCH v2 5/7] ARM: dts: Add an armv7 timer for zx297520v3.
Date: Wed, 28 Jan 2026 23:34:53 +0300 [thread overview]
Message-ID: <20260128203455.38569-6-stefandoesinger@gmail.com> (raw)
In-Reply-To: <20260128203455.38569-1-stefandoesinger@gmail.com>
The stock kernel does not use this timer, but it seems to work fine. The
board has other board-specific timers that would need a driver and I see
no reason to bother with them since the arm standard timer works.
The caveat is the non-standard GIC setup needed to handle the timer's
level-low PPI.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
arch/arm/boot/dts/zte/zx297520v3.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi
index d6c71d52b26c..ecd07f3fb8b3 100644
--- a/arch/arm/boot/dts/zte/zx297520v3.dtsi
+++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi
@@ -24,6 +24,15 @@ soc {
interrupt-parent = <&gic>;
ranges;
+ /* The GIC has a non-standard way of configuring ints between level-low/level
+ * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE
+ * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source
+ * seem wrong.
+ *
+ * Everything defaults to active-high/rising edge, but the timer is active-low. We
+ * currently rely on the boot loader to change timer IRQs to active-low for us for
+ * now.
+ */
gic: interrupt-controller@f2000000 {
compatible = "arm,gic-v3";
interrupt-controller;
@@ -33,5 +42,20 @@ gic: interrupt-controller@f2000000 {
reg = <0xf2000000 0x10000>,
<0xf2040000 0x20000>;
};
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <26000000>;
+ interrupt-parent = <&gic>;
+ /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the
+ * arm timer at all. Since this is a single CPU system I don't think it
+ * really matters that the offset is random though.
+ */
+ arm,cpu-registers-not-fw-configured;
+ };
};
};
--
2.52.0
next prev parent reply other threads:[~2026-01-28 20:35 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 20:34 [RFC PATCH v2 0/7] Add support for ZTE zx297520v3 Stefan Dösinger
2026-01-28 20:34 ` [RFC PATCH v2 1/7] ARM: zte: Add zx297520v3 platform support Stefan Dösinger
2026-01-30 9:07 ` Linus Walleij
2026-01-30 16:37 ` Stefan Dösinger
2026-02-02 9:09 ` Linus Walleij
2026-02-02 17:38 ` Stefan Dösinger
2026-01-28 20:34 ` [RFC PATCH v2 2/7] dt-bindings: arm: Add zx297520v3 board binding Stefan Dösinger
2026-01-28 20:34 ` [RFC PATCH v2 3/7] ARM: dts: Add D-Link DWR-932M support Stefan Dösinger
2026-01-28 20:34 ` [RFC PATCH v2 4/7] ARM: zte: Add support for zx29 low level debug Stefan Dösinger
2026-01-28 20:34 ` Stefan Dösinger [this message]
2026-01-28 20:34 ` [RFC PATCH v2 6/7] ARM: zte: Bring back ZX29 UART support Stefan Dösinger
2026-01-28 20:34 ` [RFC PATCH v2 7/7] ARM: dts: Declare UART1 on zx297520v3 boards Stefan Dösinger
2026-01-28 22:00 ` [RFC PATCH v2 0/7] Add support for ZTE zx297520v3 Arnd Bergmann
2026-01-29 19:38 ` Stefan Dösinger
2026-01-30 8:58 ` Arnd Bergmann
2026-01-30 10:17 ` Linus Walleij
2026-01-30 14:08 ` Robin Murphy
2026-01-30 14:02 ` Andre Przywara
2026-01-30 15:02 ` Stefan Dösinger
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