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Date: Wed, 28 Jan 2026 23:34:53 +0300 Message-ID: <20260128203455.38569-6-stefandoesinger@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128203455.38569-1-stefandoesinger@gmail.com> References: <20260128203455.38569-1-stefandoesinger@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260128_123515_988332_1EF63187 X-CRM114-Status: GOOD ( 16.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The stock kernel does not use this timer, but it seems to work fine. The board has other board-specific timers that would need a driver and I see no reason to bother with them since the arm standard timer works. The caveat is the non-standard GIC setup needed to handle the timer's level-low PPI. Signed-off-by: Stefan Dösinger --- arch/arm/boot/dts/zte/zx297520v3.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi index d6c71d52b26c..ecd07f3fb8b3 100644 --- a/arch/arm/boot/dts/zte/zx297520v3.dtsi +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi @@ -24,6 +24,15 @@ soc { interrupt-parent = <&gic>; ranges; + /* The GIC has a non-standard way of configuring ints between level-low/level + * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE + * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source + * seem wrong. + * + * Everything defaults to active-high/rising edge, but the timer is active-low. We + * currently rely on the boot loader to change timer IRQs to active-low for us for + * now. + */ gic: interrupt-controller@f2000000 { compatible = "arm,gic-v3"; interrupt-controller; @@ -33,5 +42,20 @@ gic: interrupt-controller@f2000000 { reg = <0xf2000000 0x10000>, <0xf2040000 0x20000>; }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <26000000>; + interrupt-parent = <&gic>; + /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the + * arm timer at all. Since this is a single CPU system I don't think it + * really matters that the offset is random though. + */ + arm,cpu-registers-not-fw-configured; + }; }; }; -- 2.52.0