* Re: [v5,2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
[not found] <939fdaf94038613486bdbba510a92a1e57e18c71.1769592679.git.dan.carpenter@linaro.org>
@ 2026-01-29 5:10 ` Jakub Kicinski
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From: Jakub Kicinski @ 2026-01-29 5:10 UTC (permalink / raw)
To: dan.carpenter
Cc: Jakub Kicinski, jan.petrous, davem, edumazet, pabeni,
mcoquelin.stm32, imx, chester62515, mbrugger, netdev, s32,
conor+dt, andrew+netdev, robh, kernel, linux-stm32, shawnguo,
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alexandre.torgue, krzk+dt, devicetree, festevam, s.hauer
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---
dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
This commit adds the nxp,phy-sel property to the S32 DWMAC binding,
allowing access to the GMAC_0_CTRL_STS register via a syscon interface
instead of the previous ad-hoc direct register mapping.
> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..65633b10e49e 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
[ ... ]
> + nxp,phy-sel:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to the GPR syscon node
> + - description: offset of PHY selection register
> + description:
> + This phandle points to the GMAC_0_CTRL_STS register which controls the
> + GMAC_0 configuration options. The register lets you select the PHY
> + interface and the PHY mode. It also controls if the FTM_0 or FTM_1
> + FlexTimer Modules connect to GMAC_O.
^^^^^^
Should this be GMAC_0 (with a zero) instead of GMAC_O (with a letter O)?
The rest of the description uses GMAC_0_CTRL_STS and GMAC_0 consistently.
--
pw-bot: cr
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