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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WRaPh/VZki+helQnwkSi0HWdEvPyMZkTvDeK3wOd343LLoADe/+LKNilvw6pRSX99a1glYGecJd5qzsETs5L9QPOqj8BWfpqw6pRdl6gpQr3EGBEZ+pOOtRAxgLRndfJr1X7W1Jw+J/joP3IGCph0j2szsxzJFLxVH/3MN5shgmkgnG8PkiPuK8+Ksn2g8KF1XWEsy72jjTTz3yh6GrtS27TVchDA7xayL9Q/nKHf0MQMpMqKVMxYQWOt+wLHusCr8WgHcil9/f+SSF5LalNL9BgvPgCWy/cLSBjg6vFMGgubAMY0Hevl12O8NOt5l6KWVJtPCDIGPzy6ff4senN2G1b2Ag9Xz4uNejQ3EZULjmmaaRuYnZYrxJPNFJox/LQxM75oNHM2TYkvP4v+NYBXxAzkYzsfkemWXQS9kxE88g54ym3WVNWtyt2Rf46Ub1s X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2026 19:19:15.8638 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd8965c9-701a-4cc0-0c5a-08de65b49e6b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR10MB6870 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260206_111924_075817_C4A606E8 X-CRM114-Status: GOOD ( 10.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for detecting AM62P silicon revisions using the NVMEM framework to read the GP_SW1 register. Background: =========== On AM62P SoCs, the standard JTAGID register does not provide information on silicon revision, instead the GP_SW1 register contains the information needed for proper device identification. Proper silicon revision detection is required to apply proper workarounds and quirks for different silicon revisions, particularly for MMCSD [0]. Implementation history: ======================= An initial implementation [0] added a second register range directly to the chipid node to access GP_SW registers. Following upstream review feedback to split the patches appropriately, an alternative RFC approach [1] was explored that introduced a new NVMEM eFuse binding specifically for TI K3 SoCs. This final implementation takes a simpler approach by leveraging the existing NVMEM framework with optional nvmem-cells support. The k3-socinfo driver can now optionally consume silicon revision data from the NVMEM provider, making it more flexible and avoiding the need for either direct register access or new bindings. Implementation details: ======================= - NVMEM support is fully optional - the driver continues to work without it and falls back to SR1.0 for AM62P devices - When NVMEM cells are present, the driver reads GP_SW1 to accurately detect SR1.1 and SR1.2 variants Changelog: ========== since v1: - Drop valid bit check, and determine all silicon revisions from ADR register bits - In k3_chipinfo_get_gpsw_variant, merge detection of final return value and return action - k3_chipinfo_get_gpsw_variant parameter: switch pdev to dev Revisions: ========== v1: https://lore.kernel.org/all/20260204213746.2589028-1-jm@ti.com/ [0] https://lore.kernel.org/linux-mmc/20250805234950.3781367-1-jm@ti.com/ [1] https://lore.kernel.org/all/20250924210735.1732423-1-jm@ti.com/ Judith Mendez (2): dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells support soc: ti: k3-socinfo: Add support for AM62P variants via NVMEM .../bindings/hwinfo/ti,k3-socinfo.yaml | 12 ++++++ drivers/soc/ti/k3-socinfo.c | 41 +++++++++++++++++-- 2 files changed, 50 insertions(+), 3 deletions(-) -- 2.52.0