[PATCH 00/11] ARM: rockchip: Add initial RV1103B and Omega4 board support

[PATCH 00/11] ARM: rockchip: Add initial RV1103B and Omega4 board support

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

This series adds initial support for the Rockchip RV1103B SoC and
the Omega4 board.

The goal of this series is to provide the minimal device tree and
platform support required to boot the Omega4 board into Linux
userspace with the root filesystem located on SPI NAND.

The series includes:

  - Base RV1103B SoC device tree description
  - Omega4 board device tree
  - Required pinctrl and clock definitions
  - Basic peripheral enablement required for boot

With this series applied, the Omega4 board is able to:

  - Initialize DRAM
  - Boot the kernel
  - Access SPI NAND
  - Mount the root filesystem from SPI NAND
  - Reach userspace successfully

This submission intentionally focuses on minimal bring-up support.
Additional peripheral enablement and feature support will be
submitted separately.

Tested on Omega4 hardware based on the RV1103B SoC.

Boot verified with root filesystem stored on SPI NAND.

Fabio Estevam (11):
  dt-bindings: clock: rockchip: Add RV1103B clock and reset unit
  dt-bindings: clk: rockchip: Add RV1103B clock header
  clk: rockchip: Add clock controller for the RV1103B
  dt-bindings: pinctrl: Add RV1103B pinctrl support
  pinctrl: rockchip: Add RV1103B pinctrl support
  dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for R1103B
  dt-bindings: serial: snps-dw-apb-uart: Add support for RV1103B
  dt-bindings: soc: rockchip: Add RV1103B IOC and GRF entries
  ARM: dts: rockchip: Add support for RV1103B
  dt-bindings: arm: rockchip: Add Onion RV1103B Omega4
  ARM: dts: rockchip: Add Onion RV1103B Omega4

 .../devicetree/bindings/arm/rockchip.yaml     |   5 +
 .../bindings/clock/rockchip,rv1103b-cru.yaml  |  63 ++
 .../bindings/mmc/rockchip-dw-mshc.yaml        |   1 +
 .../bindings/pinctrl/rockchip,pinctrl.yaml    |   1 +
 .../bindings/serial/snps-dw-apb-uart.yaml     |   1 +
 .../devicetree/bindings/soc/rockchip/grf.yaml |   2 +
 arch/arm/boot/dts/rockchip/Makefile           |   1 +
 arch/arm/boot/dts/rockchip/rv1103b-omega4.dts |  92 ++
 .../boot/dts/rockchip/rv1103b-pinctrl.dtsi    | 831 ++++++++++++++++++
 arch/arm/boot/dts/rockchip/rv1103b.dtsi       | 266 ++++++
 drivers/clk/rockchip/Kconfig                  |   7 +
 drivers/clk/rockchip/Makefile                 |   1 +
 drivers/clk/rockchip/clk-rv1103b.c            | 670 ++++++++++++++
 drivers/clk/rockchip/clk.h                    |  49 ++
 drivers/pinctrl/pinctrl-rockchip.c            | 313 ++++++-
 drivers/pinctrl/pinctrl-rockchip.h            |   1 +
 .../dt-bindings/clock/rockchip,rv1103b-cru.h  | 488 ++++++++++
 17 files changed, 2791 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103b-omega4.dts
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103b.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rv1103b.c
 create mode 100644 include/dt-bindings/clock/rockchip,rv1103b-cru.h

-- 
2.34.1

[PATCH 01/11] dt-bindings: clock: rockchip: Add RV1103B clock and reset unit

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

Add device tree bindings for the clock and reset unit for the RV1103B SoC.

Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 .../bindings/clock/rockchip,rv1103b-cru.yaml  | 63 +++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml
new file mode 100644
index 000000000000..fa7298955aea
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1103b-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RV1103B Clock and Reset Unit
+
+maintainers:
+  - Fabio Estevam <festevam@nabladev.com>
+  - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+  The RV1103B clock controller generates and supplies clocks to various
+  controllers within the SoC and also implements a reset controller for SoC
+  peripherals.
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All available clocks are defined as
+  preprocessor macros in the dt-bindings/clock/rockchip,rv1103b-cru.h header
+  and can be used in device tree sources. Similar macros exist for the reset
+  sources in these files.
+  There are several clocks that are generated outside the SoC. It is expected
+  that they are defined using standard clock bindings with following
+  clock-output-names:
+    - "xin24m"   - crystal input                              - required
+    - "xin32k"   - rtc clock                                  - optional
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rv1103b-cru
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@20000000 {
+      compatible = "rockchip,rv1103b-cru";
+      reg = <0x20000000 0x81000>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
-- 
2.34.1

[PATCH 02/11] dt-bindings: clk: rockchip: Add RV1103B clock header

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

Add the RV1103B clock and reset IDs.

Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 .../dt-bindings/clock/rockchip,rv1103b-cru.h  | 488 ++++++++++++++++++
 1 file changed, 488 insertions(+)
 create mode 100644 include/dt-bindings/clock/rockchip,rv1103b-cru.h

diff --git a/include/dt-bindings/clock/rockchip,rv1103b-cru.h b/include/dt-bindings/clock/rockchip,rv1103b-cru.h
new file mode 100644
index 000000000000..92c994185354
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1103b-cru.h
@@ -0,0 +1,488 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
+
+/* pll clocks */
+#define PLL_GPLL				1
+#define ARMCLK					2
+#define PLL_DPLL				3
+
+/* clk (clocks) */
+#define XIN_OSC0_HALF				5
+#define CLK_GPLL_DIV24				6
+#define CLK_GPLL_DIV12				7
+#define CLK_GPLL_DIV6				8
+#define CLK_GPLL_DIV4				9
+#define CLK_GPLL_DIV3				10
+#define CLK_GPLL_DIV2P5				11
+#define CLK_GPLL_DIV2				12
+#define CLK_UART0_SRC				13
+#define CLK_UART1_SRC				14
+#define CLK_UART2_SRC				15
+#define CLK_UART0_FRAC				16
+#define CLK_UART1_FRAC				17
+#define CLK_UART2_FRAC				18
+#define CLK_SAI_SRC				19
+#define CLK_SAI_FRAC				20
+#define LSCLK_NPU_SRC				21
+#define CLK_NPU_SRC				22
+#define ACLK_VEPU_SRC				23
+#define CLK_VEPU_SRC				24
+#define ACLK_VI_SRC				25
+#define CLK_ISP_SRC				26
+#define DCLK_VICAP				27
+#define CCLK_EMMC				28
+#define CCLK_SDMMC0				29
+#define SCLK_SFC_2X				30
+#define LSCLK_PERI_SRC				31
+#define ACLK_PERI_SRC				32
+#define HCLK_HPMCU				33
+#define SCLK_UART0				34
+#define SCLK_UART1				35
+#define SCLK_UART2				36
+#define CLK_I2C_PMU				37
+#define CLK_I2C_PERI				38
+#define CLK_SPI0				39
+#define CLK_PWM0_SRC				40
+#define CLK_PWM1				41
+#define CLK_PWM2				42
+#define DCLK_DECOM_SRC				43
+#define CCLK_SDMMC1				44
+#define CLK_CORE_CRYPTO				45
+#define CLK_PKA_CRYPTO				46
+#define CLK_CORE_RGA				47
+#define MCLK_SAI_SRC				48
+#define CLK_FREQ_PWM0_SRC			49
+#define CLK_COUNTER_PWM0_SRC			50
+#define PCLK_TOP_ROOT				51
+#define CLK_REF_MIPI0				52
+#define CLK_MIPI0_OUT2IO			53
+#define CLK_REF_MIPI1				54
+#define CLK_MIPI1_OUT2IO			55
+#define MCLK_SAI_OUT2IO				56
+#define ACLK_NPU_ROOT				57
+#define HCLK_RKNN				58
+#define ACLK_RKNN				59
+#define LSCLK_VEPU_ROOT				60
+#define HCLK_VEPU				61
+#define ACLK_VEPU				62
+#define CLK_CORE_VEPU				63
+#define PCLK_IOC_VCCIO3				64
+#define PCLK_ACODEC				65
+#define PCLK_USBPHY				66
+#define LSCLK_VI_100M				67
+#define LSCLK_VI_ROOT				68
+#define HCLK_ISP				69
+#define ACLK_ISP				70
+#define CLK_CORE_ISP				71
+#define ACLK_VICAP				72
+#define HCLK_VICAP				73
+#define ISP0CLK_VICAP				74
+#define PCLK_CSI2HOST0				75
+#define PCLK_CSI2HOST1				76
+#define HCLK_EMMC				77
+#define HCLK_SFC				78
+#define HCLK_SFC_XIP				79
+#define HCLK_SDMMC0				80
+#define PCLK_CSIPHY				81
+#define PCLK_GPIO1				82
+#define DBCLK_GPIO1				83
+#define PCLK_IOC_VCCIO47			84
+#define LSCLK_DDR_ROOT				85
+#define CLK_TIMER_DDRMON			86
+#define LSCLK_PMU_ROOT				87
+#define PCLK_PMU				88
+#define XIN_RC_DIV				89
+#define CLK_32K					90
+#define PCLK_PMU_GPIO0				91
+#define DBCLK_PMU_GPIO0				92
+#define CLK_DDR_FAIL_SAFE			93
+#define PCLK_PMU_HP_TIMER			94
+#define CLK_PMU_32K_HP_TIMER			95
+#define PCLK_PWM0				96
+#define CLK_PWM0				97
+#define CLK_OSC_PWM0				98
+#define CLK_RC_PWM0				99
+#define CLK_FREQ_PWM0				100
+#define CLK_COUNTER_PWM0			101
+#define PCLK_I2C0				102
+#define CLK_I2C0				103
+#define PCLK_UART0				104
+#define PCLK_IOC_PMUIO0				105
+#define CLK_REFOUT				106
+#define CLK_PREROLL				107
+#define CLK_PREROLL_32K				108
+#define CLK_LPMCU_PMU				109
+#define PCLK_SPI2AHB				110
+#define HCLK_SPI2AHB				111
+#define SCLK_SPI2AHB				112
+#define PCLK_WDT_LPMCU				113
+#define TCLK_WDT_LPMCU				114
+#define HCLK_SFC_PMU1				115
+#define HCLK_SFC_XIP_PMU1			116
+#define SCLK_SFC_2X_PMU1			117
+#define CLK_LPMCU				118
+#define CLK_LPMCU_RTC				119
+#define PCLK_LPMCU_MAILBOX			120
+#define PCLK_IOC_PMUIO1				121
+#define PCLK_CRU_PMU1				122
+#define PCLK_PERI_ROOT				123
+#define PCLK_RTC_ROOT				124
+#define CLK_TIMER_ROOT				125
+#define PCLK_TIMER				126
+#define CLK_TIMER0				127
+#define CLK_TIMER1				128
+#define CLK_TIMER2				129
+#define CLK_TIMER3				130
+#define CLK_TIMER4				131
+#define CLK_TIMER5				132
+#define PCLK_STIMER				133
+#define CLK_STIMER0				134
+#define CLK_STIMER1				135
+#define PCLK_WDT_NS				136
+#define TCLK_WDT_NS				137
+#define PCLK_WDT_S				138
+#define TCLK_WDT_S				139
+#define PCLK_WDT_HPMCU				140
+#define TCLK_WDT_HPMCU				141
+#define PCLK_I2C1				142
+#define CLK_I2C1				143
+#define PCLK_I2C2				144
+#define CLK_I2C2				145
+#define PCLK_I2C3				146
+#define CLK_I2C3				147
+#define PCLK_I2C4				148
+#define CLK_I2C4				149
+#define PCLK_SPI0				150
+#define PCLK_PWM1				151
+#define CLK_OSC_PWM1				152
+#define PCLK_PWM2				153
+#define CLK_OSC_PWM2				154
+#define PCLK_UART2				155
+#define PCLK_UART1				156
+#define ACLK_RKDMA				157
+#define PCLK_TSADC				158
+#define CLK_TSADC				159
+#define CLK_TSADC_TSEN				160
+#define PCLK_SARADC				161
+#define CLK_SARADC				162
+#define PCLK_GPIO2				163
+#define DBCLK_GPIO2				164
+#define PCLK_IOC_VCCIO6				165
+#define ACLK_USBOTG				166
+#define CLK_REF_USBOTG				167
+#define HCLK_SDMMC1				168
+#define HCLK_SAI				169
+#define MCLK_SAI				170
+#define ACLK_CRYPTO				171
+#define HCLK_CRYPTO				172
+#define HCLK_RK_RNG_NS				173
+#define HCLK_RK_RNG_S				174
+#define PCLK_OTPC_NS				175
+#define CLK_OTPC_ROOT_NS			176
+#define CLK_SBPI_OTPC_NS			177
+#define CLK_USER_OTPC_NS			178
+#define PCLK_OTPC_S				179
+#define CLK_OTPC_ROOT_S				180
+#define CLK_SBPI_OTPC_S				181
+#define CLK_USER_OTPC_S				182
+#define CLK_OTPC_ARB				183
+#define PCLK_OTP_MASK				184
+#define HCLK_RGA				185
+#define ACLK_RGA				186
+#define ACLK_MAC				187
+#define PCLK_MAC				188
+#define CLK_MACPHY				189
+#define ACLK_SPINLOCK				190
+#define HCLK_CACHE				191
+#define PCLK_HPMCU_MAILBOX			192
+#define PCLK_HPMCU_INTMUX			193
+#define CLK_HPMCU				194
+#define CLK_HPMCU_RTC				195
+#define DCLK_DECOM				196
+#define ACLK_DECOM				197
+#define PCLK_DECOM				198
+#define ACLK_SYS_SRAM				199
+#define PCLK_DMA2DDR				200
+#define ACLK_DMA2DDR				201
+#define PCLK_DCF				202
+#define ACLK_DCF				203
+#define MCLK_ACODEC_TX				204
+#define SCLK_UART0_SRC				205
+#define SCLK_UART1_SRC				206
+#define SCLK_UART2_SRC				207
+#define XIN_RC_SRC				208
+#define CLK_UTMI_USBOTG				209
+#define CLK_REF_USBPHY				230
+
+// PERICRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_ARESETN_PERI_BIU			0x00000002
+#define SRST_HRESETN_HPMCU_BIU			0x00000003
+#define SRST_LSRESETN_PERI_BIU			0x00000004
+#define SRST_PRESETN_PERI_BIU			0x00000005
+#define SRST_PRESETN_RTC_BIU			0x00000006
+#define SRST_HRESETN_BOOTROM			0x00000007
+
+// PERICRU_SOFTRST_CON01(Offset:0xA04)
+#define SRST_PRESETN_TIMER			0x00000010
+#define SRST_RESETN_TIMER0			0x00000011
+#define SRST_RESETN_TIMER1			0x00000012
+#define SRST_RESETN_TIMER2			0x00000013
+#define SRST_RESETN_TIMER3			0x00000014
+#define SRST_RESETN_TIMER4			0x00000015
+#define SRST_RESETN_TIMER5			0x00000016
+#define SRST_PRESETN_STIMER			0x00000017
+#define SRST_RESETN_STIMER0			0x00000018
+#define SRST_RESETN_STIMER1			0x00000019
+
+// PERICRU_SOFTRST_CON02(Offset:0xA08)
+#define SRST_PRESETN_WDT_NS			0x00000020
+#define SRST_TRESETN_WDT_NS			0x00000021
+#define SRST_PRESETN_WDT_S			0x00000022
+#define SRST_TRESETN_WDT_S			0x00000023
+#define SRST_PRESETN_WDT_HPMCU			0x00000024
+#define SRST_TRESETN_WDT_HPMCU			0x00000025
+#define SRST_PRESETN_I2C1			0x00000026
+#define SRST_RESETN_I2C1			0x00000027
+#define SRST_PRESETN_I2C2			0x00000028
+#define SRST_RESETN_I2C2			0x00000029
+#define SRST_PRESETN_I2C3			0x0000002A
+#define SRST_RESETN_I2C3			0x0000002B
+#define SRST_PRESETN_I2C4			0x0000002C
+#define SRST_RESETN_I2C4			0x0000002D
+
+// PERICRU_SOFTRST_CON03(Offset:0xA0C)
+#define SRST_PRESETN_UART2			0x00000030
+#define SRST_SRESETN_UART2			0x00000031
+#define SRST_PRESETN_UART1			0x00000032
+#define SRST_SRESETN_UART1			0x00000033
+#define SRST_PRESETN_SPI0			0x0000003A
+#define SRST_RESETN_SPI0			0x0000003B
+
+// PERICRU_SOFTRST_CON04(Offset:0xA10)
+#define SRST_PRESETN_PWM1			0x00000046
+#define SRST_RESETN_PWM1			0x00000047
+#define SRST_PRESETN_PWM2			0x0000004C
+#define SRST_RESETN_PWM2			0x0000004D
+
+// PERICRU_SOFTRST_CON05(Offset:0xA14)
+#define SRST_ARESETN_RKDMA			0x00000058
+#define SRST_PRESETN_TSADC			0x00000059
+#define SRST_RESETN_TSADC			0x0000005A
+#define SRST_PRESETN_SARADC			0x0000005C
+#define SRST_RESETN_SARADC			0x0000005D
+
+// PERICRU_SOFTRST_CON06(Offset:0xA18)
+#define SRST_RESETN_SARADC_PHY			0x00000060
+#define SRST_PRESETN_RTC_TEST			0x00000061
+#define SRST_PRESETN_GPIO2			0x00000063
+#define SRST_DBRESETN_GPIO2			0x00000064
+#define SRST_PRESETN_IOC_VCCIO6			0x00000065
+#define SRST_PRESETN_PERI_SGRF			0x00000066
+#define SRST_PRESETN_PERI_GRF			0x00000067
+#define SRST_PRESETN_CRU_PERI			0x00000068
+#define SRST_ARESETN_USBOTG			0x00000069
+
+// PERICRU_SOFTRST_CON07(Offset:0xA1C)
+#define SRST_HRESETN_SDMMC1			0x00000070
+#define SRST_HRESETN_SAI			0x00000071
+#define SRST_MRESETN_SAI			0x00000072
+
+// PERICRU_SOFTRST_CON08(Offset:0xA20)
+#define SRST_RESETN_CORE_CRYPTO			0x00000080
+#define SRST_RESETN_PKA_CRYPTO			0x00000081
+#define SRST_ARESETN_CRYPTO			0x00000082
+#define SRST_HRESETN_CRYPTO			0x00000083
+#define SRST_HRESETN_RK_RNG_NS			0x00000084
+#define SRST_HRESETN_RK_RNG_S			0x00000085
+#define SRST_PRESETN_OTPC_NS			0x00000086
+#define SRST_RESETN_SBPI_OTPC_NS		0x00000088
+#define SRST_RESETN_USER_OTPC_NS		0x00000089
+#define SRST_PRESETN_OTPC_S			0x0000008A
+#define SRST_RESETN_SBPI_OTPC_S			0x0000008C
+#define SRST_RESETN_USER_OTPC_S			0x0000008D
+#define SRST_RESETN_OTPC_ARB			0x0000008E
+#define SRST_PRESETN_OTP_MASK			0x0000008F
+
+// PERICRU_SOFTRST_CON09(Offset:0xA24)
+#define SRST_HRESETN_RGA			0x00000090
+#define SRST_ARESETN_RGA			0x00000091
+#define SRST_RESETN_CORE_RGA			0x00000092
+#define SRST_ARESETN_MAC			0x00000093
+#define SRST_RESETN_MACPHY			0x0000009B
+
+// PERICRU_SOFTRST_CON10(Offset:0xA28)
+#define SRST_ARESETN_SPINLOCK			0x000000A0
+#define SRST_HRESETN_CACHE			0x000000A1
+#define SRST_PRESETN_HPMCU_MAILBOX		0x000000A2
+#define SRST_PRESETN_HPMCU_INTMUX		0x000000A3
+#define SRST_RESETN_HPMCU_FULL_CLUSTER		0x000000A4
+#define SRST_RESETN_HPMCU_PWUP			0x000000A5
+#define SRST_RESETN_HPMCU_ONLY_CORE		0x000000A6
+#define SRST_TRESETN_HPMCU_JTAG			0x000000A7
+
+// PERICRU_SOFTRST_CON11(Offset:0xA2C)
+#define SRST_DRESETN_DECOM			0x000000B0
+#define SRST_ARESETN_DECOM			0x000000B1
+#define SRST_PRESETN_DECOM			0x000000B2
+#define SRST_ARESETN_SYS_SRAM			0x000000B3
+#define SRST_PRESETN_DMA2DDR			0x000000B4
+#define SRST_ARESETN_DMA2DDR			0x000000B5
+#define SRST_PRESETN_DCF			0x000000B6
+#define SRST_ARESETN_DCF			0x000000B7
+#define SRST_RESETN_USBPHY_POR			0x000000BC
+#define SRST_RESETN_USBPHY_OTG			0x000000BD
+
+// ======================= VEPUCRU module definition bank=1 =======================
+// VEPUCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_ARESETN_VEPU_BIU			0x00040001
+#define SRST_LSRESETN_VEPU_BIU			0x00040002
+#define SRST_RESETN_REF_PVTPLL_VEPU		0x00040003
+#define SRST_HRESETN_VEPU			0x00040004
+#define SRST_ARESETN_VEPU			0x00040005
+#define SRST_RESETN_CORE_VEPU			0x00040006
+#define SRST_PRESETN_VEPU_PVTPLL		0x00040007
+#define SRST_PRESETN_CRU_VEPU			0x00040008
+#define SRST_PRESETN_VEPU_GRF			0x0004000A
+#define SRST_PRESETN_IOC_VCCIO3			0x0004000B
+#define SRST_PRESETN_ACODEC			0x0004000D
+#define SRST_PRESETN_USBPHY			0x0004000E
+
+// ======================= NPUCRU module definition bank=2 ========================
+// NPUCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_RESETN_REF_PVTPLL_NPU		0x00080000
+#define SRST_ARESETN_NPU_BIU			0x00080002
+#define SRST_LSRESETN_NPU_BIU			0x00080003
+#define SRST_HRESETN_RKNN			0x00080004
+#define SRST_ARESETN_RKNN			0x00080005
+#define SRST_PRESETN_NPU_PVTPLL			0x00080006
+#define SRST_PRESETN_CRU_NPU			0x00080007
+#define SRST_PRESETN_NPU_GRF			0x00080009
+
+// ======================== VICRU module definition bank=3 ========================
+// VICRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_LSRESETN_VI_BIU			0x000c0001
+#define SRST_ARESETN_VI_BIU			0x000c0002
+#define SRST_RESETN_REF_PVTPLL_ISP		0x000c0003
+#define SRST_RESETN_CORE_ISP			0x000c0006
+
+// VICRU_SOFTRST_CON01(Offset:0xA04)
+#define SRST_DRESETN_VICAP			0x000c0010
+#define SRST_ARESETN_VICAP			0x000c0012
+#define SRST_HRESETN_VICAP			0x000c0013
+#define SRST_ISP0RESETN_VICAP			0x000c0018
+#define SRST_PRESETN_CSI2HOST0			0x000c0019
+#define SRST_PRESETN_CSI2HOST1			0x000c001B
+#define SRST_SRESETN_SFC_2X			0x000c001C
+#define SRST_HRESETN_EMMC			0x000c001D
+#define SRST_HRESETN_SFC			0x000c001E
+#define SRST_HRESETN_SFC_XIP			0x000c001F
+
+// VICRU_SOFTRST_CON02(Offset:0xA08)
+#define SRST_HRESETN_SDMMC0			0x000c0020
+#define SRST_PRESETN_CSIPHY			0x000c0022
+#define SRST_PRESETN_GPIO1			0x000c0023
+#define SRST_DBRESETN_GPIO1			0x000c0024
+#define SRST_PRESETN_IOC_VCCIO47		0x000c0025
+#define SRST_PRESETN_VI_GRF			0x000c0026
+#define SRST_PRESETN_CRU_VI			0x000c0028
+#define SRST_PRESETN_VI_PVTPLL			0x000c0029
+
+// ======================= CORECRU module definition bank=4 =======================
+// CORECRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_RESETN_REF_PVTPLL_CORE		0x00100000
+#define SRST_NCOREPORESET			0x00100001
+#define SRST_NCORESET				0x00100002
+#define SRST_NDBGRESET				0x00100003
+#define SRST_NL2RESET				0x00100004
+#define SRST_ARESETN_CORE_BIU			0x00100005
+#define SRST_PRESETN_CORE_BIU			0x00100006
+#define SRST_HRESETN_CORE_BIU			0x00100007
+#define SRST_PRESETN_DBG			0x00100008
+#define SRST_POTRESETN_DBG			0x00100009
+#define SRST_NTRESETN_DBG			0x0010000A
+
+// ======================= DDRCRU module definition bank=5 ========================
+// DDRCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_LSRESETN_DDR_BIU			0x00140001
+#define SRST_PRESETN_DDRC			0x00140002
+#define SRST_PRESETN_DDRMON			0x00140003
+#define SRST_RESETN_TIMER_DDRMON		0x00140004
+#define SRST_PRESETN_DFICTRL			0x00140005
+#define SRST_PRESETN_DDR_GRF			0x00140006
+#define SRST_PRESETN_CRU_DDR			0x00140007
+#define SRST_HRESETN_DDRPHY			0x00140008
+
+// ====================== SUBDDRCRU module definition bank=6 ======================
+// SUBDDRCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_RESETN_DDR_BIU			0x00160001
+#define SRST_ARESETN_DDRSCH_CPU			0x00160002
+#define SRST_ARESETN_DDRSCH_VI			0x00160004
+#define SRST_ARESETN_DDRSCH_NPVD		0x00160005
+#define SRST_RESETN_CORE_DDRC			0x00160006
+#define SRST_RESETN_DDRMON			0x00160007
+#define SRST_RESETN_DFICTRL			0x00160008
+#define SRST_RESETN_DFI_SCRAMBLE		0x00160009
+
+// ======================= TOPCRU module definition bank=7 ========================
+// TOPCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_PRESETN_CRU			0x00180000
+#define SRST_PRESETN_CRU_BIU			0x00180001
+#define SRST_RESETN_DDRPHY			0x0018000C
+
+//======================= PMUCRU module definition bank=8 ========================
+// PMUCRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_PRESETN_PMU_GPIO0			0x001c0004
+#define SRST_DBRESETN_PMU_GPIO0			0x001c0005
+#define SRST_RESETN_DDR_FAIL_SAFE		0x001c0008
+#define SRST_PRESETN_PMU_HP_TIMER		0x001c0009
+#define SRST_RESETN_PMU_HP_TIMER		0x001c000A
+#define SRST_RESETN_PMU_32K_HP_TIMER		0x001c000B
+#define SRST_PRESETN_I2C0			0x001c000C
+#define SRST_RESETN_I2C0			0x001c000D
+#define SRST_PRESETN_UART0			0x001c000E
+#define SRST_SRESETN_UART0			0x001c000F
+
+// PMUCRU_SOFTRST_CON01(Offset:0xA04)
+#define SRST_PRESETN_IOC_PMUIO0			0x001c0010
+#define SRST_PRESETN_CRU_PMU			0x001c0011
+#define SRST_PRESETN_PMU_GRF			0x001c0012
+#define SRST_PRESETN_PMU_SGRF			0x001c0013
+#define SRST_PRESETN_PMU_SGRF_REMAP		0x001c0014
+#define SRST_RESETN_PREROLL			0x001c0016
+#define SRST_RESETN_PREROLL_32K			0x001c0017
+#define SRST_HRESETN_PMU_SRAM			0x001c0018
+#define SRST_PRESETN_PWM0			0x001c0019
+#define SRST_RESETN_PWM0			0x001c001A
+
+// PMUCRU_SOFTRST_CON02(Offset:0xA08)
+#define SRST_RESETN_LPMCU			0x001c0020
+#define SRST_RESETN_LPMCU_PWRUP			0x001c0021
+#define SRST_RESETN_LPMCU_CPU			0x001c0022
+#define SRST_TRESETN_LPMCU_CPU			0x001c0023
+
+// ======================= PMU1CRU module definition bank=9 =======================
+// PMU1CRU_SOFTRST_CON00(Offset:0xA00)
+#define SRST_PRESETN_SPI2AHB			0x00200000
+#define SRST_HRESETN_SPI2AHB			0x00200001
+#define SRST_SRESETN_SPI2AHB			0x00200002
+#define SRST_LSRESETN_PMU_BIU			0x00200003
+#define SRST_PRESETN_WDT_LPMCU			0x00200009
+#define SRST_TRESETN_WDT_LPMCU			0x0020000A
+#define SRST_HRESETN_SFC_PMU1			0x0020000C
+#define SRST_HRESETN_SFC_XIP_PMU1		0x0020000D
+#define SRST_SRESETN_SFC_2X_PMU1		0x0020000E
+
+// PMU1CRU_SOFTRST_CON01(Offset:0xA04)
+#define SRST_PRESETN_LPMCU_MAILBOX		0x00200018
+#define SRST_PRESETN_IOC_PMUIO1			0x00200019
+#define SRST_PRESETN_CRU_PMU1			0x0020001A
+
+#define CLK_NR_SRST				(SRST_PRESETN_CRU_PMU1 + 1)
+
+#endif
-- 
2.34.1

[PATCH 03/11] clk: rockchip: Add clock controller for the RV1103B

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

Add the clock and reset tree definitions for the RV1103B SoC.

Based on the 5.10 Rockchip vendor kernel driver.

Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 drivers/clk/rockchip/Kconfig       |   7 +
 drivers/clk/rockchip/Makefile      |   1 +
 drivers/clk/rockchip/clk-rv1103b.c | 670 +++++++++++++++++++++++++++++
 drivers/clk/rockchip/clk.h         |  49 +++
 4 files changed, 727 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk-rv1103b.c

diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 5cf1e0fd6fb3..3fc91f3c2453 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -23,6 +23,13 @@ config CLK_RV110X
 	help
 	  Build the driver for RV110x Clock Driver.
 
+config CLK_RV1103B
+	tristate "Rockchip RV1103B clock controller support"
+	depends on ARM || COMPILE_TEST
+	default y
+	help
+	  Build the driver for RV1103B Clock Driver.
+
 config CLK_RV1126
 	bool "Rockchip RV1126 clock controller support"
 	depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 4d8cbb2044c7..7c984ee006c6 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -18,6 +18,7 @@ clk-rockchip-y += gate-link.o
 clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
 obj-$(CONFIG_CLK_PX30)          += clk-px30.o
+obj-$(CONFIG_CLK_RV1103B)	+= clk-rv1103b.o
 obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
 obj-$(CONFIG_CLK_RV1126)        += clk-rv1126.o
 obj-$(CONFIG_CLK_RV1126B)	+= clk-rv1126b.o rst-rv1126b.o
diff --git a/drivers/clk/rockchip/clk-rv1103b.c b/drivers/clk/rockchip/clk-rv1103b.c
new file mode 100644
index 000000000000..40e04a7e2b1c
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rv1103b.c
@@ -0,0 +1,670 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
+#include "clk.h"
+
+#define RV1103B_GRF_SOC_STATUS0		0x10
+#define RV1103B_FRAC_MAX_PRATE		1200000000
+#define PVTPLL_SRC_SEL_PVTPLL		(BIT(0) | BIT(16))
+
+enum rv1103b_plls {
+	dpll,
+	gpll,
+};
+
+static struct rockchip_pll_rate_table rv1103b_pll_rates[] = {
+	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+	RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+	{ /* sentinel */ },
+};
+
+#define RV1103B_DIV_ACLK_CORE_MASK	0x1f
+#define RV1103B_DIV_ACLK_CORE_SHIFT	0
+#define RV1103B_DIV_PCLK_DBG_MASK	0x1f
+#define RV1103B_DIV_PCLK_DBG_SHIFT	8
+#define RV1103B_CORE_SEL_MASK		0x1
+#define RV1103B_CORE_SEL_SHIFT		1
+#define RV1103B_ALT_DIV_MASK		0x7
+#define RV1103B_ALT_DIV_SHIFT		13
+
+#define RV1103B_CLKSEL0(_aclk_core)						\
+{										\
+	.reg = RV1103B_CORECLKSEL_CON(2),					\
+	.val = HIWORD_UPDATE(_aclk_core - 1, RV1103B_DIV_ACLK_CORE_MASK,	\
+			     RV1103B_DIV_ACLK_CORE_SHIFT),			\
+}
+
+#define RV1103B_CLKSEL1(_pclk_dbg)						\
+{										\
+	.reg = RV1103B_CORECLKSEL_CON(2),					\
+	.val = HIWORD_UPDATE(_pclk_dbg - 1, RV1103B_DIV_PCLK_DBG_MASK,		\
+			     RV1103B_DIV_PCLK_DBG_SHIFT),			\
+}
+
+#define RV1103B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)			\
+{										\
+	.prate = _prate,							\
+	.divs = {								\
+		RV1103B_CLKSEL0(_aclk_core),					\
+		RV1103B_CLKSEL1(_pclk_dbg),					\
+	},									\
+}
+
+static struct rockchip_cpuclk_rate_table rv1103b_cpuclk_rates[] __initdata = {
+	RV1103B_CPUCLK_RATE(1608000000, 4, 10),
+	RV1103B_CPUCLK_RATE(1512000000, 4, 10),
+	RV1103B_CPUCLK_RATE(1416000000, 4, 10),
+	RV1103B_CPUCLK_RATE(1296000000, 3, 10),
+	RV1103B_CPUCLK_RATE(1200000000, 3, 10),
+	RV1103B_CPUCLK_RATE(1188000000, 3, 8),
+	RV1103B_CPUCLK_RATE(1104000000, 2, 8),
+	RV1103B_CPUCLK_RATE(1008000000, 2, 8),
+	RV1103B_CPUCLK_RATE(816000000, 2, 6),
+	RV1103B_CPUCLK_RATE(600000000, 2, 4),
+	RV1103B_CPUCLK_RATE(594000000, 2, 4),
+	RV1103B_CPUCLK_RATE(408000000, 1, 3),
+	RV1103B_CPUCLK_RATE(396000000, 1, 3),
+};
+
+PNAME(mux_pll_p)			= { "xin24m" };
+PNAME(mux_200m_100m_p)			= { "clk_gpll_div6", "clk_gpll_div12" };
+PNAME(mux_gpll_24m_p)			= { "gpll", "xin24m" };
+PNAME(mux_480m_400m_300m_200m_p)	= { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" };
+PNAME(mux_480m_400m_300m_p)		= { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4" };
+PNAME(mux_300m_200m_p)			= { "clk_gpll_div4", "clk_gpll_div6" };
+PNAME(mux_600m_480m_400m_p)		= { "clk_gpll_div2", "clk_gpll_div2p5", "clk_gpll_div3" };
+PNAME(mux_400m_300m_p)			= { "clk_gpll_div3", "clk_gpll_div4" };
+PNAME(mux_100m_24m_p)			= { "clk_gpll_div12", "xin24m" };
+PNAME(mux_200m_24m_p)			= { "clk_gpll_div6", "xin24m" };
+PNAME(mux_200m_100m_50m_24m_p)		= { "clk_gpll_div6", "clk_gpll_div12", "clk_gpll_div24", "xin24m" };
+PNAME(mux_300m_200m_100m_p)		= { "clk_gpll_div4", "clk_gpll_div6", "clk_gpll_div12" };
+PNAME(sclk_uart0_src_p)			= { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
+PNAME(sclk_uart1_src_p)			= { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
+PNAME(sclk_uart2_src_p)			= { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
+PNAME(mclk_sai_src_p)			= { "clk_sai_src", "clk_sai_frac", "mclk_sai_from_io", "xin_osc0_half" };
+PNAME(clk_freq_pwm0_src_p)		= { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
+PNAME(clk_counter_pwm0_src_p)		= { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
+PNAME(clk_mipi0_out2io_p)		= { "clk_ref_mipi0", "xin24m" };
+PNAME(clk_mipi1_out2io_p)		= { "clk_ref_mipi1", "xin24m" };
+PNAME(mclk_sai_out2io_p)		= { "mclk_sai_src", "xin_osc0_half" };
+PNAME(aclk_npu_root_p)			= { "clk_npu_src", "clk_npu_pvtpll" };
+PNAME(clk_core_vepu_p)			= { "clk_vepu_src", "clk_vepu_pvtpll" };
+PNAME(lsclk_vi_root_p)			= { "clk_gpll_div6", "lsclk_vi_100m" };
+PNAME(clk_core_isp_p)			= { "clk_isp_src", "clk_isp_pvtpll_src" };
+PNAME(lsclk_pmu_root_p)			= { "xin24m", "clk_rc_osc_io" };
+PNAME(xin_rc_div_p)			= { "xin24m", "clk_rc_osc_io" };
+PNAME(clk_32k_p)			= { "xin_rc_div", "clk_32k_rtc", "clk_32k_io" };
+PNAME(dbclk_pmu_gpio0_p)		= { "xin24m", "clk_32k" };
+PNAME(sclk_sfc_2x_pmu1_p)		= { "clk_gpll_div12", "clk_rc_osc_io" };
+PNAME(mux_armclk_p)			= { "armclk_gpll", "clk_core_pvtpll" };
+
+static struct rockchip_pll_clock rv1103b_pll_clks[] __initdata = {
+	[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+		     CLK_IS_CRITICAL, RV1103B_PLL_CON(16),
+		     RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
+	[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+		     CLK_IS_CRITICAL, RV1103B_PLL_CON(24),
+		     RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rv1103b_clk_uart0_fracmux __initdata =
+	MUX(SCLK_UART0_SRC, "sclk_uart0_src", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
+			RV1103B_CLKSEL_CON(32), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1103b_clk_uart1_fracmux __initdata =
+	MUX(SCLK_UART1_SRC, "sclk_uart1_src", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
+			RV1103B_CLKSEL_CON(32), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1103b_clk_uart2_fracmux __initdata =
+	MUX(SCLK_UART2_SRC, "sclk_uart2_src", sclk_uart2_src_p, CLK_SET_RATE_PARENT,
+			RV1103B_CLKSEL_CON(32), 12, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1103b_rcdiv_pmu_fracmux __initdata =
+	MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+			RK3568_PMU_CLKSEL_CON(0), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1103b_clk_branches[] __initdata = {
+
+	/*       Clock Definition       */
+	FACTOR(XIN_OSC0_HALF, "xin_osc0_half", "xin24m", 0, 1, 2),
+
+	COMPOSITE_NOGATE(0, "armclk_gpll", mux_gpll_24m_p, CLK_IS_CRITICAL,
+			RV1103B_CLKSEL_CON(37), 12, 1, MFLAGS, 13, 3, DFLAGS),
+
+	/* pd_top */
+	COMPOSITE_NOMUX(CLK_GPLL_DIV24, "clk_gpll_div24", "gpll", 0,
+			RV1103B_CLKSEL_CON(0), 0, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NOMUX(CLK_GPLL_DIV12, "clk_gpll_div12", "gpll", 0,
+			RV1103B_CLKSEL_CON(0), 5, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NOMUX(CLK_GPLL_DIV6, "clk_gpll_div6", "gpll", 0,
+			RV1103B_CLKSEL_CON(1), 0, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(0), 3, GFLAGS),
+	COMPOSITE_NOMUX(CLK_GPLL_DIV4, "clk_gpll_div4", "gpll", 0,
+			RV1103B_CLKSEL_CON(1), 10, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(0), 5, GFLAGS),
+	COMPOSITE_NOMUX(CLK_GPLL_DIV3, "clk_gpll_div3", "gpll", 0,
+			RV1103B_CLKSEL_CON(2), 0, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(0), 7, GFLAGS),
+	COMPOSITE_NOMUX_HALFDIV(CLK_GPLL_DIV2P5, "clk_gpll_div2p5", "gpll", 0,
+			RV1103B_CLKSEL_CON(2), 5, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(0), 8, GFLAGS),
+	COMPOSITE_NOMUX(CLK_GPLL_DIV2, "clk_gpll_div2", "gpll", 0,
+			RV1103B_CLKSEL_CON(2), 10, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(0), 9, GFLAGS),
+	COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0,
+			RV1103B_CLKSEL_CON(5), 0, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(1), 0, GFLAGS),
+	COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0,
+			RV1103B_CLKSEL_CON(5), 5, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(1), 1, GFLAGS),
+	COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0,
+			RV1103B_CLKSEL_CON(5), 10, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(1), 2, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", 0,
+			RV1103B_CLKSEL_CON(10), 0,
+			RV1103B_CLKGATE_CON(1), 6, GFLAGS,
+			&rv1103b_clk_uart0_fracmux),
+	COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", 0,
+			RV1103B_CLKSEL_CON(11), 0,
+			RV1103B_CLKGATE_CON(1), 7, GFLAGS,
+			&rv1103b_clk_uart1_fracmux),
+	COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", 0,
+			RV1103B_CLKSEL_CON(12), 0,
+			RV1103B_CLKGATE_CON(1), 8, GFLAGS,
+			&rv1103b_clk_uart2_fracmux),
+	GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_src", 0,
+			RV1103B_CLKGATE_CON(3), 3, GFLAGS),
+	GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_src", 0,
+			RV1103B_CLKGATE_CON(3), 4, GFLAGS),
+	GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_src", 0,
+			RV1103B_CLKGATE_CON(3), 8, GFLAGS),
+
+	COMPOSITE_NOMUX(CLK_SAI_SRC, "clk_sai_src", "gpll", 0,
+			RV1103B_CLKSEL_CON(20), 0, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(1), 12, GFLAGS),
+	MUX(MCLK_SAI_SRC, "mclk_sai_src", mclk_sai_src_p, CLK_SET_RATE_PARENT,
+			RV1103B_CLKSEL_CON(35), 10, 2, MFLAGS),
+	GATE(MCLK_SAI, "mclk_sai", "mclk_sai_src", 0,
+			RV1103B_CLKGATE_CON(5), 5, GFLAGS),
+
+	COMPOSITE_NODIV(LSCLK_NPU_SRC, "lsclk_npu_src", mux_200m_100m_p, CLK_IS_CRITICAL,
+			RV1103B_CLKSEL_CON(30), 0, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(2), 0, GFLAGS),
+	COMPOSITE(CLK_NPU_SRC, "clk_npu_src", mux_gpll_24m_p, 0,
+			RV1103B_CLKSEL_CON(37), 0, 1, MFLAGS, 1, 2, DFLAGS,
+			RV1103B_CLKGATE_CON(5), 12, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VEPU_SRC, "aclk_vepu_src", mux_480m_400m_300m_200m_p, 0,
+			RV1103B_CLKSEL_CON(30), 8, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(2), 4, GFLAGS),
+	COMPOSITE(CLK_VEPU_SRC, "clk_vepu_src", mux_gpll_24m_p, 0,
+			RV1103B_CLKSEL_CON(37), 4, 1, MFLAGS, 5, 2, DFLAGS,
+			RV1103B_CLKGATE_CON(5), 13, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VI_SRC, "aclk_vi_src", mux_480m_400m_300m_p, CLK_IS_CRITICAL,
+			RV1103B_CLKSEL_CON(30), 12, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(2), 8, GFLAGS),
+	COMPOSITE(CLK_ISP_SRC, "clk_isp_src", mux_gpll_24m_p, 0,
+			RV1103B_CLKSEL_CON(37), 8, 1, MFLAGS, 9, 2, DFLAGS,
+			RV1103B_CLKGATE_CON(5), 14, GFLAGS),
+	COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_300m_200m_p, 0,
+			RV1103B_CLKSEL_CON(30), 14, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(2), 9, GFLAGS),
+	COMPOSITE(CCLK_EMMC, "cclk_emmc", mux_gpll_24m_p, 0,
+			RV1103B_CLKSEL_CON(31), 15, 1, MFLAGS, 0, 8, DFLAGS,
+			RV1103B_CLKGATE_CON(2), 10, GFLAGS),
+	COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", mux_gpll_24m_p, 0,
+			RV1103B_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 8, DFLAGS,
+			RV1103B_CLKGATE_CON(2), 11, GFLAGS),
+	COMPOSITE(SCLK_SFC_2X, "sclk_sfc_2x", mux_gpll_24m_p, 0,
+			RV1103B_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 8, DFLAGS,
+			RV1103B_CLKGATE_CON(2), 12, GFLAGS),
+	COMPOSITE_NODIV(LSCLK_PERI_SRC, "lsclk_peri_src", mux_300m_200m_p, CLK_IS_CRITICAL,
+			RV1103B_CLKSEL_CON(31), 9, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(3), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_600m_480m_400m_p, CLK_IS_CRITICAL,
+			RV1103B_CLKSEL_CON(31), 10, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(3), 1, GFLAGS),
+	COMPOSITE_NODIV(HCLK_HPMCU, "hclk_hpmcu", mux_400m_300m_p, 0,
+			RV1103B_CLKSEL_CON(31), 12, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(3), 2, GFLAGS),
+		COMPOSITE_NODIV(CLK_I2C_PMU, "clk_i2c_pmu", mux_100m_24m_p, 0,
+			RV1103B_CLKSEL_CON(34), 0, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(4), 0, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C_PERI, "clk_i2c_peri", mux_200m_24m_p, 0,
+			RV1103B_CLKSEL_CON(34), 1, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(4), 4, GFLAGS),
+	COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
+			RV1103B_CLKSEL_CON(34), 2, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(4), 5, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM0_SRC, "clk_pwm0_src", mux_100m_24m_p, 0,
+			RV1103B_CLKSEL_CON(34), 12, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(4), 10, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_24m_p, 0,
+			RV1103B_CLKSEL_CON(34), 13, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(4), 11, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_24m_p, 0,
+			RV1103B_CLKSEL_CON(34), 14, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(4), 12, GFLAGS),
+	COMPOSITE_NODIV(DCLK_DECOM_SRC, "dclk_decom_src", mux_480m_400m_300m_p, 0,
+			RV1103B_CLKSEL_CON(35), 0, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(5), 0, GFLAGS),
+	COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", mux_gpll_24m_p, 0,
+			RV1103B_CLKSEL_CON(36), 15, 1, MFLAGS, 0, 8, DFLAGS,
+			RV1103B_CLKGATE_CON(5), 1, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_p, 0,
+			RV1103B_CLKSEL_CON(35), 2, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(5), 2, GFLAGS),
+	COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_p, 0,
+			RV1103B_CLKSEL_CON(35), 4, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(5), 3, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_RGA, "clk_core_rga", mux_400m_300m_p, 0,
+			RV1103B_CLKSEL_CON(35), 8, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(5), 4, GFLAGS),
+
+	GATE(PCLK_TOP_ROOT, "pclk_top_root", "clk_gpll_div12", CLK_IS_CRITICAL,
+			RV1103B_CLKGATE_CON(6), 0, GFLAGS),
+	COMPOSITE_NOMUX(CLK_REF_MIPI0, "clk_ref_mipi0", "clk_gpll_div2", 0,
+			RV1103B_CLKSEL_CON(40), 0, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(6), 3, GFLAGS),
+	COMPOSITE_NODIV(CLK_MIPI0_OUT2IO, "clk_mipi0_out2io", clk_mipi0_out2io_p, CLK_SET_RATE_PARENT,
+			RV1103B_CLKSEL_CON(40), 6, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(6), 4, GFLAGS),
+	COMPOSITE_NOMUX(CLK_REF_MIPI1, "clk_ref_mipi1", "clk_gpll_div2", 0,
+			RV1103B_CLKSEL_CON(40), 8, 5, DFLAGS,
+			RV1103B_CLKGATE_CON(6), 5, GFLAGS),
+	COMPOSITE_NODIV(CLK_MIPI1_OUT2IO, "clk_mipi1_out2io", clk_mipi1_out2io_p, CLK_SET_RATE_PARENT,
+			RV1103B_CLKSEL_CON(40), 14, 1, MFLAGS,
+			RV1103B_CLKGATE_CON(6), 6, GFLAGS),
+	COMPOSITE(MCLK_SAI_OUT2IO, "mclk_sai_out2io", mclk_sai_out2io_p, 0,
+			RV1103B_CLKSEL_CON(41), 7, 1, MFLAGS, 13, 3, DFLAGS,
+			RV1103B_CLKGATE_CON(6), 9, GFLAGS),
+
+	/* pd_vpu */
+	COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", aclk_npu_root_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+			RV1103B_NPUCLKSEL_CON(0), 1, 1, MFLAGS,
+			RV1103B_NPUCLKGATE_CON(0), 1, GFLAGS),
+	GATE(HCLK_RKNN, "hclk_rknn", "lsclk_npu_src", 0,
+			RV1103B_NPUCLKGATE_CON(0), 4, GFLAGS),
+	GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
+			RV1103B_NPUCLKGATE_CON(0), 5, GFLAGS),
+
+	/* pd_vepu */
+	COMPOSITE_NOMUX(LSCLK_VEPU_ROOT, "lsclk_vepu_root", "aclk_vepu_src", CLK_IS_CRITICAL,
+			RV1103B_VEPUCLKSEL_CON(0), 2, 2, DFLAGS,
+			RV1103B_VEPUCLKGATE_CON(0), 0, GFLAGS),
+	GATE(HCLK_VEPU, "hclk_vepu", "lsclk_vepu_root", 0,
+			RV1103B_VEPUCLKGATE_CON(0), 4, GFLAGS),
+	GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_src", 0,
+			RV1103B_VEPUCLKGATE_CON(0), 5, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", clk_core_vepu_p, 0,
+			RV1103B_VEPUCLKSEL_CON(0), 1, 1, MFLAGS,
+			RV1103B_VEPUCLKGATE_CON(0), 6, GFLAGS),
+	GATE(PCLK_ACODEC, "pclk_acodec", "lsclk_vepu_root", 0,
+			RV1103B_VEPUCLKGATE_CON(0), 13, GFLAGS),
+	GATE(PCLK_USBPHY, "pclk_usbphy", "lsclk_vepu_root", 0,
+			RV1103B_VEPUCLKGATE_CON(0), 14, GFLAGS),
+
+	/* pd_vi */
+	FACTOR(LSCLK_VI_100M, "lsclk_vi_100m", "clk_gpll_div6", 0, 1, 2),
+	COMPOSITE_NODIV(LSCLK_VI_ROOT, "lsclk_vi_root", lsclk_vi_root_p, CLK_IS_CRITICAL,
+			RV1103B_VICLKSEL_CON(0), 3, 1, MFLAGS,
+			RV1103B_VICLKGATE_CON(0), 0, GFLAGS),
+	GATE(HCLK_ISP, "hclk_isp", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(0), 4, GFLAGS),
+	GATE(ACLK_ISP, "aclk_isp", "aclk_vi_src", 0,
+			RV1103B_VICLKGATE_CON(0), 5, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_ISP, "clk_core_isp", clk_core_isp_p, 0,
+			RV1103B_VICLKSEL_CON(0), 1, 1, MFLAGS,
+			RV1103B_VICLKGATE_CON(0), 6, GFLAGS),
+	GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_src", 0,
+			RV1103B_VICLKGATE_CON(1), 2, GFLAGS),
+	GATE(HCLK_VICAP, "hclk_vicap", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(1), 3, GFLAGS),
+	GATE(ISP0CLK_VICAP, "isp0clk_vicap", "clk_core_isp", 0,
+			RV1103B_VICLKGATE_CON(1), 8, GFLAGS),
+	GATE(PCLK_CSI2HOST0, "pclk_csi2host0", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(1), 9, GFLAGS),
+	GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(1), 11, GFLAGS),
+	GATE(HCLK_EMMC, "hclk_emmc", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(1), 13, GFLAGS),
+	GATE(HCLK_SFC, "hclk_sfc", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(1), 14, GFLAGS),
+	GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(1), 15, GFLAGS),
+	GATE(HCLK_SDMMC0, "hclk_sdmmc0", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(2), 0, GFLAGS),
+	GATE(PCLK_CSIPHY, "pclk_csiphy", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(2), 2, GFLAGS),
+	GATE(PCLK_GPIO1, "pclk_gpio1", "lsclk_vi_root", 0,
+			RV1103B_VICLKGATE_CON(2), 3, GFLAGS),
+	GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
+			RV1103B_VICLKGATE_CON(2), 4, GFLAGS),
+
+	/* pd_ddr */
+	GATE(LSCLK_DDR_ROOT, "lsclk_ddr_root", "clk_gpll_div12", CLK_IS_CRITICAL,
+			RV1103B_DDRCLKGATE_CON(0), 0, GFLAGS),
+	GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
+			RV1103B_DDRCLKGATE_CON(0), 4, GFLAGS),
+	FACTOR(0, "sclk_ddr", "dpll", 0, 1, 2),
+
+	/* pd_pmu */
+	COMPOSITE(LSCLK_PMU_ROOT, "lsclk_pmu_root", lsclk_pmu_root_p, CLK_IS_CRITICAL,
+			RV1103B_PMUCLKSEL_CON(2), 4, 1, MFLAGS, 0, 2, DFLAGS,
+			RV1103B_PMUCLKGATE_CON(0), 0, GFLAGS),
+	GATE(PCLK_PMU, "pclk_pmu", "lsclk_pmu_root", CLK_IS_CRITICAL,
+			RV1103B_PMUCLKGATE_CON(0), 2, GFLAGS),
+	MUX(XIN_RC_SRC, "xin_rc_src", xin_rc_div_p, 0,
+			RV1103B_PMUCLKSEL_CON(0), 2, 1, MFLAGS),
+	COMPOSITE_FRACMUX(XIN_RC_DIV, "xin_rc_div", "xin_rc_src", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			RV1103B_PMUCLKSEL_CON(1), 0,
+			RV1103B_PMUCLKGATE_CON(0), 3, GFLAGS,
+			&rv1103b_rcdiv_pmu_fracmux),
+	GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "lsclk_pmu_root", 0,
+			RV1103B_PMUCLKGATE_CON(0), 4, GFLAGS),
+	COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", dbclk_pmu_gpio0_p, 0,
+			RK3568_PMU_CLKSEL_CON(0), 3, 1, MFLAGS,
+			RV1103B_PMUCLKGATE_CON(0), 5, GFLAGS),
+	GATE(PCLK_PWM0, "pclk_pwm0", "lsclk_pmu_root", 0,
+			RV1103B_PMUCLKGATE_CON(2), 0, GFLAGS),
+	GATE(CLK_PWM0, "clk_pwm0", "clk_pwm0_src", 0,
+			RV1103B_PMUCLKGATE_CON(2), 1, GFLAGS),
+	GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
+			RV1103B_PMUCLKGATE_CON(2), 2, GFLAGS),
+	GATE(CLK_RC_PWM0, "clk_rc_pwm0", "clk_32k", 0,
+			RV1103B_PMUCLKGATE_CON(2), 3, GFLAGS),
+	GATE(PCLK_I2C0, "pclk_i2c0", "lsclk_pmu_root", 0,
+			RV1103B_PMUCLKGATE_CON(0), 12, GFLAGS),
+	GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_pmu", 0,
+			RV1103B_PMUCLKGATE_CON(0), 13, GFLAGS),
+	GATE(PCLK_UART0, "pclk_uart0", "lsclk_pmu_root", 0,
+			RV1103B_PMUCLKGATE_CON(0), 14, GFLAGS),
+	GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
+			RV1103B_PMUCLKGATE_CON(1), 4, GFLAGS),
+	GATE(CLK_PREROLL, "clk_preroll", "lsclk_pmu_root", 0,
+			RV1103B_PMUCLKGATE_CON(1), 6, GFLAGS),
+	GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0,
+			RV1103B_PMUCLKGATE_CON(1), 7, GFLAGS),
+	GATE(CLK_LPMCU_PMU, "clk_lpmcu_pmu", "lsclk_pmu_root", 0,
+			RV1103B_PMUCLKGATE_CON(2), 12, GFLAGS),
+
+	/* pd_pmu1 */
+	GATE(PCLK_SPI2AHB, "pclk_spi2ahb", "lsclk_pmu_root", 0,
+			RV1103B_PMU1CLKGATE_CON(0), 0, GFLAGS),
+	GATE(HCLK_SPI2AHB, "hclk_spi2ahb", "lsclk_pmu_root", 0,
+			RV1103B_PMU1CLKGATE_CON(0), 1, GFLAGS),
+	GATE(PCLK_WDT_LPMCU, "pclk_wdt_lpmcu", "lsclk_pmu_root", 0,
+			RV1103B_PMU1CLKGATE_CON(0), 9, GFLAGS),
+	GATE(TCLK_WDT_LPMCU, "tclk_wdt_lpmcu", "xin24m", 0,
+			RV1103B_PMU1CLKGATE_CON(0), 10, GFLAGS),
+	GATE(HCLK_SFC_PMU1, "hclk_sfc_pmu1", "lsclk_pmu_root", 0,
+			RV1103B_PMU1CLKGATE_CON(0), 12, GFLAGS),
+	GATE(HCLK_SFC_XIP_PMU1, "hclk_sfc_xip_pmu1", "lsclk_pmu_root", 0,
+			RV1103B_PMU1CLKGATE_CON(0), 13, GFLAGS),
+	COMPOSITE_NODIV(SCLK_SFC_2X_PMU1, "sclk_sfc_2x_pmu1", sclk_sfc_2x_pmu1_p, 0,
+			RV1103B_PMU1CLKSEL_CON(0), 8, 1, MFLAGS,
+			RV1103B_PMU1CLKGATE_CON(0), 14, GFLAGS),
+	GATE(CLK_LPMCU, "clk_lpmcu", "lsclk_pmu_root", 0,
+			RV1103B_PMU1CLKGATE_CON(1), 0, GFLAGS),
+	GATE(CLK_LPMCU_RTC, "clk_lpmcu_rtc", "xin24m", 0,
+			RV1103B_PMU1CLKGATE_CON(1), 4, GFLAGS),
+	GATE(PCLK_LPMCU_MAILBOX, "pclk_lpmcu_mailbox", "lsclk_pmu_root", 0,
+			RV1103B_PMU1CLKGATE_CON(1), 8, GFLAGS),
+
+	/* pd_peri */
+	COMPOSITE_NOMUX(PCLK_PERI_ROOT, "pclk_peri_root", "lsclk_peri_src", CLK_IS_CRITICAL,
+			RV1103B_PERICLKSEL_CON(0), 0, 2, DFLAGS,
+			RV1103B_PERICLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NOMUX(PCLK_RTC_ROOT, "pclk_rtc_root", "lsclk_peri_src", CLK_IS_CRITICAL,
+			RV1103B_PERICLKSEL_CON(2), 12, 4, DFLAGS,
+			RV1103B_PERICLKGATE_CON(0), 8, GFLAGS),
+	GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(0), 1, GFLAGS),
+	GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 0, GFLAGS),
+	GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 1, GFLAGS),
+	GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 2, GFLAGS),
+	GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 3, GFLAGS),
+	GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 4, GFLAGS),
+	GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 5, GFLAGS),
+	GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 6, GFLAGS),
+	GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 7, GFLAGS),
+	GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 8, GFLAGS),
+	GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
+			RV1103B_PERICLKGATE_CON(1), 9, GFLAGS),
+	GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(2), 0, GFLAGS),
+	GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(2), 1, GFLAGS),
+	GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(2), 2, GFLAGS),
+	GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(2), 3, GFLAGS),
+	GATE(PCLK_WDT_HPMCU, "pclk_wdt_hpmcu", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(2), 4, GFLAGS),
+	GATE(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(2), 5, GFLAGS),
+	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(2), 6, GFLAGS),
+	GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_peri", 0,
+			RV1103B_PERICLKGATE_CON(2), 7, GFLAGS),
+	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(2), 8, GFLAGS),
+	GATE(CLK_I2C2, "clk_i2c2", "clk_i2c_peri", 0,
+			RV1103B_PERICLKGATE_CON(2), 9, GFLAGS),
+	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(2), 10, GFLAGS),
+	GATE(CLK_I2C3, "clk_i2c3", "clk_i2c_peri", 0,
+			RV1103B_PERICLKGATE_CON(2), 11, GFLAGS),
+	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(2), 12, GFLAGS),
+	GATE(CLK_I2C4, "clk_i2c4", "clk_i2c_peri", 0,
+			RV1103B_PERICLKGATE_CON(2), 13, GFLAGS),
+	GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(3), 10, GFLAGS),
+	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(4), 6, GFLAGS),
+	GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(4), 8, GFLAGS),
+	GATE(PCLK_PWM2, "pclk_pwm2", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(4), 12, GFLAGS),
+	GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(4), 13, GFLAGS),
+	GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(3), 0, GFLAGS),
+	GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(3), 2, GFLAGS),
+	GATE(ACLK_RKDMA, "aclk_rkdma", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(5), 8, GFLAGS),
+	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(5), 9, GFLAGS),
+	COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
+			RV1103B_PERICLKSEL_CON(0), 4, 5, DFLAGS,
+			RV1103B_PERICLKGATE_CON(5), 10, GFLAGS),
+	COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
+			RV1103B_PERICLKSEL_CON(0), 10, 5, DFLAGS,
+			RV1103B_PERICLKGATE_CON(5), 11, GFLAGS),
+	GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(5), 12, GFLAGS),
+	COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+			RV1103B_PERICLKSEL_CON(1), 0, 3, DFLAGS,
+			RV1103B_PERICLKGATE_CON(5), 13, GFLAGS),
+	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(6), 3, GFLAGS),
+	GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(6), 4, GFLAGS),
+	GATE(ACLK_USBOTG, "aclk_usbotg", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(6), 9, GFLAGS),
+	GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(6), 10, GFLAGS),
+	GATE(HCLK_SDMMC1, "hclk_sdmmc1", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(7), 0, GFLAGS),
+	GATE(HCLK_SAI, "hclk_sai", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(7), 1, GFLAGS),
+	GATE(ACLK_CRYPTO, "aclk_crypto", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(8), 2, GFLAGS),
+	GATE(HCLK_CRYPTO, "hclk_crypto", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(8), 3, GFLAGS),
+	GATE(HCLK_RK_RNG_S, "hclk_rk_rng_s", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(8), 5, GFLAGS),
+	GATE(HCLK_RK_RNG_NS, "hclk_rk_rng_ns", "hclk_rk_rng_s", 0,
+			RV1103B_PERICLKGATE_CON(8), 4, GFLAGS),
+	GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(8), 6, GFLAGS),
+	GATE(CLK_OTPC_ROOT_NS, "clk_otpc_root_ns", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(8), 7, GFLAGS),
+	GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "clk_otpc_root_ns", 0,
+			RV1103B_PERICLKGATE_CON(8), 8, GFLAGS),
+	COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_otpc_root_ns", 0,
+			RV1103B_PERICLKSEL_CON(1), 4, 3, DFLAGS,
+			RV1103B_PERICLKGATE_CON(8), 9, GFLAGS),
+	GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(8), 10, GFLAGS),
+	GATE(CLK_OTPC_ROOT_S, "clk_otpc_root_s", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(8), 11, GFLAGS),
+	GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "clk_otpc_root_s", 0,
+			RV1103B_PERICLKGATE_CON(8), 12, GFLAGS),
+	COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "clk_otpc_root_s", 0,
+			RV1103B_PERICLKSEL_CON(1), 8, 3, DFLAGS,
+			RV1103B_PERICLKGATE_CON(8), 13, GFLAGS),
+	GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(8), 15, GFLAGS),
+	GATE(HCLK_RGA, "hclk_rga", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(9), 0, GFLAGS),
+	GATE(ACLK_RGA, "aclk_rga", "aclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(9), 1, GFLAGS),
+	GATE(ACLK_MAC, "aclk_mac", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(9), 3, GFLAGS),
+	GATE(PCLK_MAC, "pclk_mac", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(9), 4, GFLAGS),
+	GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(9), 11, GFLAGS),
+	GATE(ACLK_SPINLOCK, "aclk_spinlock", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(10), 0, GFLAGS),
+	GATE(HCLK_CACHE, "hclk_cache", "hclk_hpmcu", 0,
+			RV1103B_PERICLKGATE_CON(10), 1, GFLAGS),
+	GATE(PCLK_HPMCU_MAILBOX, "pclk_hpmcu_mailbox", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(10), 2, GFLAGS),
+	GATE(PCLK_HPMCU_INTMUX, "pclk_hpmcu_intmux", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(10), 3, GFLAGS),
+	GATE(CLK_HPMCU, "clk_hpmcu", "hclk_hpmcu", 0,
+			RV1103B_PERICLKGATE_CON(10), 4, GFLAGS),
+	GATE(CLK_HPMCU_RTC, "clk_hpmcu_rtc", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(10), 8, GFLAGS),
+	GATE(DCLK_DECOM, "dclk_decom", "dclk_decom_src", 0,
+			RV1103B_PERICLKGATE_CON(11), 0, GFLAGS),
+	GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(11), 1, GFLAGS),
+	GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(11), 2, GFLAGS),
+	GATE(ACLK_SYS_SRAM, "aclk_sys_sram", "lsclk_peri_src", CLK_IS_CRITICAL,
+			RV1103B_PERICLKGATE_CON(11), 3, GFLAGS),
+	GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(11), 4, GFLAGS),
+	GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(11), 5, GFLAGS),
+	GATE(PCLK_DCF, "pclk_dcf", "pclk_peri_root", 0,
+			RV1103B_PERICLKGATE_CON(11), 6, GFLAGS),
+	GATE(ACLK_DCF, "aclk_dcf", "lsclk_peri_src", 0,
+			RV1103B_PERICLKGATE_CON(11), 7, GFLAGS),
+	COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_sai_src", 0,
+			RV1103B_PERICLKSEL_CON(2), 0, 3, DFLAGS,
+			RV1103B_PERICLKGATE_CON(11), 9, GFLAGS),
+	GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
+			RV1103B_PERICLKGATE_CON(11), 12, GFLAGS),
+
+	/* io */
+	COMPOSITE_NODIV(CLK_FREQ_PWM0_SRC, "clk_freq_pwm0_src", clk_freq_pwm0_src_p, 0,
+			RV1103B_CLKSEL_CON(35), 12, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(5), 6, GFLAGS),
+	GATE(CLK_FREQ_PWM0, "clk_freq_pwm0", "clk_freq_pwm0_src", 0,
+			RV1103B_PMUCLKGATE_CON(2), 4, GFLAGS),
+	COMPOSITE_NODIV(CLK_COUNTER_PWM0_SRC, "clk_counter_pwm0_src", clk_counter_pwm0_src_p, 0,
+			RV1103B_CLKSEL_CON(35), 14, 2, MFLAGS,
+			RV1103B_CLKGATE_CON(5), 7, GFLAGS),
+	GATE(CLK_COUNTER_PWM0, "clk_counter_pwm0", "clk_counter_pwm0_src", 0,
+			RV1103B_PMUCLKGATE_CON(2), 5, GFLAGS),
+	GATE(SCLK_SPI2AHB, "sclk_spi2ahb", "sclk_spi2ahb_io", 0,
+			RV1103B_PMU1CLKGATE_CON(0), 2, GFLAGS),
+	GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
+			RV1103B_PERICRU_IP_CON, 14, GFLAGS),
+};
+
+static struct rockchip_clk_branch rv1103b_armclk __initdata =
+	MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+			RV1103B_CORECLKSEL_CON(0), 1, 1, MFLAGS);
+
+static void __init rv1103b_clk_init(struct device_node *np)
+{
+	struct rockchip_clk_provider *ctx;
+	unsigned long clk_nr;
+	void __iomem *reg_base;
+
+	clk_nr = rockchip_clk_find_max_clk_id(rv1103b_clk_branches,
+					      ARRAY_SIZE(rv1103b_clk_branches)) + 1;
+	reg_base = of_iomap(np, 0);
+	if (!reg_base) {
+		pr_err("%s: could not map cru region\n", __func__);
+		return;
+	}
+
+	ctx = rockchip_clk_init(np, reg_base, clk_nr);
+	if (IS_ERR(ctx)) {
+		pr_err("%s: rockchip clk init failed\n", __func__);
+		iounmap(reg_base);
+		return;
+	}
+
+	rockchip_clk_register_plls(ctx, rv1103b_pll_clks,
+				   ARRAY_SIZE(rv1103b_pll_clks),
+				   RV1103B_GRF_SOC_STATUS0);
+
+	rockchip_clk_register_branches(ctx, rv1103b_clk_branches,
+				       ARRAY_SIZE(rv1103b_clk_branches));
+
+	rockchip_clk_register_armclk_multi_pll(ctx, &rv1103b_armclk,
+					rv1103b_cpuclk_rates,
+					ARRAY_SIZE(rv1103b_cpuclk_rates));
+
+	rockchip_register_softrst(np, CLK_NR_SRST, reg_base + RV1103B_PERISOFTRST_CON(0),
+				  ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+	rockchip_register_restart_notifier(ctx, RV1103B_GLB_SRST_FST, NULL);
+
+	rockchip_clk_of_add_provider(np, ctx);
+
+	/* pvtpll src init */
+	writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_CORECLKSEL_CON(0));
+	writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_NPUCLKSEL_CON(0));
+	writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_VICLKSEL_CON(0));
+	writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_VEPUCLKSEL_CON(0));
+}
+
+CLK_OF_DECLARE(rv1103b_cru, "rockchip,rv1103b-cru", rv1103b_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index b2fff1d13a4a..cf0f5f11c34b 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -66,6 +66,55 @@ struct clk;
 #define PX30_PMU_CLKGATE_CON(x)		((x) * 0x4 + 0x80)
 #define PX30_PMU_MODE			0x0020
 
+#define RV1103B_TOPCRU_BASE		0x60000
+#define RV1103B_PERICRU_BASE		0x0
+#define RV1103B_VICRU_BASE		0x30000
+#define RV1103B_NPUCRU_BASE		0x20000
+#define RV1103B_CORECRU_BASE		0x40000
+#define RV1103B_VEPUCRU_BASE		0x10000
+#define RV1103B_DDRCRU_BASE		0x50000
+#define RV1103B_SUBDDRCRU_BASE		0x58000
+#define RV1103B_PMUCRU_BASE		0x70000
+#define RV1103B_PMU1CRU_BASE		0x80000
+
+#define RV1103B_PMUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_PMUCRU_BASE)
+#define RV1103B_PMUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_PMUCRU_BASE)
+#define RV1103B_PMUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_PMUCRU_BASE)
+#define RV1103B_PMU1CLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_PMU1CRU_BASE)
+#define RV1103B_PMU1CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_PMU1CRU_BASE)
+#define RV1103B_PMU1SOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_PMU1CRU_BASE)
+#define RV1103B_PLL_CON(x)		((x) * 0x4 + RV1103B_TOPCRU_BASE)
+#define RV1103B_MODE_CON		(0x280 + RV1103B_TOPCRU_BASE)
+#define RV1103B_CLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)
+#define RV1103B_CLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1103B_TOPCRU_BASE)
+#define RV1103B_SOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1103B_TOPCRU_BASE)
+#define RV1103B_GLB_SRST_FST		(0xc08 + RV1103B_TOPCRU_BASE)
+#define RV1103B_GLB_SRST_SND		(0xc0c + RV1103B_TOPCRU_BASE)
+#define RV1103B_CLK_SAI_FRAC_DIV_HIGH	(0xcc0 + RV1103B_TOPCRU_BASE)
+#define RV1103B_PERICLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_PERICRU_BASE)
+#define RV1103B_PERICLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_PERICRU_BASE)
+#define RV1103B_PERISOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_PERICRU_BASE)
+#define RV1103B_PERICRU_IP_CON		(0xc08 + RV1103B_PERICRU_BASE)
+#define RV1103B_VICLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1103B_VICRU_BASE)
+#define RV1103B_VICLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_VICRU_BASE)
+#define RV1103B_VISOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_VICRU_BASE)
+#define RV1103B_NPUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_NPUCRU_BASE)
+#define RV1103B_NPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_NPUCRU_BASE)
+#define RV1103B_NPUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_NPUCRU_BASE)
+#define RV1103B_CORECLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_CORECRU_BASE)
+#define RV1103B_CORECLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_CORECRU_BASE)
+#define RV1103B_CORESOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_CORECRU_BASE)
+#define RV1103B_VEPUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_VEPUCRU_BASE)
+#define RV1103B_VEPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_VEPUCRU_BASE)
+#define RV1103B_VEPUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_VEPUCRU_BASE)
+#define RV1103B_DDRCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_DDRCRU_BASE)
+#define RV1103B_DDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_DDRCRU_BASE)
+#define RV1103B_DDRSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_DDRCRU_BASE)
+#define RV1103B_SUBDDRCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_SUBDDRCRU_BASE)
+#define RV1103B_SUBDDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_SUBDDRCRU_BASE)
+#define RV1103B_SUBDDRSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_SUBDDRCRU_BASE)
+#define RV1103B_SUBDDRMODE_CON		(0x280 + RV1103B_SUBDDRCRU_BASE)
+
 #define RV1108_PLL_CON(x)		((x) * 0x4)
 #define RV1108_CLKSEL_CON(x)		((x) * 0x4 + 0x60)
 #define RV1108_CLKGATE_CON(x)		((x) * 0x4 + 0x120)
-- 
2.34.1

[PATCH 04/11] dt-bindings: pinctrl: Add RV1103B pinctrl support

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

Document the compatible string for the RV1103B SoC.

Cc: Linus Walleij <linusw@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
index 76e607281716..9b3cbeb54fed 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
@@ -50,6 +50,7 @@ properties:
       - rockchip,rk3568-pinctrl
       - rockchip,rk3576-pinctrl
       - rockchip,rk3588-pinctrl
+      - rockchip,rv1103b-pinctrl
       - rockchip,rv1108-pinctrl
       - rockchip,rv1126-pinctrl
 
-- 
2.34.1

[PATCH 05/11] pinctrl: rockchip: Add RV1103B pinctrl support

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

Add pinctrl support for the RV1103B.

Based on the 5.10 Rockchip vendor kernel driver.

Cc: Linus Walleij <linusw@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 drivers/pinctrl/pinctrl-rockchip.c | 313 ++++++++++++++++++++++++++++-
 drivers/pinctrl/pinctrl-rockchip.h |   1 +
 2 files changed, 313 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 816823403e97..527548354c0f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -467,6 +467,22 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
  * Hardware access
  */
 
+static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = {
+	{
+		.num = 1,
+		.pin = 6,
+		.reg = 0x10024,
+		.bit = 8,
+		.mask = 0xf
+	}, {
+		.num = 1,
+		.pin = 7,
+		.reg = 0x10024,
+		.bit = 12,
+		.mask = 0xf
+	},
+};
+
 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 	{
 		.num = 1,
@@ -1172,6 +1188,9 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 	else
 		regmap = info->regmap_base;
 
+	if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
+		return 0;
+
 	if (ctrl->type == RK3506) {
 		if (bank->bank_num == 1)
 			regmap = info->regmap_ioc1;
@@ -1298,6 +1317,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 	else
 		regmap = info->regmap_base;
 
+	if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
+		return 0;
+
 	if (ctrl->type == RK3506) {
 		if (bank->bank_num == 1)
 			regmap = info->regmap_ioc1;
@@ -1495,6 +1517,214 @@ static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
 	return 0;
 }
 
+#define RV1103B_DRV_BITS_PER_PIN		8
+#define RV1103B_DRV_PINS_PER_REG		2
+#define RV1103B_DRV_GPIO0_A_OFFSET		0x40100
+#define RV1103B_DRV_GPIO0_B_OFFSET		0x50110
+#define RV1103B_DRV_GPIO1_A01_OFFSET		0x140
+#define RV1103B_DRV_GPIO1_A67_OFFSET		0x1014C
+#define RV1103B_DRV_GPIO2_OFFSET		0x30180
+#define RV1103B_DRV_GPIO2_SARADC_OFFSET		0x3080C
+
+static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+				       int pin_num, struct regmap **regmap,
+				       int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl *info = bank->drvdata;
+	int ret = 0;
+
+	*regmap = info->regmap_base;
+	switch (bank->bank_num) {
+	case 0:
+		if (pin_num < 7)
+			*reg = RV1103B_DRV_GPIO0_A_OFFSET;
+		else if (pin_num > 7 && pin_num < 14)
+			*reg = RV1103B_DRV_GPIO0_B_OFFSET - 0x10;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 1:
+		if (pin_num < 6)
+			*reg = RV1103B_DRV_GPIO1_A01_OFFSET;
+		else if (pin_num >= 6 && pin_num < 23)
+			*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
+		else if (pin_num >= 24 && pin_num < 30)
+			*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 2:
+		if (pin_num < 12) {
+			*reg = RV1103B_DRV_GPIO2_OFFSET;
+		} else if (pin_num >= 16) {
+			ret = -EINVAL;
+		} else {
+			*reg = RV1103B_DRV_GPIO2_SARADC_OFFSET;
+			*bit = 10;
+
+			return 0;
+		}
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+
+		return ret;
+	}
+
+	*reg += ((pin_num / RV1103B_DRV_PINS_PER_REG) * 4);
+	*bit = pin_num % RV1103B_DRV_PINS_PER_REG;
+	*bit *= RV1103B_DRV_BITS_PER_PIN;
+
+	return 0;
+}
+
+#define RV1103B_PULL_BITS_PER_PIN		2
+#define RV1103B_PULL_PINS_PER_REG		8
+#define RV1103B_PULL_GPIO0_A_OFFSET		0x40200
+#define RV1103B_PULL_GPIO0_B_OFFSET		0x50204
+#define RV1103B_PULL_GPIO1_A01_OFFSET		0x210
+#define RV1103B_PULL_GPIO1_A67_OFFSET		0x10210
+#define RV1103B_PULL_GPIO2_OFFSET		0x30220
+#define RV1103B_PULL_GPIO2_SARADC_OFFSET	0x3080C
+
+static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+					int pin_num, struct regmap **regmap,
+					int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl *info = bank->drvdata;
+	int ret = 0;
+
+	*regmap = info->regmap_base;
+	switch (bank->bank_num) {
+	case 0:
+		if (pin_num < 7)
+			*reg = RV1103B_PULL_GPIO0_A_OFFSET;
+		else if (pin_num > 7 && pin_num < 14)
+			*reg = RV1103B_PULL_GPIO0_B_OFFSET - 0x4;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 1:
+		if (pin_num < 6)
+			*reg = RV1103B_PULL_GPIO1_A01_OFFSET;
+		else if (pin_num >= 6 && pin_num < 23)
+			*reg = RV1103B_PULL_GPIO1_A67_OFFSET;
+		else if (pin_num >= 24 && pin_num < 30)
+			*reg = RV1103B_PULL_GPIO1_A67_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 2:
+		if (pin_num < 12) {
+			*reg = RV1103B_PULL_GPIO2_OFFSET;
+		} else if (pin_num >= 16) {
+			ret = -EINVAL;
+		} else {
+			*reg = RV1103B_PULL_GPIO2_SARADC_OFFSET;
+			*bit = 13;
+
+			return 0;
+		}
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+
+		return ret;
+	}
+
+	*reg += ((pin_num / RV1103B_PULL_PINS_PER_REG) * 4);
+	*bit = pin_num % RV1103B_PULL_PINS_PER_REG;
+	*bit *= RV1103B_PULL_BITS_PER_PIN;
+
+	return 0;
+}
+
+#define RV1103B_SMT_BITS_PER_PIN		1
+#define RV1103B_SMT_PINS_PER_REG		8
+#define RV1103B_SMT_GPIO0_A_OFFSET		0x40400
+#define RV1103B_SMT_GPIO0_B_OFFSET		0x50404
+#define RV1103B_SMT_GPIO1_A01_OFFSET		0x410
+#define RV1103B_SMT_GPIO1_A67_OFFSET		0x10410
+#define RV1103B_SMT_GPIO2_OFFSET		0x30420
+#define RV1103B_SMT_GPIO2_SARADC_OFFSET		0x3080C
+
+static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+					   int pin_num,
+					   struct regmap **regmap,
+					   int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl *info = bank->drvdata;
+	int ret = 0;
+
+	*regmap = info->regmap_base;
+	switch (bank->bank_num) {
+	case 0:
+		if (pin_num < 7)
+			*reg = RV1103B_SMT_GPIO0_A_OFFSET;
+		else if (pin_num > 7 && pin_num < 14)
+			*reg = RV1103B_SMT_GPIO0_B_OFFSET - 0x4;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 1:
+		if (pin_num < 6)
+			*reg = RV1103B_SMT_GPIO1_A01_OFFSET;
+		else if (pin_num >= 6 && pin_num < 23)
+			*reg = RV1103B_SMT_GPIO1_A67_OFFSET;
+		else if (pin_num >= 24 && pin_num < 30)
+			*reg = RV1103B_SMT_GPIO1_A67_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 2:
+		if (pin_num < 12) {
+			*reg = RV1103B_SMT_GPIO2_OFFSET;
+		} else if (pin_num >= 16) {
+			ret = -EINVAL;
+		} else {
+			*reg = RV1103B_SMT_GPIO2_SARADC_OFFSET;
+			*bit = 8;
+
+			return 0;
+		}
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+
+		return ret;
+	}
+
+	*reg += ((pin_num / RV1103B_SMT_PINS_PER_REG) * 4);
+	*bit = pin_num % RV1103B_SMT_PINS_PER_REG;
+	*bit *= RV1103B_SMT_BITS_PER_PIN;
+
+	return 0;
+}
+
 #define RV1108_PULL_PMU_OFFSET		0x10
 #define RV1108_PULL_OFFSET		0x110
 #define RV1108_PULL_PINS_PER_REG	8
@@ -2982,6 +3212,9 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
 	u8 bit;
 	int drv_type = bank->drv[pin_num / 8].drv_type;
 
+	if (ctrl->type == RV1103B && pin_num >= 12)
+		drv_type = DRV_TYPE_IO_LEVEL_2_BIT;
+
 	ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 	if (ret)
 		return ret;
@@ -3043,6 +3276,11 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
 	if (ret)
 		return ret;
 
+	if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
+		data = data >> 10;
+		return data & 0x3;
+	}
+
 	data >>= bit;
 	data &= (1 << rmask_bits) - 1;
 
@@ -3071,7 +3309,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 		rmask_bits = RK3588_DRV_BITS_PER_PIN;
 		ret = strength;
 		goto config;
-	} else if (ctrl->type == RK3506 ||
+	} else if (ctrl->type == RV1103B ||
+		   ctrl->type == RK3506 ||
 		   ctrl->type == RK3528 ||
 		   ctrl->type == RK3562 ||
 		   ctrl->type == RK3568) {
@@ -3182,6 +3421,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 			ret = strength;
 		}
 	}
+
+	if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
+		rmask_bits = 2;
+		ret = strength;
+	}
+
 	/* enable the write to the equivalent lower bits */
 	data = ((1 << rmask_bits) - 1) << (bit + 16);
 	rmask = data | (data >> 16);
@@ -3236,6 +3481,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 				? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 				: PIN_CONFIG_BIAS_DISABLE;
 	case PX30:
+	case RV1103B:
 	case RV1108:
 	case RK3188:
 	case RK3288:
@@ -3251,6 +3497,9 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 		pull_type = bank->pull_type[pin_num / 8];
 		data >>= bit;
 		data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
+
+		if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
+			pull_type = 1;
 		/*
 		 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
 		 * where that pull up value becomes 3.
@@ -3297,6 +3546,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 		ret = regmap_write(regmap, reg, data);
 		break;
 	case PX30:
+	case RV1103B:
 	case RV1108:
 	case RV1126:
 	case RK3188:
@@ -3312,6 +3562,8 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 	case RK3576:
 	case RK3588:
 		pull_type = bank->pull_type[pin_num / 8];
+		if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
+			pull_type = 1;
 		ret = -EINVAL;
 		for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
 			i++) {
@@ -3417,6 +3669,11 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
 	if (ret)
 		return ret;
 
+	if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
+		data >>= 8;
+		return data & 0x3;
+	}
+
 	data >>= bit;
 	switch (ctrl->type) {
 	case RK3562:
@@ -3473,6 +3730,12 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
 		}
 	}
 
+	if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
+		data = 0x3 << (bit + 16);
+		rmask = data | (data >> 16);
+		data |= ((enable ? 0x3 : 0) << bit);
+	}
+
 	return regmap_update_bits(regmap, reg, rmask, data);
 }
 
@@ -3579,6 +3842,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 	case RK3066B:
 		return pull ? false : true;
 	case PX30:
+	case RV1103B:
 	case RV1108:
 	case RV1126:
 	case RK3188:
@@ -4318,6 +4582,51 @@ static struct rockchip_pin_ctrl px30_pin_ctrl = {
 		.schmitt_calc_reg	= px30_calc_schmitt_reg_and_bit,
 };
 
+static struct rockchip_pin_bank rv1103b_pin_banks[] = {
+	PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x40000, 0x50008, 0x50010, 0x50018,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT),
+	PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x20, 0x10028, 0x10030, 0x10038,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT),
+	PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x30040, 0x30048, 0x30050, 0x30058,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT,
+				    DRV_TYPE_IO_LEVEL_8_BIT),
+};
+
+static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = {
+	.pin_banks		= rv1103b_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rv1103b_pin_banks),
+	.label			= "RV1103B-GPIO",
+	.type			= RV1103B,
+	.iomux_recalced		= rv1103b_mux_recalced_data,
+	.niomux_recalced	= ARRAY_SIZE(rv1103b_mux_recalced_data),
+	.pull_calc_reg		= rv1103b_calc_pull_reg_and_bit,
+	.drv_calc_reg		= rv1103b_calc_drv_reg_and_bit,
+	.schmitt_calc_reg	= rv1103b_calc_schmitt_reg_and_bit,
+};
+
 static struct rockchip_pin_bank rv1108_pin_banks[] = {
 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
 					     IOMUX_SOURCE_PMU,
@@ -4954,6 +5263,8 @@ static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
 	{ .compatible = "rockchip,px30-pinctrl",
 		.data = &px30_pin_ctrl },
+	{ .compatible = "rockchip,rv1103b-pinctrl",
+		.data = &rv1103b_pin_ctrl },
 	{ .compatible = "rockchip,rv1108-pinctrl",
 		.data = &rv1108_pin_ctrl },
 	{ .compatible = "rockchip,rv1126-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index 4f4aff42a80a..bb0e803e3b8a 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -185,6 +185,7 @@
 
 enum rockchip_pinctrl_type {
 	PX30,
+	RV1103B,
 	RV1108,
 	RV1126,
 	RK2928,
-- 
2.34.1

[PATCH 06/11] dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for R1103B

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

The dw-mshc controller in the RV1103B is compatible to the one first found
in the RK3288 SoC, so add the RV1103B to the variant list.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-mmc@vger.kernel.org
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
index acb9fb9a92cd..a75209bd2710 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
@@ -43,6 +43,7 @@ properties:
               - rockchip,rk3562-dw-mshc
               - rockchip,rk3568-dw-mshc
               - rockchip,rk3588-dw-mshc
+              - rockchip,rv1103b-dw-mshc
               - rockchip,rv1108-dw-mshc
               - rockchip,rv1126-dw-mshc
           - const: rockchip,rk3288-dw-mshc
-- 
2.34.1

[PATCH 07/11] dt-bindings: serial: snps-dw-apb-uart: Add support for RV1103B

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

The UART used in the RV1103B SoC is still the same dw-apb-uart compatible
type as on the SoCs that came before, so add the RV1103B to the list
of variants.

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial@vger.kernel.org
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 6efe43089a74..685c1eceb782 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -71,6 +71,7 @@ properties:
               - rockchip,rk3568-uart
               - rockchip,rk3576-uart
               - rockchip,rk3588-uart
+              - rockchip,rv1103b-uart
               - rockchip,rv1108-uart
               - rockchip,rv1126-uart
               - sophgo,sg2044-uart
-- 
2.34.1

[PATCH 08/11] dt-bindings: soc: rockchip: Add RV1103B IOC and GRF entries

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

The "General Register Files" provide additional setting bits
outside the regular IP block register space and it is accessed via syscon.

Document the RV1103B IOC and GRF compatible strings.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 0b8e3294c83e..9ad7a60c659d 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -63,6 +63,7 @@ properties:
               - rockchip,rk3588-vo0-grf
               - rockchip,rk3588-vo1-grf
               - rockchip,rk3588-vop-grf
+              - rockchip,rv1103b-ioc
               - rockchip,rv1108-usbgrf
           - const: syscon
       - items:
@@ -98,6 +99,7 @@ properties:
               - rockchip,rk3576-pmu0-grf
               - rockchip,rk3576-usb2phy-grf
               - rockchip,rk3588-usb2phy-grf
+              - rockchip,rv1103b-grf
               - rockchip,rv1108-grf
               - rockchip,rv1108-pmugrf
               - rockchip,rv1126-grf
-- 
2.34.1

[PATCH 09/11] ARM: dts: rockchip: Add support for RV1103B

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

Add the initial RV1103B devicetree.

Based on the 5.10 Rockchip vendor kernel driver.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 .../boot/dts/rockchip/rv1103b-pinctrl.dtsi    | 831 ++++++++++++++++++
 arch/arm/boot/dts/rockchip/rv1103b.dtsi       | 266 ++++++
 2 files changed, 1097 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103b.dtsi

diff --git a/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi
new file mode 100644
index 000000000000..bc4d8fcdfaf7
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi
@@ -0,0 +1,831 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <arm64/rockchip/rockchip-pinconf.dtsi>
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+	cam_clk0 {
+		cam_clk0_pins: cam-clk0-pins {
+			rockchip,pins =
+				/* cam_clk0_out */
+				<1 RK_PB5 1 &pcfg_pull_none>;
+		};
+	};
+
+	cam_clk1 {
+		cam_clk1_pins: cam-clk1-pins {
+			rockchip,pins =
+				/* cam_clk1_out */
+				<1 RK_PB6 1 &pcfg_pull_none>;
+		};
+	};
+
+	cam_spi {
+		cam_spi_bus4_pins: cam-spi-bus4-pins {
+			rockchip,pins =
+				/* cam_spi_d0 */
+				<0 RK_PB5 4 &pcfg_pull_up_drv_level_2>,
+				/* cam_spi_d1 */
+				<0 RK_PB2 4 &pcfg_pull_up_drv_level_2>,
+				/* cam_spi_d2 */
+				<0 RK_PB1 4 &pcfg_pull_up_drv_level_2>,
+				/* cam_spi_d3 */
+				<0 RK_PB0 4 &pcfg_pull_up_drv_level_2>;
+		};
+		cam_spi_clk_pins: cam-spi-clk-pins {
+			rockchip,pins =
+				/* cam_spi_clk */
+				<0 RK_PB4 4 &pcfg_pull_none>;
+		};
+		cam_spi_cs0n_pins: cam-spi-cs0n-pins {
+			rockchip,pins =
+				/* cam_spi_cs0n */
+				<0 RK_PB3 4 &pcfg_pull_none>;
+		};
+	};
+
+	clk {
+		clk_32k_pins: clk-32k-pins {
+			rockchip,pins =
+				/* clk_32k */
+				<0 RK_PA0 2 &pcfg_pull_none>;
+		};
+	};
+
+	clk_24m {
+		clk_24m_out_pins: clk-24m-out-pins {
+			rockchip,pins =
+				/* clk_24m_out */
+				<0 RK_PA0 3 &pcfg_pull_none>;
+		};
+	};
+
+	cpu {
+		cpu_pins: cpu-pins {
+			rockchip,pins =
+				/* cpu_avs */
+				<0 RK_PA1 2 &pcfg_pull_none>;
+		};
+	};
+
+	emmc {
+		emmc_bus4_pins: emmc-bus4-pins {
+			rockchip,pins =
+				/* emmc_d0 */
+				<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d1 */
+				<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d2 */
+				<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d3 */
+				<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+		};
+		emmc_clk_pins: emmc-clk-pins {
+			rockchip,pins =
+				/* emmc_clk */
+				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+		};
+		emmc_cmd_pins: emmc-cmd-pins {
+			rockchip,pins =
+				/* emmc_cmd */
+				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+		};
+	};
+
+	emmc_testclk {
+		emmc_testclk_clk_pins: emmc-testclk-clk-pins {
+			rockchip,pins =
+				/* emmc_testclk_out */
+				<1 RK_PA7 3 &pcfg_pull_up_drv_level_2>;
+		};
+	};
+
+	emmc_testdata {
+		emmc_testdata_out_pins: emmc-testdata-out-pins {
+			rockchip,pins =
+				/* emmc_testdata_out */
+				<1 RK_PB0 3 &pcfg_pull_none>;
+		};
+	};
+
+	eth_led {
+		eth_led_dpx_pins: eth-led-dpx-pins {
+			rockchip,pins =
+				/* eth_led_dpx */
+				<2 RK_PA4 6 &pcfg_pull_none>;
+		};
+		eth_led_link_pins: eth-led-link-pins {
+			rockchip,pins =
+				/* eth_led_link */
+				<2 RK_PA6 6 &pcfg_pull_none>;
+		};
+		eth_led_spd_pins: eth-led-spd-pins {
+			rockchip,pins =
+				/* eth_led_spd */
+				<2 RK_PA7 6 &pcfg_pull_none>;
+		};
+	};
+
+	flash_trig {
+		flash_trig_pins: flash-trig-pins {
+			rockchip,pins =
+				/* flash_trig_out */
+				<2 RK_PB0 6 &pcfg_pull_none>;
+		};
+	};
+
+	fspi {
+		fspi_bus4_pins: fspi-bus4-pins {
+			rockchip,pins =
+				/* fspi_d0 */
+				<1 RK_PA1 2 &pcfg_pull_none>,
+				/* fspi_d1 */
+				<1 RK_PA2 2 &pcfg_pull_none>,
+				/* fspi_d2 */
+				<1 RK_PA3 2 &pcfg_pull_none>,
+				/* fspi_d3 */
+				<1 RK_PA0 2 &pcfg_pull_none>;
+		};
+		fspi_cs0_pins: fspi-cs0-pins {
+			rockchip,pins =
+				/* fspi_cs0n */
+				<1 RK_PA5 2 &pcfg_pull_up>;
+		};
+		fspi_clk_pins: fspi-clk-pins {
+			rockchip,pins =
+				/* fspi_clk */
+				<1 RK_PA4 2 &pcfg_pull_none>;
+		};
+	};
+
+	fspi_testclk {
+		fspi_testclk_out_pins: fspi-testclk-out-pins {
+			rockchip,pins =
+				/* fspi_testclk_out */
+				<1 RK_PA7 5 &pcfg_pull_none>;
+		};
+	};
+
+	fspi_testdata {
+		fspi_testdata_out_pins: fspi-testdata-out-pins {
+			rockchip,pins =
+				/* fspi_testdata_out */
+				<1 RK_PB0 5 &pcfg_pull_none>;
+		};
+	};
+
+	i2c0 {
+		i2c0m0_xfer_pins: i2c0m0-xfer-pins {
+			rockchip,pins =
+				/* i2c0_scl_m0 */
+				<0 RK_PA5 3 &pcfg_pull_none_smt>,
+				/* i2c0_sda_m0 */
+				<0 RK_PA6 3 &pcfg_pull_none_smt>;
+		};
+		i2c0m1_xfer_pins: i2c0m1-xfer-pins {
+			rockchip,pins =
+				/* i2c0_scl_m1 */
+				<1 RK_PB4 5 &pcfg_pull_none_smt>,
+				/* i2c0_sda_m1 */
+				<1 RK_PB3 5 &pcfg_pull_none_smt>;
+		};
+		i2c0m2_xfer_pins: i2c0m2-xfer-pins {
+			rockchip,pins =
+				/* i2c0_scl_m2 */
+				<1 RK_PB5 2 &pcfg_pull_none_smt>,
+				/* i2c0_sda_m2 */
+				<1 RK_PB6 2 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c1 {
+		i2c1m0_xfer_pins: i2c1m0-xfer-pins {
+			rockchip,pins =
+				/* i2c1_scl_m0 */
+				<0 RK_PB0 1 &pcfg_pull_none_smt>,
+				/* i2c1_sda_m0 */
+				<0 RK_PB1 1 &pcfg_pull_none_smt>;
+		};
+		i2c1m1_xfer_pins: i2c1m1-xfer-pins {
+			rockchip,pins =
+				/* i2c1_scl_m1 */
+				<2 RK_PA4 4 &pcfg_pull_none_smt>,
+				/* i2c1_sda_m1 */
+				<2 RK_PA5 4 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c2 {
+		i2c2m0_xfer_pins: i2c2m0-xfer-pins {
+			rockchip,pins =
+				/* i2c2_scl_m0 */
+				<0 RK_PB2 1 &pcfg_pull_none_smt>,
+				/* i2c2_sda_m0 */
+				<0 RK_PB3 1 &pcfg_pull_none_smt>;
+		};
+		i2c2m1_xfer_pins: i2c2m1-xfer-pins {
+			rockchip,pins =
+				/* i2c2_scl_m1 */
+				<2 RK_PA6 4 &pcfg_pull_none_smt>,
+				/* i2c2_sda_m1 */
+				<2 RK_PA7 4 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c3 {
+		i2c3m0_xfer_pins: i2c3m0-xfer-pins {
+			rockchip,pins =
+				/* i2c3_scl_m0 */
+				<0 RK_PB4 1 &pcfg_pull_none_smt>,
+				/* i2c3_sda_m0 */
+				<0 RK_PB5 1 &pcfg_pull_none_smt>;
+		};
+		i2c3m1_xfer_pins: i2c3m1-xfer-pins {
+			rockchip,pins =
+				/* i2c3_scl_m1 */
+				<2 RK_PB3 4 &pcfg_pull_none_smt>,
+				/* i2c3_sda_m1 */
+				<2 RK_PB2 4 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c4 {
+		i2c4m0_xfer_pins: i2c4m0-xfer-pins {
+			rockchip,pins =
+				/* i2c4_scl_m0 */
+				<2 RK_PB0 4 &pcfg_pull_none_smt>,
+				/* i2c4_sda_m0 */
+				<2 RK_PB1 4 &pcfg_pull_none_smt>;
+		};
+		i2c4m1_xfer_pins: i2c4m1-xfer-pins {
+			rockchip,pins =
+				/* i2c4_scl_m1 */
+				<1 RK_PB7 2 &pcfg_pull_none_smt>,
+				/* i2c4_sda_m1 */
+				<1 RK_PC0 2 &pcfg_pull_none_smt>;
+		};
+	};
+
+	jtag {
+		jtagm0_pins: jtagm0-pins {
+			rockchip,pins =
+				/* jtag_tck_m0 */
+				<0 RK_PA5 5 &pcfg_pull_none>,
+				/* jtag_tms_m0 */
+				<0 RK_PA6 5 &pcfg_pull_none>;
+		};
+		jtagm1_pins: jtagm1-pins {
+			rockchip,pins =
+				/* jtag_tck_m1 */
+				<0 RK_PB4 3 &pcfg_pull_none>,
+				/* jtag_tms_m1 */
+				<0 RK_PB5 3 &pcfg_pull_none>;
+		};
+		jtagm2_pins: jtagm2-pins {
+			rockchip,pins =
+				/* jtag_tck_m2 */
+				<1 RK_PB4 3 &pcfg_pull_none>,
+				/* jtag_tms_m2 */
+				<1 RK_PB3 3 &pcfg_pull_none>;
+		};
+	};
+
+	pmu_debug_test {
+		pmu_debug_test_pins: pmu-debug-test-pins {
+			rockchip,pins =
+				/* pmu_debug_test_out */
+				<0 RK_PB1 5 &pcfg_pull_none>;
+		};
+	};
+
+	prelight_trig {
+		prelight_trig_pins: prelight-trig-pins {
+			rockchip,pins =
+				/* prelight_trig_out */
+				<2 RK_PB1 6 &pcfg_pull_none>;
+		};
+	};
+
+	psram_spi {
+		psram_spi_bus4_pins: psram-spi-bus4-pins {
+			rockchip,pins =
+				/* psram_spi_d0 */
+				<0 RK_PA2 4 &pcfg_pull_none>,
+				/* psram_spi_d1 */
+				<0 RK_PA1 4 &pcfg_pull_none>,
+				/* psram_spi_d2 */
+				<0 RK_PA5 4 &pcfg_pull_none>,
+				/* psram_spi_d3 */
+				<0 RK_PA6 4 &pcfg_pull_none>;
+		};
+		psram_spi_clk_pins: psram-spi-clk-pins {
+			rockchip,pins =
+				/* psram_spi_clk */
+				<0 RK_PA0 4 &pcfg_pull_none>;
+		};
+		psram_spi_cs0n_pins: psram-spi-cs0n-pins {
+			rockchip,pins =
+				/* psram_spi_cs0n */
+				<0 RK_PA4 4 &pcfg_pull_none>;
+		};
+	};
+
+	pwm0 {
+		pwm0m0_ch0_pins: pwm0m0-ch0-pins {
+			rockchip,pins =
+				/* pwm0m0_ch0 */
+				<0 RK_PA1 1 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m0_ch1_pins: pwm0m0-ch1-pins {
+			rockchip,pins =
+				/* pwm0m0_ch1 */
+				<0 RK_PA5 2 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m0_ch2_pins: pwm0m0-ch2-pins {
+			rockchip,pins =
+				/* pwm0m0_ch2 */
+				<0 RK_PA6 2 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m0_ch3_pins: pwm0m0-ch3-pins {
+			rockchip,pins =
+				/* pwm0m0_ch3 */
+				<0 RK_PA2 1 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m1_ch0_pins: pwm0m1-ch0-pins {
+			rockchip,pins =
+				/* pwm0m1_ch0 */
+				<2 RK_PA0 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m1_ch1_pins: pwm0m1-ch1-pins {
+			rockchip,pins =
+				/* pwm0m1_ch1 */
+				<2 RK_PA1 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m1_ch2_pins: pwm0m1-ch2-pins {
+			rockchip,pins =
+				/* pwm0m1_ch2 */
+				<2 RK_PA2 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m1_ch3_pins: pwm0m1-ch3-pins {
+			rockchip,pins =
+				/* pwm0m1_ch3 */
+				<2 RK_PB0 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m2_ch1_pins: pwm0m2-ch1-pins {
+			rockchip,pins =
+				/* pwm0m2_ch1 */
+				<1 RK_PB7 1 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm0m2_ch2_pins: pwm0m2-ch2-pins {
+			rockchip,pins =
+				/* pwm0m2_ch2 */
+				<1 RK_PC0 1 &pcfg_pull_none_drv_level_0>;
+		};
+	};
+
+	pwm1 {
+		pwm1m0_ch0_pins: pwm1m0-ch0-pins {
+			rockchip,pins =
+				/* pwm1m0_ch0 */
+				<0 RK_PB0 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm1m0_ch1_pins: pwm1m0-ch1-pins {
+			rockchip,pins =
+				/* pwm1m0_ch1 */
+				<0 RK_PB1 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm1m0_ch2_pins: pwm1m0-ch2-pins {
+			rockchip,pins =
+				/* pwm1m0_ch2 */
+				<0 RK_PB2 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm1m0_ch3_pins: pwm1m0-ch3-pins {
+			rockchip,pins =
+				/* pwm1m0_ch3 */
+				<0 RK_PB3 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm1m1_ch0_pins: pwm1m1-ch0-pins {
+			rockchip,pins =
+				/* pwm1m1_ch0 */
+				<2 RK_PA3 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm1m1_ch1_pins: pwm1m1-ch1-pins {
+			rockchip,pins =
+				/* pwm1m1_ch1 */
+				<2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm1m1_ch2_pins: pwm1m1-ch2-pins {
+			rockchip,pins =
+				/* pwm1m1_ch2 */
+				<2 RK_PA5 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm1m1_ch3_pins: pwm1m1-ch3-pins {
+			rockchip,pins =
+				/* pwm1m1_ch3 */
+				<2 RK_PB1 3 &pcfg_pull_none_drv_level_0>;
+		};
+	};
+
+	pwm2 {
+		pwm2m0_ch0_pins: pwm2m0-ch0-pins {
+			rockchip,pins =
+				/* pwm2m0_ch0 */
+				<1 RK_PB0 4 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm2m0_ch1_pins: pwm2m0-ch1-pins {
+			rockchip,pins =
+				/* pwm2m0_ch1 */
+				<1 RK_PA7 4 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm2m0_ch2_pins: pwm2m0-ch2-pins {
+			rockchip,pins =
+				/* pwm2m0_ch2 */
+				<1 RK_PB4 4 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm2m0_ch3_pins: pwm2m0-ch3-pins {
+			rockchip,pins =
+				/* pwm2m0_ch3 */
+				<1 RK_PB3 4 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm2m1_ch0_pins: pwm2m1-ch0-pins {
+			rockchip,pins =
+				/* pwm2m1_ch0 */
+				<2 RK_PA6 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm2m1_ch1_pins: pwm2m1-ch1-pins {
+			rockchip,pins =
+				/* pwm2m1_ch1 */
+				<2 RK_PA7 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm2m1_ch2_pins: pwm2m1-ch2-pins {
+			rockchip,pins =
+				/* pwm2m1_ch2 */
+				<2 RK_PB2 3 &pcfg_pull_none_drv_level_0>;
+		};
+		pwm2m1_ch3_pins: pwm2m1-ch3-pins {
+			rockchip,pins =
+				/* pwm2m1_ch3 */
+				<2 RK_PB3 3 &pcfg_pull_none_drv_level_0>;
+		};
+	};
+
+	pwr {
+		pwr_pins: pwr-pins {
+			rockchip,pins =
+				/* pwr_ctrl0 */
+				<0 RK_PA3 1 &pcfg_pull_none>,
+				/* pwr_ctrl1 */
+				<0 RK_PA4 1 &pcfg_pull_none>;
+		};
+	};
+
+	rtc_32k {
+		rtc_32k_pins: rtc-32k-pins {
+			rockchip,pins =
+				/* rtc_32k_out */
+				<0 RK_PA0 1 &pcfg_pull_none>;
+		};
+	};
+
+	sai {
+		sai_pins: sai-pins {
+			rockchip,pins =
+				/* sai_lrck */
+				<2 RK_PB1 5 &pcfg_pull_none>,
+				/* sai_mclk */
+				<2 RK_PB0 5 &pcfg_pull_none>,
+				/* sai_sclk */
+				<2 RK_PA7 5 &pcfg_pull_none>,
+				/* sai_sdi */
+				<2 RK_PA6 5 &pcfg_pull_none>,
+				/* sai_sdo */
+				<2 RK_PB2 5 &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc0 {
+		sdmmc0_bus4_pins: sdmmc0-bus4-pins {
+			rockchip,pins =
+				/* sdmmc0_d0 */
+				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d1 */
+				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d2 */
+				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d3 */
+				<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+		};
+		sdmmc0_clk_pins: sdmmc0-clk-pins {
+			rockchip,pins =
+				/* sdmmc0_clk */
+				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+		};
+		sdmmc0_cmd_pins: sdmmc0-cmd-pins {
+			rockchip,pins =
+				/* sdmmc0_cmd */
+				<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+		};
+		sdmmc0_det_pins: sdmmc0-det-pins {
+			rockchip,pins =
+				/* sdmmc0_det */
+				<1 RK_PA6 1 &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc1 {
+		sdmmc1_bus4_pins: sdmmc1-bus4-pins {
+			rockchip,pins =
+				/* sdmmc1_d0 */
+				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d1 */
+				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d2 */
+				<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d3 */
+				<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+		};
+		sdmmc1_clk_pins: sdmmc1-clk-pins {
+			rockchip,pins =
+				/* sdmmc1_clk */
+				<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
+		};
+		sdmmc1_cmd_pins: sdmmc1-cmd-pins {
+			rockchip,pins =
+				/* sdmmc1_cmd */
+				<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+		};
+	};
+
+	sdmmc0_testclk {
+		sdmmc0_testclk_clk_pins: sdmmc0-testclk-clk-pins {
+			rockchip,pins =
+				/* sdmmc0_testclk_out */
+				<1 RK_PA0 3 &pcfg_pull_up_drv_level_2>;
+		};
+	};
+
+	sdmmc0_testdata {
+		sdmmc0_testdata_out_pins: sdmmc0-testdata-out-pins {
+			rockchip,pins =
+				/* sdmmc0_testdata_out */
+				<1 RK_PA3 3 &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc1_testclk {
+		sdmmc1_testclk_clk_pins: sdmmc1-testclk-clk-pins {
+			rockchip,pins =
+				/* sdmmc1_testclk_out */
+				<2 RK_PA6 7 &pcfg_pull_up_drv_level_2>;
+		};
+	};
+
+	sdmmc1_testdata {
+		sdmmc1_testdata_out_pins: sdmmc1-testdata-out-pins {
+			rockchip,pins =
+				/* sdmmc1_testdata_out */
+				<2 RK_PA7 7 &pcfg_pull_none>;
+		};
+	};
+
+	spi0 {
+		spi0m0_clk_pins: spi0m0-clk-pins {
+			rockchip,pins =
+				/* spi0_clk_m0 */
+				<2 RK_PB0 2 &pcfg_pull_none>,
+				/* spi0_miso_m0 */
+				<2 RK_PB3 2 &pcfg_pull_none>,
+				/* spi0_mosi_m0 */
+				<2 RK_PB1 2 &pcfg_pull_none>;
+		};
+		spi0m0_cs0_pins: spi0m0-cs0-pins {
+			rockchip,pins =
+				/* spi0_cs0n_m0 */
+				<2 RK_PB2 2 &pcfg_pull_none>;
+		};
+		spi0m0_cs1_pins: spi0m0-cs1-pins {
+			rockchip,pins =
+				/* spi0_cs1n_m0 */
+				<2 RK_PA7 2 &pcfg_pull_none>;
+		};
+		spi0m1_clk_pins: spi0m1-clk-pins {
+			rockchip,pins =
+				/* spi0_clk_m1 */
+				<2 RK_PA2 5 &pcfg_pull_none>,
+				/* spi0_miso_m1 */
+				<2 RK_PA4 5 &pcfg_pull_none>,
+				/* spi0_mosi_m1 */
+				<2 RK_PA1 5 &pcfg_pull_none>;
+		};
+		spi0m1_cs0_pins: spi0m1-cs0-pins {
+			rockchip,pins =
+				/* spi0_cs0n_m1 */
+				<2 RK_PA3 5 &pcfg_pull_none>;
+		};
+		spi0m1_cs1_pins: spi0m1-cs1-pins {
+			rockchip,pins =
+				/* spi0_cs1n_m1 */
+				<2 RK_PA0 5 &pcfg_pull_none>;
+		};
+	};
+
+	uart0 {
+		uart0m0_xfer_pins: uart0m0-xfer-pins {
+			rockchip,pins =
+				/* uart0_rx_m0 */
+				<0 RK_PA6 1 &pcfg_pull_up>,
+				/* uart0_tx_m0 */
+				<0 RK_PA5 1 &pcfg_pull_up>;
+		};
+		uart0m1_xfer_pins: uart0m1-xfer-pins {
+			rockchip,pins =
+				/* uart0_rx_m1 */
+				<0 RK_PB5 2 &pcfg_pull_up>,
+				/* uart0_tx_m1 */
+				<0 RK_PB4 2 &pcfg_pull_up>;
+		};
+		uart0m2_xfer_pins: uart0m2-xfer-pins {
+			rockchip,pins =
+				/* uart0_rx_m2 */
+				<1 RK_PB3 2 &pcfg_pull_up>,
+				/* uart0_tx_m2 */
+				<1 RK_PB4 2 &pcfg_pull_up>;
+		};
+	};
+
+	uart1 {
+		uart1m0_xfer_pins: uart1m0-xfer-pins {
+			rockchip,pins =
+				/* uart1_rx_m0 */
+				<0 RK_PB2 2 &pcfg_pull_up>,
+				/* uart1_tx_m0 */
+				<0 RK_PB3 2 &pcfg_pull_up>;
+		};
+		uart1m0_ctsn_pins: uart1m0-ctsn-pins {
+			rockchip,pins =
+				/* uart1m0_ctsn */
+				<0 RK_PB5 5 &pcfg_pull_none>;
+		};
+		uart1m0_rtsn_pins: uart1m0-rtsn-pins {
+			rockchip,pins =
+				/* uart1m0_rtsn */
+				<0 RK_PB4 5 &pcfg_pull_none>;
+		};
+		uart1m1_xfer_pins: uart1m1-xfer-pins {
+			rockchip,pins =
+				/* uart1_rx_m1 */
+				<1 RK_PA7 2 &pcfg_pull_up>,
+				/* uart1_tx_m1 */
+				<1 RK_PB0 2 &pcfg_pull_up>;
+		};
+		uart1m1_ctsn_pins: uart1m1-ctsn-pins {
+			rockchip,pins =
+				/* uart1m1_ctsn */
+				<1 RK_PB2 2 &pcfg_pull_none>;
+		};
+		uart1m1_rtsn_pins: uart1m1-rtsn-pins {
+			rockchip,pins =
+				/* uart1m1_rtsn */
+				<1 RK_PB1 2 &pcfg_pull_none>;
+		};
+		uart1m2_xfer_pins: uart1m2-xfer-pins {
+			rockchip,pins =
+				/* uart1_rx_m2 */
+				<2 RK_PA7 1 &pcfg_pull_up>,
+				/* uart1_tx_m2 */
+				<2 RK_PA6 1 &pcfg_pull_up>;
+		};
+		uart1m2_ctsn_pins: uart1m2-ctsn-pins {
+			rockchip,pins =
+				/* uart1m2_ctsn */
+				<2 RK_PA5 2 &pcfg_pull_none>;
+		};
+		uart1m2_rtsn_pins: uart1m2-rtsn-pins {
+			rockchip,pins =
+				/* uart1m2_rtsn */
+				<2 RK_PA4 2 &pcfg_pull_none>;
+		};
+		uart1m3_xfer_pins: uart1m3-xfer-pins {
+			rockchip,pins =
+				/* uart1_rx_m3 */
+				<2 RK_PA3 2 &pcfg_pull_up>,
+				/* uart1_tx_m3 */
+				<2 RK_PA2 2 &pcfg_pull_up>;
+		};
+		uart1m3_ctsn_pins: uart1m3-ctsn-pins {
+			rockchip,pins =
+				/* uart1m3_ctsn */
+				<2 RK_PA1 2 &pcfg_pull_none>;
+		};
+		uart1m3_rtsn_pins: uart1m3-rtsn-pins {
+			rockchip,pins =
+				/* uart1m3_rtsn */
+				<2 RK_PA0 2 &pcfg_pull_none>;
+		};
+	};
+
+	uart2 {
+		uart2m0_xfer_pins: uart2m0-xfer-pins {
+			rockchip,pins =
+				/* uart2_rx_m0 */
+				<0 RK_PB1 2 &pcfg_pull_up>,
+				/* uart2_tx_m0 */
+				<0 RK_PB0 2 &pcfg_pull_up>;
+		};
+		uart2m0_ctsn_pins: uart2m0-ctsn-pins {
+			rockchip,pins =
+				/* uart2m0_ctsn */
+				<0 RK_PB3 5 &pcfg_pull_none>;
+		};
+		uart2m0_rtsn_pins: uart2m0-rtsn-pins {
+			rockchip,pins =
+				/* uart2m0_rtsn */
+				<0 RK_PB2 5 &pcfg_pull_none>;
+		};
+		uart2m1_xfer_pins: uart2m1-xfer-pins {
+			rockchip,pins =
+				/* uart2_rx_m1 */
+				<2 RK_PB1 1 &pcfg_pull_up>,
+				/* uart2_tx_m1 */
+				<2 RK_PB0 1 &pcfg_pull_up>;
+		};
+		uart2m1_ctsn_pins: uart2m1-ctsn-pins {
+			rockchip,pins =
+				/* uart2m1_ctsn */
+				<2 RK_PB3 1 &pcfg_pull_none>;
+		};
+		uart2m1_rtsn_pins: uart2m1-rtsn-pins {
+			rockchip,pins =
+				/* uart2m1_rtsn */
+				<2 RK_PB2 1 &pcfg_pull_none>;
+		};
+		uart2m2_xfer_pins: uart2m2-xfer-pins {
+			rockchip,pins =
+				/* uart2_rx_m2 */
+				<1 RK_PB6 3 &pcfg_pull_up>,
+				/* uart2_tx_m2 */
+				<1 RK_PB5 3 &pcfg_pull_up>;
+		};
+		uart2m2_ctsn_pins: uart2m2-ctsn-pins {
+			rockchip,pins =
+				/* uart2m2_ctsn */
+				<1 RK_PC0 3 &pcfg_pull_none>;
+		};
+		uart2m2_rtsn_pins: uart2m2-rtsn-pins {
+			rockchip,pins =
+				/* uart2m2_rtsn */
+				<1 RK_PB7 3 &pcfg_pull_none>;
+		};
+	};
+};
+
+&pinctrl {
+	sdmmc0 {
+		sdmmc0_clk_idle_pins: sdmmc0-clk-idle-pins {
+			rockchip,pins =
+				/* sdmmc0_clk */
+				<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+		sdmmc0_cmd_idle_pins: sdmmc0-cmd-idle-pins {
+			rockchip,pins =
+				/* sdmmc0_cmd */
+				<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+		sdmmc0_bus1_pins: sdmmc0-bus1-pins {
+			rockchip,pins =
+				/* sdmmc0_d0 */
+				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+		};
+		sdmmc0_bus1_idle_pins: sdmmc0-bus1-idle-pins {
+			rockchip,pins =
+				/* sdmmc0_d0 */
+				<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+		sdmmc0_bus4_idle_pins: sdmmc0-bus4-idle-pins {
+			rockchip,pins =
+				/* sdmmc0_d0 */
+				<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>,
+				/* sdmmc0_d1 */
+				<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
+				/* sdmmc0_d2 */
+				<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>,
+				/* sdmmc0_d3 */
+				<1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sdmmc1 {
+		sdmmc1_bus1_pins: sdmmc1-bus1-pins {
+			rockchip,pins =
+				/* sdmmc1_d0 */
+				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/rockchip/rv1103b.dtsi b/arch/arm/boot/dts/rockchip/rv1103b.dtsi
new file mode 100644
index 000000000000..380637b63ef5
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103b.dtsi
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	compatible = "rockchip,rv1103b";
+
+	interrupt-parent = <&gic>;
+
+	arm-pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>;
+	};
+
+	xin32k: oscillator-32k {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		#clock-cells = <0>;
+	};
+
+	xin24m: oscillator-24m {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xin24m";
+		#clock-cells = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			clocks = <&cru ARMCLK>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+		clock-frequency = <24000000>;
+	};
+
+	cru: clock-controller@20000000 {
+		compatible = "rockchip,rv1103b-cru";
+		reg = <0x20000000 0x81000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+
+		assigned-clocks = <&cru PLL_GPLL>, <&cru CLK_GPLL_DIV12>;
+		assigned-clock-rates = <1188000000>, <100000000>;
+	};
+
+	/*
+	 * Merge all GRF, each independent GRF offset is shown as bellow:
+	 * VEPU_GRF:		0x20100000
+	 * NPU_GRF:		0x20110000
+	 * VI_GRF:		0x20120000
+	 * CPU_GRF:		0x20130000
+	 * DDR_GRF:		0x20140000
+	 * SYS_GRF:		0x20150000
+	 * PMU_GRF:		0x20160000
+	 */
+	grf: syscon@20100000 {
+		compatible = "rockchip,rv1103b-grf", "syscon", "simple-mfd";
+		reg = <0x20100000 0x61000>;
+
+		reboot_mode: reboot-mode {
+			compatible = "syscon-reboot-mode";
+			offset = <0x60200>;
+		};
+	};
+
+	ioc: syscon@20170000 {
+		compatible = "rockchip,rv1103b-ioc", "syscon";
+		reg = <0x20170000 0x60000>;
+	};
+
+	gic: interrupt-controller@20411000 {
+		compatible = "arm,gic-400";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+
+		reg = <0x20411000 0x1000>,
+		      <0x20412000 0x2000>,
+		      <0x20414000 0x2000>,
+		      <0x20416000 0x2000>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	uart0: serial@20540000 {
+		compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
+		reg = <0x20540000 0x100>;
+		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart0m0_xfer_pins>;
+		status = "disabled";
+	};
+
+	sdmmc1: mmc@20650000 {
+		compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x20650000 0x4000>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_bus4_pins>;
+		status = "disabled";
+	};
+
+	uart1: serial@20870000 {
+		compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
+		reg = <0x20870000 0x100>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart1m0_xfer_pins>;
+		status = "disabled";
+	};
+
+	uart2: serial@20880000 {
+		compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
+		reg = <0x20880000 0x100>;
+		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m0_xfer_pins>;
+		status = "disabled";
+	};
+
+	wdt: watchdog@208d0000 {
+		compatible = "snps,dw-wdt";
+		reg = <0x208d0000 0x100>;
+		clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+		clock-names = "tclk", "pclk";
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	sdmmc0: mmc@20d20000 {
+		compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x20d20000 0x4000>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
+		pinctrl-names = "normal", "idle";
+		pinctrl-0 = <&sdmmc0_det_pins
+			     &sdmmc0_clk_pins
+			     &sdmmc0_cmd_pins
+			     &sdmmc0_bus4_pins>;
+		pinctrl-1 = <&sdmmc0_det_pins
+			     &sdmmc0_clk_idle_pins
+			     &sdmmc0_cmd_idle_pins
+			     &sdmmc0_bus4_idle_pins>;
+		status = "disabled";
+	};
+
+	emmc: mmc@20d30000 {
+		compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x20d30000 0x4000>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
+		status = "disabled";
+	};
+
+	fspi0: spi@20d40000 {
+		compatible = "rockchip,sfc";
+		reg = <0x20d40000 0x4000>;
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>;
+		clock-names = "clk_sfc", "hclk_sfc";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	system_sram: sram@210f6000 {
+		compatible = "mmio-sram";
+		reg = <0x210f6000 0x8000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x210f6000 0x8000>;
+	};
+
+	pinctrl: pinctrl {
+		compatible = "rockchip,rv1103b-pinctrl";
+		rockchip,grf = <&ioc>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gpio0: gpio@20520000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x20520000 0x200>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio1: gpio@20d80000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x20d80000 0x200>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 32 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@20840000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x20840000 0x200>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 64 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+#include "rv1103b-pinctrl.dtsi"
-- 
2.34.1

[PATCH 10/11] dt-bindings: arm: rockchip: Add Onion RV1103B Omega4

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

Onion Omega4 board is a board based on the RV1103B SoC.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index ae77ded9fe47..40c6f7f90755 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -793,6 +793,11 @@ properties:
               - lunzn,fastrhino-r68s
           - const: rockchip,rk3568
 
+      - description: Onion RV1103B Omega4 board
+        items:
+          - const: onion,rv1103b-omega4
+          - const: rockchip,rv1103b
+
       - description: mqmaker MiQi
         items:
           - const: mqmaker,miqi
-- 
2.34.1

[PATCH 11/11] ARM: dts: rockchip: Add Onion RV1103B Omega4

[Fabio Estevam]

From: Fabio Estevam <festevam@nabladev.com>

Onion Omega4 board is a board based on the RV1103B SoC that has:

- 256 MB of RAM
- 256 MB of SPI-NAND
- Ethernet
- USB OTG
- Wifi
- SD card
- Camera connector

Add the initial support for this board so that it can fully boot into
Linux with the root file system stored in the SPI NAND.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
 arch/arm/boot/dts/rockchip/Makefile           |  1 +
 arch/arm/boot/dts/rockchip/rv1103b-omega4.dts | 92 +++++++++++++++++++
 2 files changed, 93 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103b-omega4.dts

diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile
index 716f5540e438..d8cd5df138cc 100644
--- a/arch/arm/boot/dts/rockchip/Makefile
+++ b/arch/arm/boot/dts/rockchip/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+	rv1103b-omega4.dtb \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb \
 	rv1109-relfor-saib.dtb \
diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4.dts b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dts
new file mode 100644
index 000000000000..512b063bceb1
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2025 plan44.ch/luz
+ * Copyright (c) 2025 Onion Corporation
+ */
+
+/dts-v1/;
+
+#include "rv1103b.dtsi"
+
+/ {
+	model = "Onion RV1103 Omega4 Board";
+	compatible = "onion,rv1103b-omega4", "rockchip,rv1103b";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0	{
+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+			label = "sys";
+			default-state = "on";
+		};
+	};
+};
+
+&fspi0 {
+	bootph-all;
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <75000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "env";
+				reg = <0x00000000 0x00040000>;
+			};
+
+			partition@40000 {
+				label = "idblock";
+				reg = <0x00040000 0x00100000>;
+				read-only;
+			};
+
+			partition@140000 {
+				label = "uboot";
+				reg = <0x00140000 0x00100000>;
+				read-only;
+			};
+
+			partition@240000 {
+				label = "boot";
+				reg = <0x00240000 0x00800000>;
+			};
+
+			partition@a40000 {
+				label = "ubi";
+				reg = <0x00a40000 0x0f5c0000>;
+			};
+		};
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0m0_xfer_pins>;
+	bootph-all;
+	status = "okay";
+};
+
+&wdt {
+	bootph-all;
+	status = "okay";
+};
-- 
2.34.1

Re: [PATCH 02/11] dt-bindings: clk: rockchip: Add RV1103B clock header

[Jonas Karlman]

Hi Fabio,

On 2/6/2026 7:13 PM, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> Add the RV1103B clock and reset IDs.
> 
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---
>  .../dt-bindings/clock/rockchip,rv1103b-cru.h  | 488 ++++++++++++++++++
>  1 file changed, 488 insertions(+)
>  create mode 100644 include/dt-bindings/clock/rockchip,rv1103b-cru.h
> 
> diff --git a/include/dt-bindings/clock/rockchip,rv1103b-cru.h b/include/dt-bindings/clock/rockchip,rv1103b-cru.h
> new file mode 100644
> index 000000000000..92c994185354
> --- /dev/null
> +++ b/include/dt-bindings/clock/rockchip,rv1103b-cru.h
> @@ -0,0 +1,488 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
> +
> +/* pll clocks */
> +#define PLL_GPLL				1
> +#define ARMCLK					2
> +#define PLL_DPLL				3
> +
> +/* clk (clocks) */
> +#define XIN_OSC0_HALF				5
> +#define CLK_GPLL_DIV24				6

Clock indices should start at 0 and be a continuous series without gaps.

[snip]

> +// PERICRU_SOFTRST_CON00(Offset:0xA00)
> +#define SRST_ARESETN_PERI_BIU			0x00000002
> +#define SRST_HRESETN_HPMCU_BIU			0x00000003
> +#define SRST_LSRESETN_PERI_BIU			0x00000004
> +#define SRST_PRESETN_PERI_BIU			0x00000005
> +#define SRST_PRESETN_RTC_BIU			0x00000006
> +#define SRST_HRESETN_BOOTROM			0x00000007

Reset indices should start at 0 and be a continuous series, they should
not encode register offset and bit information like downstream kernel.

Also please move the resets indices to a separate header, see most
recent Rockchip SoCs clock and reset additions, e.g. rk3528, rk3506 or
rk3562 for inspiration.

[snip]

> +#define CLK_NR_SRST				(SRST_PRESETN_CRU_PMU1 + 1)

Please drop this, not part of the binding.

Regards,
Jonas

> +#endif

Re: [PATCH 11/11] ARM: dts: rockchip: Add Onion RV1103B Omega4

[Jonas Karlman]

Hi Fabio,

On 2/6/2026 7:13 PM, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> Onion Omega4 board is a board based on the RV1103B SoC that has:
> 
> - 256 MB of RAM
> - 256 MB of SPI-NAND
> - Ethernet
> - USB OTG
> - Wifi
> - SD card
> - Camera connector
> 
> Add the initial support for this board so that it can fully boot into
> Linux with the root file system stored in the SPI NAND.
> 
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---
>  arch/arm/boot/dts/rockchip/Makefile           |  1 +
>  arch/arm/boot/dts/rockchip/rv1103b-omega4.dts | 92 +++++++++++++++++++
>  2 files changed, 93 insertions(+)
>  create mode 100644 arch/arm/boot/dts/rockchip/rv1103b-omega4.dts
> 
> diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile
> index 716f5540e438..d8cd5df138cc 100644
> --- a/arch/arm/boot/dts/rockchip/Makefile
> +++ b/arch/arm/boot/dts/rockchip/Makefile
> @@ -1,5 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += \
> +	rv1103b-omega4.dtb \
>  	rv1108-elgin-r1.dtb \
>  	rv1108-evb.dtb \
>  	rv1109-relfor-saib.dtb \
> diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4.dts b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dts
> new file mode 100644
> index 000000000000..512b063bceb1
> --- /dev/null
> +++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dts
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + * Copyright (c) 2025 plan44.ch/luz
> + * Copyright (c) 2025 Onion Corporation
> + */
> +
> +/dts-v1/;
> +
> +#include "rv1103b.dtsi"
> +
> +/ {
> +	model = "Onion RV1103 Omega4 Board";
> +	compatible = "onion,rv1103b-omega4", "rockchip,rv1103b";
> +
> +	chosen {
> +		stdout-path = &uart0;

Please add a serial0 alias and use the following form to match most
other Rockchip boards.

 		stdout-path = "serial0:115200n8";

> +	};
> +
> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x0 0x10000000>;
> +	};

Memory nodes is typically added by firmware on Rockchip platform.

Size of the DRAM is typically encoded in OS_REG2 by the DRAM init
code and can/should be picked up from there for next boot stages.

> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led-0	{
> +			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;

Please add pinctrl props for this pin. Also please add function and
color props.

> +			label = "sys";
> +			default-state = "on";
> +		};
> +	};
> +};
> +
> +&fspi0 {
> +	bootph-all;

This is not really needed in all boot phases, the initial phase only
initialize DRAM and then return to BootROM so does not need to know
about the spi flash.

Also adding it here is not enough, please instead add bootph props to
the flash@0 or possible partitions node.

For optimal boot performance and size consideration you should drop
this and add following bootph props.

> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "spi-nand";
> +		reg = <0>;

		bootph-pre-ram;
		bootph-some-ram;

Adding these here ensure that this and the parent node is included in
the second stage and the pre-relocation boot-phase, the only phases they
are needed.

Regards,
Jonas

> +		spi-max-frequency = <75000000>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <1>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "env";
> +				reg = <0x00000000 0x00040000>;
> +			};
> +
> +			partition@40000 {
> +				label = "idblock";
> +				reg = <0x00040000 0x00100000>;
> +				read-only;
> +			};
> +
> +			partition@140000 {
> +				label = "uboot";
> +				reg = <0x00140000 0x00100000>;
> +				read-only;
> +			};
> +
> +			partition@240000 {
> +				label = "boot";
> +				reg = <0x00240000 0x00800000>;
> +			};
> +
> +			partition@a40000 {
> +				label = "ubi";
> +				reg = <0x00a40000 0x0f5c0000>;
> +			};
> +		};
> +	};
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0m0_xfer_pins>;
> +	bootph-all;
> +	status = "okay";
> +};
> +
> +&wdt {
> +	bootph-all;
> +	status = "okay";
> +};

Re: [PATCH 01/11] dt-bindings: clock: rockchip: Add RV1103B clock and reset unit

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 03:12:59PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> Add device tree bindings for the clock and reset unit for the RV1103B SoC.
> 
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---
>  .../bindings/clock/rockchip,rv1103b-cru.yaml  | 63 +++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml
> new file mode 100644
> index 000000000000..fa7298955aea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1103b-cru.yaml

Exactly the same as rv1126b and others. Why do you need separate file?

Best regards,
Krzysztof

Re: [PATCH 00/11] ARM: rockchip: Add initial RV1103B and Omega4 board support

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 03:12:58PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> This series adds initial support for the Rockchip RV1103B SoC and
> the Omega4 board.
> 
> The goal of this series is to provide the minimal device tree and
> platform support required to boot the Omega4 board into Linux
> userspace with the root filesystem located on SPI NAND.
> 
> The series includes:
> 
>   - Base RV1103B SoC device tree description
>   - Omega4 board device tree
>   - Required pinctrl and clock definitions
>   - Basic peripheral enablement required for boot
> 
> With this series applied, the Omega4 board is able to:
> 
>   - Initialize DRAM
>   - Boot the kernel
>   - Access SPI NAND
>   - Mount the root filesystem from SPI NAND
>   - Reach userspace successfully
> 
> This submission intentionally focuses on minimal bring-up support.
> Additional peripheral enablement and feature support will be
> submitted separately.
> 
> Tested on Omega4 hardware based on the RV1103B SoC.
> 
> Boot verified with root filesystem stored on SPI NAND.
> 
> Fabio Estevam (11):
>   dt-bindings: clock: rockchip: Add RV1103B clock and reset unit
>   dt-bindings: clk: rockchip: Add RV1103B clock header
>   clk: rockchip: Add clock controller for the RV1103B
>   dt-bindings: pinctrl: Add RV1103B pinctrl support
>   pinctrl: rockchip: Add RV1103B pinctrl support
>   dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for R1103B
>   dt-bindings: serial: snps-dw-apb-uart: Add support for RV1103B
>   dt-bindings: soc: rockchip: Add RV1103B IOC and GRF entries
>   ARM: dts: rockchip: Add support for RV1103B
>   dt-bindings: arm: rockchip: Add Onion RV1103B Omega4
>   ARM: dts: rockchip: Add Onion RV1103B Omega4

I don't understand why you combine around 6 different subsystems into
one patchset, especially that there are no dependencies. Only difficult
for maintainers to apply.

Best regards,
Krzysztof

Re: [PATCH 10/11] dt-bindings: arm: rockchip: Add Onion RV1103B Omega4

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 03:13:08PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> Onion Omega4 board is a board based on the RV1103B SoC.
> 
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---
>  Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
> index ae77ded9fe47..40c6f7f90755 100644
> --- a/Documentation/devicetree/bindings/arm/rockchip.yaml
> +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
> @@ -793,6 +793,11 @@ properties:
>                - lunzn,fastrhino-r68s
>            - const: rockchip,rk3568
>  
> +      - description: Onion RV1103B Omega4 board

What's with the sorting? Why is this between L and M?

Best regards,
Krzysztof

Re: [PATCH 06/11] dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for R1103B

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 03:13:04PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> The dw-mshc controller in the RV1103B is compatible to the one first found
> in the RK3288 SoC, so add the RV1103B to the variant list.
> 
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Cc: linux-mmc@vger.kernel.org

Please drop the autogenerated scripts/get_maintainer.pl CC-entries from
commit msg. There is no single need to store automated output of
get_maintainers.pl in the git log. It can be easily re-created at any
given time, thus its presence in the git history is redundant and
obfuscates the log.

If you need it for your own patch management purposes, keep it under the
--- separator.

It's confusing way of new soc bringup. Maintainer receives one patch out
of 11 and what has to do with it? Apply? Ack? Where is it explained?

And before you answer that this is supposed to be applied by Rockchip,
then NO, it was explained many times and is documented in bindings for
years that it goes via MMC.

Best regards,
Krzysztof

Re: [PATCH 07/11] dt-bindings: serial: snps-dw-apb-uart: Add support for RV1103B

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 03:13:05PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> The UART used in the RV1103B SoC is still the same dw-apb-uart compatible
> type as on the SoCs that came before, so add the RV1103B to the list
> of variants.
> 
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-serial@vger.kernel.org
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>

Greg expressed MANY times that patches for him should be sent
separately.

Best regards,
Krzysztof

Re: [PATCH 02/11] dt-bindings: clk: rockchip: Add RV1103B clock header

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 03:13:00PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> Add the RV1103B clock and reset IDs.

NAK, that's never a separate patch from the binding. If you have to make
it a separate patch, it's a proof your patchset is incorrectly organized
and lacks proper description for maintainers how to handle new soc.

And adding new soc is nothing odd, we keep doing it all the time.

Best regards,
Krzysztof

Re: [PATCH 02/11] dt-bindings: clk: rockchip: Add RV1103B clock header

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 03:13:00PM -0300, Fabio Estevam wrote:
> +#define MCLK_ACODEC_TX				204
> +#define SCLK_UART0_SRC				205
> +#define SCLK_UART1_SRC				206
> +#define SCLK_UART2_SRC				207
> +#define XIN_RC_SRC				208
> +#define CLK_UTMI_USBOTG				209
> +#define CLK_REF_USBPHY				230
> +
> +// PERICRU_SOFTRST_CON00(Offset:0xA00)
> +#define SRST_ARESETN_PERI_BIU			0x00000002

NAK, not a binding. Nothing below is a binding.

> +#define SRST_HRESETN_HPMCU_BIU			0x00000003
> +#define SRST_LSRESETN_PERI_BIU			0x00000004
> +#define SRST_PRESETN_PERI_BIU			0x00000005
> +#define SRST_PRESETN_RTC_BIU			0x00000006
> +#define SRST_HRESETN_BOOTROM			0x00000007

...

> +// ======================= PMU1CRU module definition bank=9 =======================
> +// PMU1CRU_SOFTRST_CON00(Offset:0xA00)
> +#define SRST_PRESETN_SPI2AHB			0x00200000
> +#define SRST_HRESETN_SPI2AHB			0x00200001
> +#define SRST_SRESETN_SPI2AHB			0x00200002
> +#define SRST_LSRESETN_PMU_BIU			0x00200003
> +#define SRST_PRESETN_WDT_LPMCU			0x00200009
> +#define SRST_TRESETN_WDT_LPMCU			0x0020000A
> +#define SRST_HRESETN_SFC_PMU1			0x0020000C
> +#define SRST_HRESETN_SFC_XIP_PMU1		0x0020000D
> +#define SRST_SRESETN_SFC_2X_PMU1		0x0020000E
> +
> +// PMU1CRU_SOFTRST_CON01(Offset:0xA04)
> +#define SRST_PRESETN_LPMCU_MAILBOX		0x00200018
> +#define SRST_PRESETN_IOC_PMUIO1			0x00200019
> +#define SRST_PRESETN_CRU_PMU1			0x0020001A
> +
> +#define CLK_NR_SRST				(SRST_PRESETN_CRU_PMU1 + 1)

Not a binding, either

> +
> +#endif
> -- 
> 2.34.1
> 

Re: [PATCH 08/11] dt-bindings: soc: rockchip: Add RV1103B IOC and GRF entries

[Krzysztof Kozlowski]

On Fri, Feb 06, 2026 at 03:13:06PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> The "General Register Files" provide additional setting bits
> outside the regular IP block register space and it is accessed via syscon.
> 
> Document the RV1103B IOC and GRF compatible strings.
> 
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---
>  Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Why there is no update to the list of children? You added it with MFD
fallback on purpose.

Best regards,
Krzysztof

Re: [PATCH 07/11] dt-bindings: serial: snps-dw-apb-uart: Add support for RV1103B

[Greg Kroah-Hartman]

On Sat, Feb 07, 2026 at 11:59:06AM +0100, Krzysztof Kozlowski wrote:
> On Fri, Feb 06, 2026 at 03:13:05PM -0300, Fabio Estevam wrote:
> > From: Fabio Estevam <festevam@nabladev.com>
> > 
> > The UART used in the RV1103B SoC is still the same dw-apb-uart compatible
> > type as on the SoCs that came before, so add the RV1103B to the list
> > of variants.
> > 
> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > Cc: linux-serial@vger.kernel.org
> > Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> 
> Greg expressed MANY times that patches for him should be sent
> separately.

It's easy, I just ignore them now :)