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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3nD791PGhNSs1srywJYmQcw5LmHRg4F3hPWJLTXM9L2XwkmkbYM7sxHMr0+yMDUF//pSuuhvZt5acO8ymj4tdia5AR4SJLzkGNP50gU0uR6NrYXu0X7ZHSBMNSWQ8Gxx9xgOFk2+bJRZW/NI890Bo7hoyO3/ZR2EKGPwJtlCicvgfqunjxFhkBsKK6aBGXoERME3B/YPNlMaM09zAqQot/1BhpOk6RLM2IqcWvU8Q90WEpIPGgi/Zi52AIMiCIHSRgV/pIwLmYRfSp0cGYZquBiDNzgqzz1hBMASFHyvB44IEIiktN3NeJEMcDSgztWkFisyKck0H/MZL2ZTOAit4nFJrvn0uYjfT2hQ/9sssEaAP/7iV6s2rE5uhty7TSbFIc4Jzywc9RI33RsTXjwxAHLSUzf9Uf6v9NN2VDCBNMmDSIGu5IcYR/KQ1IfgqEBV X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Feb 2026 05:55:26.2571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02ef24ce-60c5-445d-2082-08de6de925e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9286 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260216_215536_444471_4F4A3A0C X-CRM114-Status: GOOD ( 11.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the EPF does not allocate backing memory. The host-side pci_endpoint_test driver still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no longer available for real use (e.g. host DMA via BAR4). This series addresses that by: 1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core. BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is for unused BARs that the EPC must disable in .init() and the EPF must not use. pci_epc_get_next_free_bar() treats both as not free. 2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4: BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA. Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay enabled so the host can use MSI-X and DMA. 3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5 (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B) to the pci_endpoint_test_tbl so the host driver can bind and run tests without corrupting MSI-X or DMA registers. 4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of 64-bit BAR0 and BAR2. With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use. pci_endpoint_test results on Tegra234 SoC, $ ./pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -V dma TAP version 13 1..13 Starting 13 tests from 8 test cases. RUN pci_ep_bar.BAR0.BAR_TEST ... OK pci_ep_bar.BAR0.BAR_TEST ok 1 pci_ep_bar.BAR0.BAR_TEST RUN pci_ep_bar.BAR1.BAR_TEST ... OK pci_ep_bar.BAR1.BAR_TEST ok 2 pci_ep_bar.BAR1.BAR_TEST RUN pci_ep_bar.BAR2.BAR_TEST ... OK pci_ep_bar.BAR2.BAR_TEST ok 3 pci_ep_bar.BAR2.BAR_TEST RUN pci_ep_bar.BAR3.BAR_TEST ... OK pci_ep_bar.BAR3.BAR_TEST ok 4 pci_ep_bar.BAR3.BAR_TEST RUN pci_ep_bar.BAR4.BAR_TEST ... OK pci_ep_bar.BAR4.BAR_TEST ok 5 pci_ep_bar.BAR4.BAR_TEST RUN pci_ep_bar.BAR5.BAR_TEST ... OK pci_ep_bar.BAR5.BAR_TEST ok 6 pci_ep_bar.BAR5.BAR_TEST RUN pci_ep_basic.CONSECUTIVE_BAR_TEST ... OK pci_ep_basic.CONSECUTIVE_BAR_TEST ok 7 pci_ep_basic.CONSECUTIVE_BAR_TEST RUN pci_ep_basic.LEGACY_IRQ_TEST ... OK pci_ep_basic.LEGACY_IRQ_TEST ok 8 pci_ep_basic.LEGACY_IRQ_TEST RUN pci_ep_basic.MSI_TEST ... SKIP MSI17 is disabled OK pci_ep_basic.MSI_TEST ok 9 pci_ep_basic.MSI_TEST # SKIP MSI17 is disabled RUN pci_ep_basic.MSIX_TEST ... pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X1 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X2 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X3 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X4 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X5 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X6 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X7 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X8 SKIP MSI-X9 is disabled OK pci_ep_basic.MSIX_TEST ok 10 pci_ep_basic.MSIX_TEST # SKIP MSI-X9 is disabled RUN pci_ep_data_transfer.memcpy.READ_TEST ... OK pci_ep_data_transfer.memcpy.READ_TEST ok 11 pci_ep_data_transfer.memcpy.READ_TEST RUN pci_ep_data_transfer.memcpy.WRITE_TEST ... OK pci_ep_data_transfer.memcpy.WRITE_TEST ok 12 pci_ep_data_transfer.memcpy.WRITE_TEST RUN pci_ep_data_transfer.memcpy.COPY_TEST ... OK pci_ep_data_transfer.memcpy.COPY_TEST ok 13 pci_ep_data_transfer.memcpy.COPY_TEST PASSED: 13 / 13 tests passed. 2 skipped test(s) detected. Consider enabling relevant config options to improve coverage. Totals: pass:11 fail:0 xfail:0 xpass:0 skip:2 error:0 Signed-off-by: Manikanta Maddireddy --- Manikanta Maddireddy (4): PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5 drivers/misc/pci_endpoint_test.c | 34 ++++++++++++++++++++++++--- drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++--------- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 8 +++---- drivers/pci/endpoint/pci-epc-core.c | 5 ++-- include/linux/pci-epc.h | 13 ++++++++-- 5 files changed, 64 insertions(+), 22 deletions(-) --- base-commit: 6f54fb70124423ec417b5efe81f8ced5b9891d62 change-id: 20260217-master-27db95eb02bd Best regards, -- Manikanta Maddireddy