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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS3PEPF0000C37C.mail.protection.outlook.com (10.167.23.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Tue, 17 Feb 2026 05:55:45 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 16 Feb 2026 21:55:24 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 16 Feb 2026 21:55:18 -0800 From: Manikanta Maddireddy To: Niklas Cassel , Vidya Sagar , Manivannan Sadhasivam , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Kishon Vijay Abraham I" , Bjorn Helgaas , "Lorenzo Pieralisi" , Rob Herring , "Thierry Reding" , Jonathan Hunter , Arnd Bergmann , Greg Kroah-Hartman , Kunihiko Hayashi , Masami Hiramatsu CC: Manikanta Maddireddy , , , , Subject: [PATCH 2/4] PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode Date: Tue, 17 Feb 2026 11:24:42 +0530 Message-ID: <20260217-master-v1-2-727e26cdfaf5@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260217-master-v1-0-727e26cdfaf5@nvidia.com> References: <20260217-master-v1-0-727e26cdfaf5@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: v+lUwcvDySUQLGetDuI3v4dEW+SLGOwvmtb4FJxvKLwKP+pK8Bca4r9ZI3eiHOfrEXajf9SObYXg9cK1j9WNH86vRnBIamtMPAqh+dOKyqjqGFaMomcTdl4dFZoQzFMbGBUHBOlK2d3Yy23g8OvtPgTzD2Jww7HDA78JUJB5+UbwJ2RPjJEDd+wgB1RZtd8aDx1G/gf5Hu/Ei2BzSdgiPJlLEyOV318WY5fk8s0mgOlKia1clLGGzORimUy5ZRYk2KLvhLR7uAUFofQJkCmXimVSPNZIXpc4LLi6otGXdrDobBNcY30dXL9Z40AWK9IfI8njVUkT8zUb0c1cFuHw1s7rIvEU8urS9QNXJAd3HbA8gnTTQOSGWbl4V2zsIYR3c85HouXZ47McPDpOjSr/OfiY9FMzlEb4HbtIPvAw/cJ29YXtX5Oz7uJPsw4Fljcl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Feb 2026 05:55:45.8780 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 422cd343-aefc-4093-8df3-08de6de9319c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4292 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260216_215554_252070_693F3C64 X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Tegra194 endpoint exposes three 64-bit BARs at indices 0, 2, and 4: - BAR0+BAR1: EPF test/data (first 64-bit BAR) - BAR2+BAR3: MSI-X table (HW-backed) - BAR4+BAR5: DMA registers (HW-backed) Update tegra_pcie_epc_features so that BAR0 is BAR_FIXED with only_64bit, BAR1 is BAR_RESERVED (high half of 64-bit BAR0), BAR2/BAR3 are BAR_RESERVED with only_64bit on BAR2 (MSI-X), and BAR4/BAR5 are BAR_RESERVED with only_64bit on BAR4 (DMA). In tegra_pcie_ep_init(), reset only BAR0 and BAR1 so that the first 64-bit BAR is disabled until the EPF enables it via set_bar. Do not reset BAR2+BAR3 or BAR4+BAR5 so that MSI-X and DMA remain enabled for the host. This keeps CONSECUTIVE_BAR_TEST and DMA tests working while allowing the host to use 64-bit BAR 2 (MSI-X) and 64-bit BAR 4 (DMA) for real use. BAR0 is capabale of supporting various sizes using DBI2 BAR registers which are programmed in dw_pcie_ep_set_bar_programmable(), remove 1 MB size limit from pci_epc_features. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 1b4fc6a9bed1..6734d1336ef1 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1948,11 +1948,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg) static void tegra_pcie_ep_init(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - enum pci_barno bar; - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) - dw_pcie_ep_reset_bar(pci, bar); -}; + /* + * Only reset the first 64-bit BAR (BAR0+BAR1); EPF will enable it via set_bar. + * BAR2+BAR3 (MSI-X table) and BAR4+BAR5 (DMA regs) are HW-backed and must + * stay enabled. + */ + dw_pcie_ep_reset_bar(pci, BAR_0); + dw_pcie_ep_reset_bar(pci, BAR_1); +} static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq) { @@ -2009,16 +2013,16 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +/* Tegra194 EP: BAR0 = programmable BAR, BAR2 = MSI-X table, BAR4 = DMA regs. */ static const struct pci_epc_features tegra_pcie_epc_features = { .linkup_notifier = true, .msi_capable = true, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, - .only_64bit = true, }, - .bar[BAR_1] = { .type = BAR_RESERVED, }, - .bar[BAR_2] = { .type = BAR_RESERVED, }, - .bar[BAR_3] = { .type = BAR_RESERVED, }, - .bar[BAR_4] = { .type = BAR_RESERVED, }, - .bar[BAR_5] = { .type = BAR_RESERVED, }, + .bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, }, + .bar[BAR_1] = { .type = BAR_RESERVED, }, /* high half of 64-bit BAR0 */ + .bar[BAR_2] = { .type = BAR_RESERVED, .only_64bit = true, }, /* MSI-X table */ + .bar[BAR_3] = { .type = BAR_RESERVED, }, /* high half of 64-bit BAR2 */ + .bar[BAR_4] = { .type = BAR_RESERVED, .only_64bit = true, }, /* DMA regs */ + .bar[BAR_5] = { .type = BAR_RESERVED, }, /* high half of 64-bit BAR4 */ .align = SZ_64K, }; -- 2.34.1