From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: "Niklas Cassel" <cassel@kernel.org>,
"Vidya Sagar" <vidyas@nvidia.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Arnd Bergmann" <arnd@arndb.de>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Kunihiko Hayashi" <hayashi.kunihiko@socionext.com>,
"Masami Hiramatsu" <mhiramat@kernel.org>
Cc: Manikanta Maddireddy <mmaddireddy@nvidia.com>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-tegra@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH 3/4] misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs
Date: Tue, 17 Feb 2026 11:24:43 +0530 [thread overview]
Message-ID: <20260217-master-v1-3-727e26cdfaf5@nvidia.com> (raw)
In-Reply-To: <20260217-master-v1-0-727e26cdfaf5@nvidia.com>
Add an optional bar_skip_mask to pci_endpoint_test_data so that
endpoints with HW-backed BARs (e.g. MSI-X table, DMA regs) can skip
the destructive BAR read/write test on those BARs. When a BAR is
skipped, it is not written or read in the consecutive BAR test, and
PCITEST_BAR ioctl for that BAR returns -EINVAL.
Add Tegra endpoint test data with bar_skip_mask set to skip BAR1
through BAR5 (test only BAR0, the first 64-bit BAR). Add
pci_endpoint_test_tbl entries for NVIDIA Tegra194 EP (device ID
0x1AD4) and Tegra234 EP (device ID 0x229B) so the host test driver
can bind and run tests without corrupting MSI-X or DMA registers.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/misc/pci_endpoint_test.c | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 1c0fd185114f..4c9f02dbc41b 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -100,6 +100,12 @@
#define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588
+#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP 0x1ad4
+#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP 0x229b
+
+/* BARs 1-5 are HW-backed (MSI-X, DMA) or high half of 64-bit BAR0; skip BAR test */
+#define TEGRA_EP_BAR_SKIP_MASK (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
+
static DEFINE_IDA(pci_endpoint_test_ida);
#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
@@ -130,11 +136,15 @@ struct pci_endpoint_test {
size_t alignment;
u32 ep_caps;
const char *name;
+ /* Bitmask of BARs to skip in BAR test (bit N set = skip BAR N) */
+ u8 bar_skip_mask;
};
struct pci_endpoint_test_data {
enum pci_barno test_reg_bar;
size_t alignment;
+ /* Bitmask of BARs to skip in BAR test (bit N set = skip BAR N) */
+ u8 bar_skip_mask;
};
static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
@@ -393,9 +403,10 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
int ret;
/* Write all BARs in order (without reading). */
- for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
- if (test->bar[bar])
+ for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
+ if (test->bar[bar] && !(test->bar_skip_mask & (1 << bar)))
pci_endpoint_test_bars_write_bar(test, bar);
+ }
/*
* Read all BARs in order (without writing).
@@ -404,7 +415,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
* (Reading back the BAR directly after writing can not detect this.)
*/
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
- if (test->bar[bar]) {
+ if (test->bar[bar] && !(test->bar_skip_mask & (1 << bar))) {
ret = pci_endpoint_test_bars_read_bar(test, bar);
if (ret)
return ret;
@@ -941,6 +952,10 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
goto ret;
if (is_am654_pci_dev(pdev) && bar == BAR_0)
goto ret;
+ if (test->bar_skip_mask & (1 << bar)) {
+ ret = 0;
+ goto ret;
+ }
ret = pci_endpoint_test_bar(test, bar);
break;
case PCITEST_BARS:
@@ -1028,6 +1043,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
test_reg_bar = data->test_reg_bar;
test->test_reg_bar = test_reg_bar;
test->alignment = data->alignment;
+ test->bar_skip_mask = data->bar_skip_mask;
}
init_completion(&test->irq_raised);
@@ -1173,6 +1189,12 @@ static const struct pci_endpoint_test_data rk3588_data = {
.alignment = SZ_64K,
};
+static const struct pci_endpoint_test_data tegra_ep_data = {
+ .test_reg_bar = BAR_0,
+ .alignment = SZ_64K,
+ .bar_skip_mask = TEGRA_EP_BAR_SKIP_MASK,
+};
+
/*
* If the controller's Vendor/Device ID are programmable, you may be able to
* use one of the existing entries for testing instead of adding a new one.
@@ -1217,6 +1239,12 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588),
.driver_data = (kernel_ulong_t)&rk3588_data,
},
+ { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA194_EP),
+ .driver_data = (kernel_ulong_t)&tegra_ep_data,
+ },
+ { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA234_EP),
+ .driver_data = (kernel_ulong_t)&tegra_ep_data,
+ },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
--
2.34.1
next prev parent reply other threads:[~2026-02-17 5:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-17 5:54 [PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework Manikanta Maddireddy
2026-02-17 5:54 ` [PATCH 1/4] PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics Manikanta Maddireddy
2026-02-17 5:54 ` [PATCH 2/4] PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode Manikanta Maddireddy
2026-02-17 5:54 ` Manikanta Maddireddy [this message]
2026-02-17 5:54 ` [PATCH 4/4] PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5 Manikanta Maddireddy
2026-02-17 6:08 ` [PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework Manikanta Maddireddy
2026-02-17 21:38 ` Niklas Cassel
2026-02-23 3:28 ` Manikanta Maddireddy
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