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From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: "Niklas Cassel" <cassel@kernel.org>,
	"Vidya Sagar" <vidyas@nvidia.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Arnd Bergmann" <arnd@arndb.de>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Kunihiko Hayashi" <hayashi.kunihiko@socionext.com>,
	"Masami Hiramatsu" <mhiramat@kernel.org>
Cc: Manikanta Maddireddy <mmaddireddy@nvidia.com>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH 4/4] PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5
Date: Tue, 17 Feb 2026 11:24:44 +0530	[thread overview]
Message-ID: <20260217-master-v1-4-727e26cdfaf5@nvidia.com> (raw)
In-Reply-To: <20260217-master-v1-0-727e26cdfaf5@nvidia.com>

On Uniphier Pro5, BAR_4 and BAR_5 are not the high half of a 64-bit
BAR (BAR_4 has no only_64bit set) and are not HW-backed; they are
unused. Convert them from BAR_RESERVED to BAR_DISABLED. Add comments
for BAR_1 and BAR_3 to clarify they are the high halves of 64-bit
BAR0 and BAR2.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-uniphier-ep.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index d6e73811216e..cf5131eec7bf 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -425,11 +425,11 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
 		.msix_capable = false,
 		.align = 1 << 16,
 		.bar[BAR_0] = { .only_64bit = true, },
-		.bar[BAR_1] = { .type = BAR_RESERVED, },
+		.bar[BAR_1] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR0 */
 		.bar[BAR_2] = { .only_64bit = true, },
-		.bar[BAR_3] = { .type = BAR_RESERVED, },
-		.bar[BAR_4] = { .type = BAR_RESERVED, },
-		.bar[BAR_5] = { .type = BAR_RESERVED, },
+		.bar[BAR_3] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR2 */
+		.bar[BAR_4] = { .type = BAR_DISABLED, },	/* unused */
+		.bar[BAR_5] = { .type = BAR_DISABLED, },	/* unused */
 	},
 };
 

-- 
2.34.1



  parent reply	other threads:[~2026-02-17  5:56 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-17  5:54 [PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework Manikanta Maddireddy
2026-02-17  5:54 ` [PATCH 1/4] PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics Manikanta Maddireddy
2026-02-17  5:54 ` [PATCH 2/4] PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode Manikanta Maddireddy
2026-02-17  5:54 ` [PATCH 3/4] misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs Manikanta Maddireddy
2026-02-17  5:54 ` Manikanta Maddireddy [this message]
2026-02-17  6:08 ` [PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework Manikanta Maddireddy
2026-02-17 21:38 ` Niklas Cassel
2026-02-23  3:28   ` Manikanta Maddireddy

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