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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="b27VbrnZhyUo1vZR" Content-Disposition: inline In-Reply-To: <20260217-arm-microchip-v1-3-ae5d907e10e3@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260217_095403_423602_472A4BDA X-CRM114-Status: GOOD ( 19.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --b27VbrnZhyUo1vZR Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Feb 17, 2026 at 05:24:21PM +0000, Akhila YS wrote: > Convert Atmel Periodic interval timer of 64bit (PIT64b) binding to YAML > format. > Changes during conversion: > - Add missing compatible "microchip,sama7g5-pit64b" along with a fallback > compatible "microchip,sam9x60-pit64b". >=20 > Signed-off-by: Akhila YS > --- > .../bindings/arm/microchip,sam9x60-pit64b.yaml | 71 ++++++++++++++++= ++++++ > 1 file changed, 71 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit6= 4b.yaml b/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.ya= ml > new file mode 100644 > index 000000000000..6bf8e81d4c72 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PIT64B 64-bit Periodic Interval Timer > + > +maintainers: > + - Nicolas Ferre > + - Claudiu Beznea > + > +description: > + The Microchip PIT64B is a 64-bit periodic interval timer used in > + several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and > + SAMA7D65 families. It provides extended timing range, flexible > + clock selection and supports both periodic and one-shot interrupt > + generation modes. > + > +properties: > + compatible: > + oneOf: > + - const: microchip,sam9x60-pit64b > + - items: > + - const: microchip,sama7d65-pit64b > + - const: microchip,sam9x60-pit64b > + - items: > + - const: microchip,sama7g5-pit64b > + - const: microchip,sam9x60-pit64b > + - items: > + - const: microchip,sam9x7-pit64b > + - const: microchip,sam9x60-pit64b These three can be merged into one enum + const items list. > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + oneOf: > + - const: pclk > + - items: > + - const: pclk > + - const: gclk This can be an items list with minItems: 1, but there should be some conditional logic used to permit gclk only where it is valid. The text binding removal is missing so I cannot say exactly what that logic should be. pw-bot: changes-requested Cheers, Conor. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + timer@f0028000 { > + compatible =3D "microchip,sama7g5-pit64b", "microchip,sam9x60-pi= t64b"; > + reg =3D <0xf0028000 0x100>; > + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH 7>; > + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; > + clock-names =3D "pclk", "gclk"; > + }; > +... >=20 > --=20 > 2.43.0 >=20 --b27VbrnZhyUo1vZR Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaZSrNQAKCRB4tDGHoIJi 0snqAP9WAtNwebWwwNMLqSegPZVNJSYGdpVGU3DpvMr5Px3t3gEAsSrCuNO6/02a HgrWRrt6Y4/hZY70/ZP3onU0LEW+rgM= =3Tpv -----END PGP SIGNATURE----- --b27VbrnZhyUo1vZR--