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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77b3sm570714265e9.2.2026.02.17.06.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 06:25:40 -0800 (PST) Date: Tue, 17 Feb 2026 14:25:38 +0000 From: David Laight To: Peter Zijlstra Cc: Linus Torvalds , Marco Elver , Will Deacon , Ingo Molnar , Thomas Gleixner , Boqun Feng , Waiman Long , Bart Van Assche , llvm@lists.linux.dev, Catalin Marinas , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel test robot , Boqun Feng , Al Viro Subject: Re: [PATCH v3 3/3] arm64, compiler-context-analysis: Permit alias analysis through __READ_ONCE() with CONFIG_LTO=y Message-ID: <20260217142538.0a2c0892@pumpkin> In-Reply-To: <20260217121619.GA1395266@noisy.programming.kicks-ass.net> References: <20260206182650.6c21b0ff@pumpkin> <20260215221656.68b2fc1d@pumpkin> <20260216110915.4f0d5490@pumpkin> <20260216174324.75d47e37@pumpkin> <20260217121619.GA1395266@noisy.programming.kicks-ass.net> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260217_062559_812451_32FF1F68 X-CRM114-Status: GOOD ( 22.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 17 Feb 2026 13:16:19 +0100 Peter Zijlstra wrote: > On Mon, Feb 16, 2026 at 05:43:24PM +0000, David Laight wrote: > > On Mon, 16 Feb 2026 07:32:53 -0800 > > Linus Torvalds wrote: > > > > > On Mon, 16 Feb 2026 at 03:09, David Laight wrote: > > > > > > > > volatile structure members are almost free > > > > > > No, gcc does absolutely horrible things with volatiles. It disables a > > > lot of very basic stuff. > > > > > > Try doing something as simple as a "var++" on a volatile, and cry. > > > > On x86 I just see a load, inc, store - not that surprising really. > > (clang did do 'inc memory'.) > > > > It's not as though 'inc memory' is atomic (without a lock prefix). > > > > Also var++ will be 3 u-ops the same as the read, inc, write so the > > underlying execution is much the same (ok you might save on the > > address generation and the compiler doesn't have to find a register name, > > but I don't remember anything modern being limited by instruction retirement). > > You might save a bit of I-cache. > > Interrupts can tell the difference, and that matters. Just makes it the same as every other architecture. The only way to guarantee an 'add to memory' instruction is to use an asm statement. David