From: Niklas Cassel <cassel@kernel.org>
To: "Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Frank Li" <Frank.Li@nxp.com>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>,
"Marek Vasut" <marek.vasut+renesas@gmail.com>,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Kunihiko Hayashi" <hayashi.kunihiko@socionext.com>,
"Masami Hiramatsu" <mhiramat@kernel.org>
Cc: Manikanta Maddireddy <mmaddireddy@nvidia.com>,
Koichiro Den <den@valinux.co.jp>,
Damien Le Moal <dlemoal@kernel.org>,
Niklas Cassel <cassel@kernel.org>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
imx@lists.linux.dev, linux-renesas-soc@vger.kernel.org,
linux-tegra@vger.kernel.org
Subject: [PATCH 5/9] PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers
Date: Tue, 17 Feb 2026 22:27:11 +0100 [thread overview]
Message-ID: <20260217212707.2450423-16-cassel@kernel.org> (raw)
In-Reply-To: <20260217212707.2450423-11-cassel@kernel.org>
Most DWC based EPC glue drivers that have BARs marked as BAR_RESERVED in
epc_features also call dw_pcie_ep_reset_bar() for these reserved BARs in
ep->ops->init().
An EPF driver will be able to get/enable BARs that have been disabled/reset
unless they are marked as BAR_RESERVED (see pci_epc_get_next_free_bar()).
Thus all EPC drivers that have a BAR marked as BAR_RESERVED in epc_features
AND call dw_pcie_ep_reset_bar() should really be marked as BAR_DISABLED.
BARs that are marked as BAR_RESERVED in epc_features but for which
dw_pcie_ep_reset_bar() is not called in ep->ops->init() are still kept as
BAR_RESERVED.
No EPC drivers outside drivers/pci/controllers/dwc mark their BARs as
BAR_RESERVED, so there is nothing to do in non-DWC based EPC drivers.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
drivers/pci/controller/dwc/pci-imx6.c | 12 ++++++------
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 6 +++---
drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++----
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 4 ++--
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index a5b8d0b71677..ec1e3557ca53 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1433,19 +1433,19 @@ static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
static const struct pci_epc_features imx8m_pcie_epc_features = {
DWC_EPC_COMMON_FEATURES,
.msi_capable = true,
- .bar[BAR_1] = { .type = BAR_RESERVED, },
- .bar[BAR_3] = { .type = BAR_RESERVED, },
+ .bar[BAR_1] = { .type = BAR_DISABLED, },
+ .bar[BAR_3] = { .type = BAR_DISABLED, },
.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
- .bar[BAR_5] = { .type = BAR_RESERVED, },
+ .bar[BAR_5] = { .type = BAR_DISABLED, },
.align = SZ_64K,
};
static const struct pci_epc_features imx8q_pcie_epc_features = {
DWC_EPC_COMMON_FEATURES,
.msi_capable = true,
- .bar[BAR_1] = { .type = BAR_RESERVED, },
- .bar[BAR_3] = { .type = BAR_RESERVED, },
- .bar[BAR_5] = { .type = BAR_RESERVED, },
+ .bar[BAR_1] = { .type = BAR_DISABLED, },
+ .bar[BAR_3] = { .type = BAR_DISABLED, },
+ .bar[BAR_5] = { .type = BAR_DISABLED, },
.align = SZ_64K,
};
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index a6912e85e4dd..9dd05bac22b9 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -422,10 +422,10 @@ static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
DWC_EPC_COMMON_FEATURES,
.msi_capable = true,
- .bar[BAR_1] = { .type = BAR_RESERVED, },
- .bar[BAR_3] = { .type = BAR_RESERVED, },
+ .bar[BAR_1] = { .type = BAR_DISABLED, },
+ .bar[BAR_3] = { .type = BAR_DISABLED, },
.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256 },
- .bar[BAR_5] = { .type = BAR_RESERVED, },
+ .bar[BAR_5] = { .type = BAR_DISABLED, },
.align = SZ_1M,
};
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 31aa9a494dbc..9f9453e8cd23 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1994,10 +1994,10 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
.only_64bit = true, },
.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
- .bar[BAR_2] = { .type = BAR_RESERVED, },
- .bar[BAR_3] = { .type = BAR_RESERVED, },
- .bar[BAR_4] = { .type = BAR_RESERVED, },
- .bar[BAR_5] = { .type = BAR_RESERVED, },
+ .bar[BAR_2] = { .type = BAR_DISABLED, },
+ .bar[BAR_3] = { .type = BAR_DISABLED, },
+ .bar[BAR_4] = { .type = BAR_DISABLED, },
+ .bar[BAR_5] = { .type = BAR_DISABLED, },
.align = SZ_64K,
};
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index f873a1659592..5bde3ee682b5 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -429,8 +429,8 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
.bar[BAR_2] = { .only_64bit = true, },
.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
- .bar[BAR_4] = { .type = BAR_RESERVED, },
- .bar[BAR_5] = { .type = BAR_RESERVED, },
+ .bar[BAR_4] = { .type = BAR_DISABLED, },
+ .bar[BAR_5] = { .type = BAR_DISABLED, },
},
};
--
2.53.0
next prev parent reply other threads:[~2026-02-17 21:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260217212707.2450423-11-cassel@kernel.org>
2026-02-17 21:27 ` [PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER Niklas Cassel
2026-02-17 21:57 ` Frank Li
[not found] ` <81af7f88-b9c1-457f-9a21-a7b15a13d374@nvidia.com>
2026-02-23 10:14 ` Geert Uytterhoeven
2026-02-24 13:54 ` Manikanta Maddireddy
2026-02-17 21:27 ` [PATCH 3/9] PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window Niklas Cassel
2026-02-23 4:10 ` Manikanta Maddireddy
2026-02-17 21:27 ` Niklas Cassel [this message]
2026-02-17 22:15 ` [PATCH 5/9] PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers Frank Li
2026-02-23 4:46 ` Manikanta Maddireddy
2026-02-25 14:56 ` Niklas Cassel
2026-02-17 21:27 ` [PATCH 6/9] PCI: dwc: Disable BARs in common code instead of in each glue driver Niklas Cassel
2026-02-17 23:00 ` Frank Li
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