* [PATCH v9 0/3] Add support for Cix Sky1 resets
@ 2026-02-24 9:21 Gary Yang
2026-02-24 9:21 ` [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC Gary Yang
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Gary Yang @ 2026-02-24 9:21 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, p.zabel, peter.chen
Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream,
Gary Yang
Patch 1: Add yaml file for Cix Sky1 resets
Patch 2: Add driver codes for Cix Sky1 resets
Patch 3: Add dts nodes for Cix Sky1 resets
v9 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
scripts/checkpatch.pl 000*.patch
- refine reset driver
v8 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
scripts/checkpatch.pl 000*.patch
- refine reset driver
- remove "simple-mfd" strings
v7 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
scripts/checkpatch.pl 000*.patch
- fix build warning
v6 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
scripts/checkpatch.pl 000*.patch
- refine reset driver
- fix dt-bindings style
v5 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-controller.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
scripts/checkpatch.pl 000*.patch
- refine reset driver
- fix dt-bindings style
v4 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
scripts/checkpatch.pl 000*.patch
- add syscon
- refine reset driver
- fix dt-bindings style
v3 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
scripts/checkpatch.pl 000*.patch
- remove syscon
v2 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
scripts/checkpatch.pl 000*.patch
- fix dt-bindings style
- refine reset driver
Gary Yang (3):
dt-bindings: soc: cix: document the syscon on Sky1 SoC
reset: add Sky1 soc reset support
arm64: dts: cix: add support for cix sky1 resets
.../soc/cix/cix,sky1-system-control.yaml | 42 ++
arch/arm64/boot/dts/cix/sky1.dtsi | 12 +
drivers/reset/Kconfig | 7 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-sky1.c | 367 ++++++++++++++++++
include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 ++
include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++
7 files changed, 635 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
create mode 100644 drivers/reset/reset-sky1.c
create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
--
2.49.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC 2026-02-24 9:21 [PATCH v9 0/3] Add support for Cix Sky1 resets Gary Yang @ 2026-02-24 9:21 ` Gary Yang 2026-02-25 10:29 ` Krzysztof Kozlowski 2026-02-24 9:21 ` [PATCH v9 2/3] reset: add Sky1 soc reset support Gary Yang 2026-02-24 9:21 ` [PATCH v9 3/3] arm64: dts: cix: add support for cix sky1 resets Gary Yang 2 siblings, 1 reply; 10+ messages in thread From: Gary Yang @ 2026-02-24 9:21 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, p.zabel, peter.chen Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream, Gary Yang There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller is embedded as usb typeC uses it by phandle. Signed-off-by: Gary Yang <gary.yang@cixtech.com> --- .../soc/cix/cix,sky1-system-control.yaml | 42 +++++ include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++ include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++ 3 files changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file mode 100644 index 000000000000..5507deb54ebd --- /dev/null +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 SoC system control register region + +maintainers: + - Gary Yang <gary.yang@cixtech.com> + +description: + An wide assortment of registers of the system controller on Sky1 SoC, + including resets, usb, wakeup sources and so on. + +properties: + compatible: + items: + - enum: + - cix,sky1-system-control + - cix,sky1-s5-system-control + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x16000000 0x1000>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/cix,sky1-rst-fch.h b/include/dt-bindings/reset/cix,sky1-rst-fch.h new file mode 100644 index 000000000000..8e67d7eb92aa --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-rst-fch.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Author: Jerry Zhu <jerry.zhu@cixtech.com> */ +#ifndef DT_BINDING_RESET_FCH_SKY1_H +#define DT_BINDING_RESET_FCH_SKY1_H + +/* func reset for sky1 fch */ + +#define SW_I3C0_RST_FUNC_G_N 0 +#define SW_I3C0_RST_FUNC_I_N 1 +#define SW_I3C1_RST_FUNC_G_N 2 +#define SW_I3C1_RST_FUNC_I_N 3 +#define SW_UART0_RST_FUNC_N 4 +#define SW_UART1_RST_FUNC_N 5 +#define SW_UART2_RST_FUNC_N 6 +#define SW_UART3_RST_FUNC_N 7 +#define SW_TIMER_RST_FUNC_N 8 + +/* apb reset for sky1 fch */ +#define SW_I3C0_RST_APB_N 9 +#define SW_I3C1_RST_APB_N 10 +#define SW_DMA_RST_AXI_N 11 +#define SW_UART0_RST_APB_N 12 +#define SW_UART1_RST_APB_N 13 +#define SW_UART2_RST_APB_N 14 +#define SW_UART3_RST_APB_N 15 +#define SW_SPI0_RST_APB_N 16 +#define SW_SPI1_RST_APB_N 17 +#define SW_I2C0_RST_APB_N 18 +#define SW_I2C1_RST_APB_N 19 +#define SW_I2C2_RST_APB_N 20 +#define SW_I2C3_RST_APB_N 21 +#define SW_I2C4_RST_APB_N 22 +#define SW_I2C5_RST_APB_N 23 +#define SW_I2C6_RST_APB_N 24 +#define SW_I2C7_RST_APB_N 25 +#define SW_GPIO_RST_APB_N 26 + +/* fch rst for xspi */ +#define SW_XSPI_REG_RST_N 27 +#define SW_XSPI_SYS_RST_N 28 + +#endif diff --git a/include/dt-bindings/reset/cix,sky1-rst.h b/include/dt-bindings/reset/cix,sky1-rst.h new file mode 100644 index 000000000000..2f0990922aad --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-rst.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Author: Jerry Zhu <jerry.zhu@cixtech.com> */ +#ifndef DT_BINDING_RESET_SKY1_H +#define DT_BINDING_RESET_SKY1_H + +/* reset for csu_pm */ + +#define SKY1_CSU_PM_RESET_N 0 +#define SKY1_SENSORFUSION_RESET_N 1 +#define SKY1_SENSORFUSION_NOC_RESET_N 2 + +/* reset group0 for s0 domain modules */ +#define SKY1_DDRC_RESET_N 3 +#define SKY1_GIC_RESET_N 4 +#define SKY1_CI700_RESET_N 5 +#define SKY1_SYS_NI700_RESET_N 6 +#define SKY1_MM_NI700_RESET_N 7 +#define SKY1_PCIE_NI700_RESET_N 8 +#define SKY1_GPU_RESET_N 9 +#define SKY1_NPUTOP_RESET_N 10 +#define SKY1_NPUCORE0_RESET_N 11 +#define SKY1_NPUCORE1_RESET_N 12 +#define SKY1_NPUCORE2_RESET_N 13 +#define SKY1_VPU_RESET_N 14 +#define SKY1_ISP_SRESET_N 15 +#define SKY1_ISP_ARESET_N 16 +#define SKY1_ISP_HRESET_N 17 +#define SKY1_ISP_GDCRESET_N 18 +#define SKY1_DPU_RESET0_N 19 +#define SKY1_DPU_RESET1_N 20 +#define SKY1_DPU_RESET2_N 21 +#define SKY1_DPU_RESET3_N 22 +#define SKY1_DPU_RESET4_N 23 +#define SKY1_DP_RESET0_N 24 +#define SKY1_DP_RESET1_N 25 +#define SKY1_DP_RESET2_N 26 +#define SKY1_DP_RESET3_N 27 +#define SKY1_DP_RESET4_N 28 +#define SKY1_DP_PHY_RST_N 29 + +/* reset group1 for s0 domain modules */ +#define SKY1_AUDIO_HIFI5_RESET_N 30 +#define SKY1_AUDIO_HIFI5_NOC_RESET_N 31 +#define SKY1_CSIDPHY_PRST0_N 32 +#define SKY1_CSIDPHY_CMNRST0_N 33 +#define SKY1_CSI0_RST_N 34 +#define SKY1_CSIDPHY_PRST1_N 35 +#define SKY1_CSIDPHY_CMNRST1_N 36 +#define SKY1_CSI1_RST_N 37 +#define SKY1_CSI2_RST_N 38 +#define SKY1_CSI3_RST_N 39 +#define SKY1_CSIBRDGE0_RST_N 40 +#define SKY1_CSIBRDGE1_RST_N 41 +#define SKY1_CSIBRDGE2_RST_N 42 +#define SKY1_CSIBRDGE3_RST_N 43 +#define SKY1_GMAC0_RST_N 44 +#define SKY1_GMAC1_RST_N 45 +#define SKY1_PCIE0_RESET_N 46 +#define SKY1_PCIE1_RESET_N 47 +#define SKY1_PCIE2_RESET_N 48 +#define SKY1_PCIE3_RESET_N 49 +#define SKY1_PCIE4_RESET_N 50 + +/* reset group1 for usb phys */ +#define SKY1_USB_DP_PHY0_PRST_N 51 +#define SKY1_USB_DP_PHY1_PRST_N 52 +#define SKY1_USB_DP_PHY2_PRST_N 53 +#define SKY1_USB_DP_PHY3_PRST_N 54 +#define SKY1_USB_DP_PHY0_RST_N 55 +#define SKY1_USB_DP_PHY1_RST_N 56 +#define SKY1_USB_DP_PHY2_RST_N 57 +#define SKY1_USB_DP_PHY3_RST_N 58 +#define SKY1_USBPHY_SS_PST_N 59 +#define SKY1_USBPHY_SS_RST_N 60 +#define SKY1_USBPHY_HS0_PRST_N 61 +#define SKY1_USBPHY_HS1_PRST_N 62 +#define SKY1_USBPHY_HS2_PRST_N 63 +#define SKY1_USBPHY_HS3_PRST_N 64 +#define SKY1_USBPHY_HS4_PRST_N 65 +#define SKY1_USBPHY_HS5_PRST_N 66 +#define SKY1_USBPHY_HS6_PRST_N 67 +#define SKY1_USBPHY_HS7_PRST_N 68 +#define SKY1_USBPHY_HS8_PRST_N 69 +#define SKY1_USBPHY_HS9_PRST_N 70 + +/* reset group1 for usb controllers */ +#define SKY1_USBC_SS0_PRST_N 71 +#define SKY1_USBC_SS1_PRST_N 72 +#define SKY1_USBC_SS2_PRST_N 73 +#define SKY1_USBC_SS3_PRST_N 74 +#define SKY1_USBC_SS4_PRST_N 75 +#define SKY1_USBC_SS5_PRST_N 76 +#define SKY1_USBC_SS0_RST_N 77 +#define SKY1_USBC_SS1_RST_N 78 +#define SKY1_USBC_SS2_RST_N 79 +#define SKY1_USBC_SS3_RST_N 80 +#define SKY1_USBC_SS4_RST_N 81 +#define SKY1_USBC_SS5_RST_N 82 +#define SKY1_USBC_HS0_PRST_N 83 +#define SKY1_USBC_HS1_PRST_N 84 +#define SKY1_USBC_HS2_PRST_N 85 +#define SKY1_USBC_HS3_PRST_N 86 +#define SKY1_USBC_HS0_RST_N 87 +#define SKY1_USBC_HS1_RST_N 88 +#define SKY1_USBC_HS2_RST_N 89 +#define SKY1_USBC_HS3_RST_N 90 + +/* reset group0 for rcsu */ +#define SKY1_AUDIO_RCSU_RESET_N 91 +#define SKY1_CI700_RCSU_RESET_N 92 +#define SKY1_CSI_RCSU0_RESET_N 93 +#define SKY1_CSI_RCSU1_RESET_N 94 +#define SKY1_CSU_PM_RCSU_RESET_N 95 +#define SKY1_DDR_BROADCAST_RCSU_RESET_N 96 +#define SKY1_DDR_CTRL_RCSU_0_RESET_N 97 +#define SKY1_DDR_CTRL_RCSU_1_RESET_N 98 +#define SKY1_DDR_CTRL_RCSU_2_RESET_N 99 +#define SKY1_DDR_CTRL_RCSU_3_RESET_N 100 +#define SKY1_DDR_TZC400_RCSU_0_RESET_N 101 +#define SKY1_DDR_TZC400_RCSU_1_RESET_N 102 +#define SKY1_DDR_TZC400_RCSU_2_RESET_N 103 +#define SKY1_DDR_TZC400_RCSU_3_RESET_N 104 +#define SKY1_DP0_RCSU_RESET_N 105 +#define SKY1_DP1_RCSU_RESET_N 106 +#define SKY1_DP2_RCSU_RESET_N 107 +#define SKY1_DP3_RCSU_RESET_N 108 +#define SKY1_DP4_RCSU_RESET_N 109 +#define SKY1_DPU0_RCSU_RESET_N 110 +#define SKY1_DPU1_RCSU_RESET_N 111 +#define SKY1_DPU2_RCSU_RESET_N 112 +#define SKY1_DPU3_RCSU_RESET_N 113 +#define SKY1_DPU4_RCSU_RESET_N 114 +#define SKY1_DSU_RCSU_RESET_N 115 +#define SKY1_FCH_RCSU_RESET_N 116 +#define SKY1_GICD_RCSU_RESET_N 117 +#define SKY1_GMAC_RCSU_RESET_N 118 +#define SKY1_GPU_RCSU_RESET_N 119 +#define SKY1_ISP_RCSU0_RESET_N 120 +#define SKY1_ISP_RCSU1_RESET_N 121 +#define SKY1_NI700_MMHUB_RCSU_RESET_N 122 + +/* reset group1 for rcsu */ +#define SKY1_NPU_RCSU_RESET_N 123 +#define SKY1_NI700_PCIE_RCSU_RESET_N 124 +#define SKY1_PCIE_X421_RCSU_RESET_N 125 +#define SKY1_PCIE_X8_RCSU_RESET_N 126 +#define SKY1_SF_RCSU_RESET_N 127 +#define SKY1_RCSU_SMMU_MMHUB_RESET_N 128 +#define SKY1_RCSU_SMMU_PCIEHUB_RESET_N 129 +#define SKY1_RCSU_SYSHUB_RESET_N 130 +#define SKY1_NI700_SMN_RCSU_RESET_N 131 +#define SKY1_NI700_SYSHUB_RCSU_RESET_N 132 +#define SKY1_RCSU_USB2_HOST0_RESET_N 133 +#define SKY1_RCSU_USB2_HOST1_RESET_N 134 +#define SKY1_RCSU_USB2_HOST2_RESET_N 135 +#define SKY1_RCSU_USB2_HOST3_RESET_N 136 +#define SKY1_RCSU_USB3_TYPEA_DRD_RESET_N 137 +#define SKY1_RCSU_USB3_TYPEC_DRD_RESET_N 138 +#define SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N 139 +#define SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N 140 +#define SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N 141 +#define SKY1_VPU_RCSU_RESET_N 142 + +#endif -- 2.49.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC 2026-02-24 9:21 ` [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC Gary Yang @ 2026-02-25 10:29 ` Krzysztof Kozlowski 2026-02-25 10:30 ` Krzysztof Kozlowski 0 siblings, 1 reply; 10+ messages in thread From: Krzysztof Kozlowski @ 2026-02-25 10:29 UTC (permalink / raw) To: Gary Yang Cc: robh, krzk+dt, conor+dt, p.zabel, peter.chen, devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream On Tue, Feb 24, 2026 at 05:21:09PM +0800, Gary Yang wrote: > + > +additionalProperties: false > + > +examples: > + - | > + syscon@16000000 { > + compatible = "cix,sky1-s5-system-control", "syscon"; > + reg = <0x16000000 0x1000>; > + #reset-cells = <1>; > + }; > diff --git a/include/dt-bindings/reset/cix,sky1-rst-fch.h b/include/dt-bindings/reset/cix,sky1-rst-fch.h I am not going to repeat my reviews. NAK, I mark it as changes requested in Patchwork. Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC 2026-02-25 10:29 ` Krzysztof Kozlowski @ 2026-02-25 10:30 ` Krzysztof Kozlowski 2026-02-25 11:15 ` 回复: " Gary Yang 0 siblings, 1 reply; 10+ messages in thread From: Krzysztof Kozlowski @ 2026-02-25 10:30 UTC (permalink / raw) To: Gary Yang Cc: robh, krzk+dt, conor+dt, p.zabel, peter.chen, devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream On 25/02/2026 11:29, Krzysztof Kozlowski wrote: > On Tue, Feb 24, 2026 at 05:21:09PM +0800, Gary Yang wrote: >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + syscon@16000000 { >> + compatible = "cix,sky1-s5-system-control", "syscon"; >> + reg = <0x16000000 0x1000>; >> + #reset-cells = <1>; >> + }; >> diff --git a/include/dt-bindings/reset/cix,sky1-rst-fch.h b/include/dt-bindings/reset/cix,sky1-rst-fch.h > > I am not going to repeat my reviews. Quoting myself last time from second email: "It's the last time I am asking you of it" > > NAK, I mark it as changes requested in Patchwork. > > Krzysztof > Best regards, Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* 回复: [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC 2026-02-25 10:30 ` Krzysztof Kozlowski @ 2026-02-25 11:15 ` Gary Yang 2026-02-25 11:46 ` Krzysztof Kozlowski 0 siblings, 1 reply; 10+ messages in thread From: Gary Yang @ 2026-02-25 11:15 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, Peter Chen, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cix-kernel-upstream Hi Krzysztof: I'm sorry for my mistakes. > EXTERNAL EMAIL > > On 25/02/2026 11:29, Krzysztof Kozlowski wrote: > > On Tue, Feb 24, 2026 at 05:21:09PM +0800, Gary Yang wrote: > >> + > >> +additionalProperties: false > >> + > >> +examples: > >> + - | > >> + syscon@16000000 { > >> + compatible = "cix,sky1-s5-system-control", "syscon"; > >> + reg = <0x16000000 0x1000>; > >> + #reset-cells = <1>; > >> + }; > >> diff --git a/include/dt-bindings/reset/cix,sky1-rst-fch.h > b/include/dt-bindings/reset/cix,sky1-rst-fch.h > > > > I am not going to repeat my reviews. > > Quoting myself last time from second email: > > "It's the last time I am asking you of it" > > > > > NAK, I mark it as changes requested in Patchwork. > > > > Krzysztof > > > Sorry for missing your advices. We just come back from the Chinese New Year Festival. It almost takes two weeks, so we forget your advices. Do you mean that cix,sky1-rst-fch.h should be named cix,sky1-system-control.h and cix,sky1-rst.h should be named cix,sky1-s5-system-control.h? Are there other advices forgot, except this one? Please give us one more chances. If miss any information, please let us know. Thanks Best Regards Gary > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: 回复: [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC 2026-02-25 11:15 ` 回复: " Gary Yang @ 2026-02-25 11:46 ` Krzysztof Kozlowski 0 siblings, 0 replies; 10+ messages in thread From: Krzysztof Kozlowski @ 2026-02-25 11:46 UTC (permalink / raw) To: Gary Yang Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, Peter Chen, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cix-kernel-upstream On 25/02/2026 12:15, Gary Yang wrote: > Hi Krzysztof: > > I'm sorry for my mistakes. > >> EXTERNAL EMAIL >> >> On 25/02/2026 11:29, Krzysztof Kozlowski wrote: >>> On Tue, Feb 24, 2026 at 05:21:09PM +0800, Gary Yang wrote: >>>> + >>>> +additionalProperties: false >>>> + >>>> +examples: >>>> + - | >>>> + syscon@16000000 { >>>> + compatible = "cix,sky1-s5-system-control", "syscon"; >>>> + reg = <0x16000000 0x1000>; >>>> + #reset-cells = <1>; >>>> + }; >>>> diff --git a/include/dt-bindings/reset/cix,sky1-rst-fch.h >> b/include/dt-bindings/reset/cix,sky1-rst-fch.h >>> >>> I am not going to repeat my reviews. >> >> Quoting myself last time from second email: >> >> "It's the last time I am asking you of it" >> >>> >>> NAK, I mark it as changes requested in Patchwork. >>> >>> Krzysztof >>> >> > > Sorry for missing your advices. We just come back from the Chinese New Year Festival. > It almost takes two weeks, so we forget your advices. Do you mean that cix,sky1-rst-fch.h > should be named cix,sky1-system-control.h and cix,sky1-rst.h should be named cix,sky1-s5-system-control.h? > Are there other advices forgot, except this one? Please give us one more chances. > > If miss any information, please let us know. Thanks The same filename as used for binding. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v9 2/3] reset: add Sky1 soc reset support 2026-02-24 9:21 [PATCH v9 0/3] Add support for Cix Sky1 resets Gary Yang 2026-02-24 9:21 ` [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC Gary Yang @ 2026-02-24 9:21 ` Gary Yang 2026-02-24 10:12 ` Philipp Zabel 2026-02-24 9:21 ` [PATCH v9 3/3] arm64: dts: cix: add support for cix sky1 resets Gary Yang 2 siblings, 1 reply; 10+ messages in thread From: Gary Yang @ 2026-02-24 9:21 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, p.zabel, peter.chen Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream, Gary Yang Add support for the resets on Cix's Sky1 SoC. There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. Signed-off-by: Gary Yang <gary.yang@cixtech.com> --- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-sky1.c | 367 +++++++++++++++++++++++++++++++++++++ 3 files changed, 375 insertions(+) create mode 100644 drivers/reset/reset-sky1.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6e5d6deffa7d..0aaac1b88d02 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -291,6 +291,13 @@ config RESET_SIMPLE - SiFive FU740 SoCs - Sophgo SoCs +config RESET_SKY1 + bool "Cix Sky1 reset controller" + depends on OF && REGMAP_MMIO + depends on ARCH_CIX || COMPILE_TEST + help + This enables the reset controller for Cix Sky1. + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) default ARM && ARCH_INTEL_SOCFPGA diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 9c3e484dfd81..0d2e1329561d 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o +obj-$(CONFIG_RESET_SKY1) += reset-sky1.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o diff --git a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c new file mode 100644 index 000000000000..fb8a919fd3f7 --- /dev/null +++ b/drivers/reset/reset-sky1.c @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * + * CIX System Reset Controller (SRC) driver + * + * Author: Jerry Zhu <jerry.zhu@cixtech.com> + */ + +#include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#include <dt-bindings/reset/cix,sky1-rst.h> +#include <dt-bindings/reset/cix,sky1-rst-fch.h> + +#define SKY1_RESET_SLEEP_MIN_US 50 +#define SKY1_RESET_SLEEP_MAX_US 100 + +struct sky1_src_signal { + unsigned int offset; + unsigned int bit; +}; + +struct sky1_src_variant { + const struct sky1_src_signal *signals; + unsigned int signals_num; +}; + +struct sky1_src { + struct reset_controller_dev rcdev; + const struct sky1_src_signal *signals; + struct regmap *regmap; +}; + +enum { + CSU_PM_RESET = 0x304, + SENSORFUSION_RESET = 0x308, + SENSORFUSION_NOC_RESET = 0x30c, + RESET_GROUP0_S0_DOMAIN_0 = 0x400, + RESET_GROUP0_S0_DOMAIN_1 = 0x404, + RESET_GROUP1_USB_PHYS = 0x408, + RESET_GROUP1_USB_CONTROLLERS = 0x40c, + RESET_GROUP0_RCSU = 0x800, + RESET_GROUP1_RCSU = 0x804, +}; + +static const struct sky1_src_signal sky1_src_signals[] = { + /* reset group1 for s0 domain modules */ + [SKY1_CSU_PM_RESET_N] = { CSU_PM_RESET, BIT(0) }, + [SKY1_SENSORFUSION_RESET_N] = { SENSORFUSION_RESET, BIT(0) }, + [SKY1_SENSORFUSION_NOC_RESET_N] = { SENSORFUSION_NOC_RESET, BIT(0) }, + [SKY1_DDRC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(0) }, + [SKY1_GIC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(1) }, + [SKY1_CI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(2) }, + [SKY1_SYS_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(3) }, + [SKY1_MM_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(4) }, + [SKY1_PCIE_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(5) }, + [SKY1_GPU_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(6) }, + [SKY1_NPUTOP_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(7) }, + [SKY1_NPUCORE0_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(8) }, + [SKY1_NPUCORE1_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(9) }, + [SKY1_NPUCORE2_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(10) }, + [SKY1_VPU_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(11) }, + [SKY1_ISP_SRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(12) }, + [SKY1_ISP_ARESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(13) }, + [SKY1_ISP_HRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(14) }, + [SKY1_ISP_GDCRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(15) }, + [SKY1_DPU_RESET0_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(16) }, + [SKY1_DPU_RESET1_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(17) }, + [SKY1_DPU_RESET2_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(18) }, + [SKY1_DPU_RESET3_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(19) }, + [SKY1_DPU_RESET4_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(20) }, + [SKY1_DP_RESET0_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(21) }, + [SKY1_DP_RESET1_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(22) }, + [SKY1_DP_RESET2_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(23) }, + [SKY1_DP_RESET3_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(24) }, + [SKY1_DP_RESET4_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(25) }, + [SKY1_DP_PHY_RST_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(26) }, + + /* reset group1 for s0 domain modules */ + [SKY1_AUDIO_HIFI5_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(0) }, + [SKY1_AUDIO_HIFI5_NOC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(1) }, + [SKY1_CSIDPHY_PRST0_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(2) }, + [SKY1_CSIDPHY_CMNRST0_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(3) }, + [SKY1_CSI0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(4) }, + [SKY1_CSIDPHY_PRST1_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(5) }, + [SKY1_CSIDPHY_CMNRST1_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(6) }, + [SKY1_CSI1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(7) }, + [SKY1_CSI2_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(8) }, + [SKY1_CSI3_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(9) }, + [SKY1_CSIBRDGE0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(10) }, + [SKY1_CSIBRDGE1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(11) }, + [SKY1_CSIBRDGE2_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(12) }, + [SKY1_CSIBRDGE3_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(13) }, + [SKY1_GMAC0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(14) }, + [SKY1_GMAC1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(15) }, + [SKY1_PCIE0_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(16) }, + [SKY1_PCIE1_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(17) }, + [SKY1_PCIE2_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(18) }, + [SKY1_PCIE3_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(19) }, + [SKY1_PCIE4_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(20) }, + + /* reset group1 for usb phys */ + [SKY1_USB_DP_PHY0_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(0) }, + [SKY1_USB_DP_PHY1_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(1) }, + [SKY1_USB_DP_PHY2_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(2) }, + [SKY1_USB_DP_PHY3_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(3) }, + [SKY1_USB_DP_PHY0_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(4) }, + [SKY1_USB_DP_PHY1_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(5) }, + [SKY1_USB_DP_PHY2_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(6) }, + [SKY1_USB_DP_PHY3_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(7) }, + [SKY1_USBPHY_SS_PST_N] = { RESET_GROUP1_USB_PHYS, BIT(8) }, + [SKY1_USBPHY_SS_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(9) }, + [SKY1_USBPHY_HS0_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(10) }, + [SKY1_USBPHY_HS1_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(11) }, + [SKY1_USBPHY_HS2_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(12) }, + [SKY1_USBPHY_HS3_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(13) }, + [SKY1_USBPHY_HS4_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(14) }, + [SKY1_USBPHY_HS5_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(15) }, + [SKY1_USBPHY_HS6_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(16) }, + [SKY1_USBPHY_HS7_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(17) }, + [SKY1_USBPHY_HS8_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(18) }, + [SKY1_USBPHY_HS9_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(19) }, + + /* reset group1 for usb controllers */ + [SKY1_USBC_SS0_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(0) }, + [SKY1_USBC_SS1_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(1) }, + [SKY1_USBC_SS2_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(2) }, + [SKY1_USBC_SS3_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(3) }, + [SKY1_USBC_SS4_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(4) }, + [SKY1_USBC_SS5_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(5) }, + [SKY1_USBC_SS0_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(6) }, + [SKY1_USBC_SS1_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(7) }, + [SKY1_USBC_SS2_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(8) }, + [SKY1_USBC_SS3_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(9) }, + [SKY1_USBC_SS4_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(10) }, + [SKY1_USBC_SS5_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(11) }, + [SKY1_USBC_HS0_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(12) }, + [SKY1_USBC_HS1_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(13) }, + [SKY1_USBC_HS2_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(14) }, + [SKY1_USBC_HS3_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(15) }, + [SKY1_USBC_HS0_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(16) }, + [SKY1_USBC_HS1_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(17) }, + [SKY1_USBC_HS2_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(18) }, + [SKY1_USBC_HS3_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(19) }, + + /* reset group0 for rcsu */ + [SKY1_AUDIO_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(0) }, + [SKY1_CI700_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(1) }, + [SKY1_CSI_RCSU0_RESET_N] = { RESET_GROUP0_RCSU, BIT(2) }, + [SKY1_CSI_RCSU1_RESET_N] = { RESET_GROUP0_RCSU, BIT(3) }, + [SKY1_CSU_PM_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(4) }, + [SKY1_DDR_BROADCAST_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(5) }, + [SKY1_DDR_CTRL_RCSU_0_RESET_N] = { RESET_GROUP0_RCSU, BIT(6) }, + [SKY1_DDR_CTRL_RCSU_1_RESET_N] = { RESET_GROUP0_RCSU, BIT(7) }, + [SKY1_DDR_CTRL_RCSU_2_RESET_N] = { RESET_GROUP0_RCSU, BIT(8) }, + [SKY1_DDR_CTRL_RCSU_3_RESET_N] = { RESET_GROUP0_RCSU, BIT(9) }, + [SKY1_DDR_TZC400_RCSU_0_RESET_N] = { RESET_GROUP0_RCSU, BIT(10) }, + [SKY1_DDR_TZC400_RCSU_1_RESET_N] = { RESET_GROUP0_RCSU, BIT(11) }, + [SKY1_DDR_TZC400_RCSU_2_RESET_N] = { RESET_GROUP0_RCSU, BIT(12) }, + [SKY1_DDR_TZC400_RCSU_3_RESET_N] = { RESET_GROUP0_RCSU, BIT(13) }, + [SKY1_DP0_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(14) }, + [SKY1_DP1_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(15) }, + [SKY1_DP2_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(16) }, + [SKY1_DP3_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(17) }, + [SKY1_DP4_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(18) }, + [SKY1_DPU0_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(19) }, + [SKY1_DPU1_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(20) }, + [SKY1_DPU2_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(21) }, + [SKY1_DPU3_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(22) }, + [SKY1_DPU4_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(23) }, + [SKY1_DSU_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(24) }, + [SKY1_FCH_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(25) }, + [SKY1_GICD_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(26) }, + [SKY1_GMAC_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(27) }, + [SKY1_GPU_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(28) }, + [SKY1_ISP_RCSU0_RESET_N] = { RESET_GROUP0_RCSU, BIT(29) }, + [SKY1_ISP_RCSU1_RESET_N] = { RESET_GROUP0_RCSU, BIT(30) }, + [SKY1_NI700_MMHUB_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(31) }, + + /* reset group1 for rcsu */ + [SKY1_NPU_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(0) }, + [SKY1_NI700_PCIE_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(1) }, + [SKY1_PCIE_X421_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(2) }, + [SKY1_PCIE_X8_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(3) }, + [SKY1_SF_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(4) }, + [SKY1_RCSU_SMMU_MMHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(5) }, + [SKY1_RCSU_SMMU_PCIEHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(6) }, + [SKY1_RCSU_SYSHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(7) }, + [SKY1_NI700_SMN_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(8) }, + [SKY1_NI700_SYSHUB_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(9) }, + [SKY1_RCSU_USB2_HOST0_RESET_N] = { RESET_GROUP1_RCSU, BIT(10) }, + [SKY1_RCSU_USB2_HOST1_RESET_N] = { RESET_GROUP1_RCSU, BIT(11) }, + [SKY1_RCSU_USB2_HOST2_RESET_N] = { RESET_GROUP1_RCSU, BIT(12) }, + [SKY1_RCSU_USB2_HOST3_RESET_N] = { RESET_GROUP1_RCSU, BIT(13) }, + [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N] = { RESET_GROUP1_RCSU, BIT(14) }, + [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N] = { RESET_GROUP1_RCSU, BIT(15) }, + [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N] = { RESET_GROUP1_RCSU, BIT(16) }, + [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N] = { RESET_GROUP1_RCSU, BIT(17) }, + [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N] = { RESET_GROUP1_RCSU, BIT(18) }, + [SKY1_VPU_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(19) }, +}; + +static const struct sky1_src_variant variant_sky1 = { + .signals = sky1_src_signals, + .signals_num = ARRAY_SIZE(sky1_src_signals), +}; + +enum { + FCH_SW_RST_FUNC = 0x8, + FCH_SW_RST_BUS = 0xc, + FCH_SW_XSPI = 0x10, +}; + +static const struct sky1_src_signal sky1_src_fch_signals[] = { + /* resets for fch_sw_rst_func */ + [SW_I3C0_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(0) }, + [SW_I3C0_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(1) }, + [SW_I3C1_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(2) }, + [SW_I3C1_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(3) }, + [SW_UART0_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(4) }, + [SW_UART1_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(5) }, + [SW_UART2_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(6) }, + [SW_UART3_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(7) }, + [SW_TIMER_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(20) }, + + /* resets for fch_sw_rst_bus */ + [SW_I3C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(0) }, + [SW_I3C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(1) }, + [SW_DMA_RST_AXI_N] = { FCH_SW_RST_BUS, BIT(2) }, + [SW_UART0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(4) }, + [SW_UART1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(5) }, + [SW_UART2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(6) }, + [SW_UART3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(7) }, + [SW_SPI0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(8) }, + [SW_SPI1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(9) }, + [SW_I2C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(12) }, + [SW_I2C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(13) }, + [SW_I2C2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(14) }, + [SW_I2C3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(15) }, + [SW_I2C4_RST_APB_N] = { FCH_SW_RST_BUS, BIT(16) }, + [SW_I2C5_RST_APB_N] = { FCH_SW_RST_BUS, BIT(17) }, + [SW_I2C6_RST_APB_N] = { FCH_SW_RST_BUS, BIT(18) }, + [SW_I2C7_RST_APB_N] = { FCH_SW_RST_BUS, BIT(19) }, + [SW_GPIO_RST_APB_N] = { FCH_SW_RST_BUS, BIT(21) }, + + /* resets for fch_sw_xspi */ + [SW_XSPI_REG_RST_N] = { FCH_SW_XSPI, BIT(0) }, + [SW_XSPI_SYS_RST_N] = { FCH_SW_XSPI, BIT(1) }, +}; + +static const struct sky1_src_variant variant_sky1_fch = { + .signals = sky1_src_fch_signals, + .signals_num = ARRAY_SIZE(sky1_src_fch_signals), +}; + +static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct sky1_src, rcdev); +} + +static int sky1_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct sky1_src *sky1src = to_sky1_src(rcdev); + const struct sky1_src_signal *signal = &sky1src->signals[id]; + unsigned int value = assert ? 0 : sky1src->signals[id].bit; + + return regmap_update_bits(sky1src->regmap, + signal->offset, signal->bit, value); +} + +static int sky1_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + sky1_reset_set(rcdev, id, true); + usleep_range(SKY1_RESET_SLEEP_MIN_US, + SKY1_RESET_SLEEP_MAX_US); + return 0; +} + +static int sky1_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + sky1_reset_set(rcdev, id, false); + usleep_range(SKY1_RESET_SLEEP_MIN_US, + SKY1_RESET_SLEEP_MAX_US); + return 0; +} + +static int sky1_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + sky1_reset_assert(rcdev, id); + sky1_reset_deassert(rcdev, id); + return 0; +} + +static int sky1_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + unsigned int value = 0; + struct sky1_src *sky1src = to_sky1_src(rcdev); + const struct sky1_src_signal *signal = &sky1src->signals[id]; + + regmap_read(sky1src->regmap, signal->offset, &value); + return !(value & signal->bit); +} + +static const struct reset_control_ops sky1_src_ops = { + .reset = sky1_reset, + .assert = sky1_reset_assert, + .deassert = sky1_reset_deassert, + .status = sky1_reset_status +}; + +static int sky1_reset_probe(struct platform_device *pdev) +{ + struct sky1_src *sky1src; + struct device *dev = &pdev->dev; + const struct sky1_src_variant *variant; + + sky1src = devm_kzalloc(dev, sizeof(*sky1src), GFP_KERNEL); + if (!sky1src) + return -ENOMEM; + + variant = of_device_get_match_data(dev); + + sky1src->regmap = device_node_to_regmap(dev->of_node); + if (IS_ERR(sky1src->regmap)) { + dev_err(dev, "Unable to get sky1-src regmap"); + return PTR_ERR(sky1src->regmap); + } + + sky1src->signals = variant->signals; + sky1src->rcdev.owner = THIS_MODULE; + sky1src->rcdev.nr_resets = variant->signals_num; + sky1src->rcdev.ops = &sky1_src_ops; + sky1src->rcdev.of_node = dev->of_node; + sky1src->rcdev.dev = dev; + + return devm_reset_controller_register(dev, &sky1src->rcdev); +} + +static const struct of_device_id sky1_sysreg_of_match[] = { + { .compatible = "cix,sky1-system-control", .data = &variant_sky1_fch}, + { .compatible = "cix,sky1-s5-system-control", .data = &variant_sky1}, + {}, +}; +MODULE_DEVICE_TABLE(of, sky1_sysreg_of_match); + +static struct platform_driver sky1_reset_driver = { + .probe = sky1_reset_probe, + .driver = { + .name = "cix,sky1-rst", + .of_match_table = sky1_sysreg_of_match, + }, +}; +module_platform_driver(sky1_reset_driver) + +MODULE_AUTHOR("Jerry Zhu <jerry.zhu@cixtech.com>"); +MODULE_DESCRIPTION("Cix Sky1 reset driver"); +MODULE_LICENSE("GPL"); -- 2.49.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v9 2/3] reset: add Sky1 soc reset support 2026-02-24 9:21 ` [PATCH v9 2/3] reset: add Sky1 soc reset support Gary Yang @ 2026-02-24 10:12 ` Philipp Zabel 2026-02-24 10:34 ` 回复: " Gary Yang 0 siblings, 1 reply; 10+ messages in thread From: Philipp Zabel @ 2026-02-24 10:12 UTC (permalink / raw) To: Gary Yang, robh, krzk+dt, conor+dt, peter.chen Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream On Di, 2026-02-24 at 17:21 +0800, Gary Yang wrote: > Add support for the resets on Cix's Sky1 SoC. > There are two reset controllers on Cix Sky1 Soc. One is located in S0 > domain, and the other is located in S5 domain. The second controller is not in S0 domain anymore? This change was not explained in the change log. This seems to contradict a comment in "cix,sky1-s5-system-control" -> variant_sky1 -> sky1_src_signals: /* reset group1 for s0 domain modules */ > Signed-off-by: Gary Yang <gary.yang@cixtech.com> > --- > drivers/reset/Kconfig | 7 + > drivers/reset/Makefile | 1 + > drivers/reset/reset-sky1.c | 367 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 375 insertions(+) > create mode 100644 drivers/reset/reset-sky1.c > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index 6e5d6deffa7d..0aaac1b88d02 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -291,6 +291,13 @@ config RESET_SIMPLE > - SiFive FU740 SoCs > - Sophgo SoCs > > +config RESET_SKY1 > + bool "Cix Sky1 reset controller" > + depends on OF && REGMAP_MMIO Select REGMAP_MMIO instead. > + depends on ARCH_CIX || COMPILE_TEST > + help > + This enables the reset controller for Cix Sky1. > + > config RESET_SOCFPGA > bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) > default ARM && ARCH_INTEL_SOCFPGA > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 9c3e484dfd81..0d2e1329561d 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o > obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o > obj-$(CONFIG_RESET_SCMI) += reset-scmi.o > obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o > +obj-$(CONFIG_RESET_SKY1) += reset-sky1.o > obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o > obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o > diff --git a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c > new file mode 100644 > index 000000000000..fb8a919fd3f7 > --- /dev/null > +++ b/drivers/reset/reset-sky1.c > @@ -0,0 +1,367 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * > + * CIX System Reset Controller (SRC) driver > + * > + * Author: Jerry Zhu <jerry.zhu@cixtech.com> > + */ > + > +#include <linux/delay.h> > +#include <linux/mfd/syscon.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/reset-controller.h> > + > +#include <dt-bindings/reset/cix,sky1-rst.h> > +#include <dt-bindings/reset/cix,sky1-rst-fch.h> > + > +#define SKY1_RESET_SLEEP_MIN_US 50 > +#define SKY1_RESET_SLEEP_MAX_US 100 > + > +struct sky1_src_signal { > + unsigned int offset; > + unsigned int bit; > +}; > + > +struct sky1_src_variant { > + const struct sky1_src_signal *signals; > + unsigned int signals_num; > +}; > + > +struct sky1_src { > + struct reset_controller_dev rcdev; > + const struct sky1_src_signal *signals; > + struct regmap *regmap; > +}; > + > +enum { > + CSU_PM_RESET = 0x304, > + SENSORFUSION_RESET = 0x308, > + SENSORFUSION_NOC_RESET = 0x30c, > + RESET_GROUP0_S0_DOMAIN_0 = 0x400, > + RESET_GROUP0_S0_DOMAIN_1 = 0x404, > + RESET_GROUP1_USB_PHYS = 0x408, > + RESET_GROUP1_USB_CONTROLLERS = 0x40c, > + RESET_GROUP0_RCSU = 0x800, > + RESET_GROUP1_RCSU = 0x804, > +}; > + > +static const struct sky1_src_signal sky1_src_signals[] = { > + /* reset group1 for s0 domain modules */ > + [SKY1_CSU_PM_RESET_N] = { CSU_PM_RESET, BIT(0) }, > + [SKY1_SENSORFUSION_RESET_N] = { SENSORFUSION_RESET, BIT(0) }, > + [SKY1_SENSORFUSION_NOC_RESET_N] = { SENSORFUSION_NOC_RESET, BIT(0) }, > + [SKY1_DDRC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(0) }, > + [SKY1_GIC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(1) }, > + [SKY1_CI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(2) }, > + [SKY1_SYS_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(3) }, > + [SKY1_MM_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(4) }, > + [SKY1_PCIE_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(5) }, > + [SKY1_GPU_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(6) }, > + [SKY1_NPUTOP_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(7) }, > + [SKY1_NPUCORE0_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(8) }, > + [SKY1_NPUCORE1_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(9) }, > + [SKY1_NPUCORE2_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(10) }, > + [SKY1_VPU_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(11) }, > + [SKY1_ISP_SRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(12) }, > + [SKY1_ISP_ARESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(13) }, > + [SKY1_ISP_HRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(14) }, > + [SKY1_ISP_GDCRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(15) }, > + [SKY1_DPU_RESET0_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(16) }, > + [SKY1_DPU_RESET1_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(17) }, > + [SKY1_DPU_RESET2_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(18) }, > + [SKY1_DPU_RESET3_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(19) }, > + [SKY1_DPU_RESET4_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(20) }, > + [SKY1_DP_RESET0_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(21) }, > + [SKY1_DP_RESET1_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(22) }, > + [SKY1_DP_RESET2_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(23) }, > + [SKY1_DP_RESET3_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(24) }, > + [SKY1_DP_RESET4_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(25) }, > + [SKY1_DP_PHY_RST_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(26) }, > + > + /* reset group1 for s0 domain modules */ > + [SKY1_AUDIO_HIFI5_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(0) }, > + [SKY1_AUDIO_HIFI5_NOC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(1) }, > + [SKY1_CSIDPHY_PRST0_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(2) }, > + [SKY1_CSIDPHY_CMNRST0_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(3) }, > + [SKY1_CSI0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(4) }, > + [SKY1_CSIDPHY_PRST1_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(5) }, > + [SKY1_CSIDPHY_CMNRST1_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(6) }, > + [SKY1_CSI1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(7) }, > + [SKY1_CSI2_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(8) }, > + [SKY1_CSI3_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(9) }, > + [SKY1_CSIBRDGE0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(10) }, > + [SKY1_CSIBRDGE1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(11) }, > + [SKY1_CSIBRDGE2_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(12) }, > + [SKY1_CSIBRDGE3_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(13) }, > + [SKY1_GMAC0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(14) }, > + [SKY1_GMAC1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(15) }, > + [SKY1_PCIE0_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(16) }, > + [SKY1_PCIE1_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(17) }, > + [SKY1_PCIE2_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(18) }, > + [SKY1_PCIE3_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(19) }, > + [SKY1_PCIE4_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(20) }, > + > + /* reset group1 for usb phys */ > + [SKY1_USB_DP_PHY0_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(0) }, > + [SKY1_USB_DP_PHY1_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(1) }, > + [SKY1_USB_DP_PHY2_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(2) }, > + [SKY1_USB_DP_PHY3_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(3) }, > + [SKY1_USB_DP_PHY0_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(4) }, > + [SKY1_USB_DP_PHY1_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(5) }, > + [SKY1_USB_DP_PHY2_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(6) }, > + [SKY1_USB_DP_PHY3_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(7) }, > + [SKY1_USBPHY_SS_PST_N] = { RESET_GROUP1_USB_PHYS, BIT(8) }, > + [SKY1_USBPHY_SS_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(9) }, > + [SKY1_USBPHY_HS0_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(10) }, > + [SKY1_USBPHY_HS1_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(11) }, > + [SKY1_USBPHY_HS2_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(12) }, > + [SKY1_USBPHY_HS3_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(13) }, > + [SKY1_USBPHY_HS4_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(14) }, > + [SKY1_USBPHY_HS5_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(15) }, > + [SKY1_USBPHY_HS6_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(16) }, > + [SKY1_USBPHY_HS7_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(17) }, > + [SKY1_USBPHY_HS8_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(18) }, > + [SKY1_USBPHY_HS9_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(19) }, > + > + /* reset group1 for usb controllers */ > + [SKY1_USBC_SS0_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(0) }, > + [SKY1_USBC_SS1_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(1) }, > + [SKY1_USBC_SS2_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(2) }, > + [SKY1_USBC_SS3_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(3) }, > + [SKY1_USBC_SS4_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(4) }, > + [SKY1_USBC_SS5_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(5) }, > + [SKY1_USBC_SS0_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(6) }, > + [SKY1_USBC_SS1_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(7) }, > + [SKY1_USBC_SS2_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(8) }, > + [SKY1_USBC_SS3_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(9) }, > + [SKY1_USBC_SS4_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(10) }, > + [SKY1_USBC_SS5_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(11) }, > + [SKY1_USBC_HS0_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(12) }, > + [SKY1_USBC_HS1_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(13) }, > + [SKY1_USBC_HS2_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(14) }, > + [SKY1_USBC_HS3_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(15) }, > + [SKY1_USBC_HS0_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(16) }, > + [SKY1_USBC_HS1_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(17) }, > + [SKY1_USBC_HS2_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(18) }, > + [SKY1_USBC_HS3_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(19) }, > + > + /* reset group0 for rcsu */ > + [SKY1_AUDIO_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(0) }, > + [SKY1_CI700_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(1) }, > + [SKY1_CSI_RCSU0_RESET_N] = { RESET_GROUP0_RCSU, BIT(2) }, > + [SKY1_CSI_RCSU1_RESET_N] = { RESET_GROUP0_RCSU, BIT(3) }, > + [SKY1_CSU_PM_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(4) }, > + [SKY1_DDR_BROADCAST_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(5) }, > + [SKY1_DDR_CTRL_RCSU_0_RESET_N] = { RESET_GROUP0_RCSU, BIT(6) }, > + [SKY1_DDR_CTRL_RCSU_1_RESET_N] = { RESET_GROUP0_RCSU, BIT(7) }, > + [SKY1_DDR_CTRL_RCSU_2_RESET_N] = { RESET_GROUP0_RCSU, BIT(8) }, > + [SKY1_DDR_CTRL_RCSU_3_RESET_N] = { RESET_GROUP0_RCSU, BIT(9) }, > + [SKY1_DDR_TZC400_RCSU_0_RESET_N] = { RESET_GROUP0_RCSU, BIT(10) }, > + [SKY1_DDR_TZC400_RCSU_1_RESET_N] = { RESET_GROUP0_RCSU, BIT(11) }, > + [SKY1_DDR_TZC400_RCSU_2_RESET_N] = { RESET_GROUP0_RCSU, BIT(12) }, > + [SKY1_DDR_TZC400_RCSU_3_RESET_N] = { RESET_GROUP0_RCSU, BIT(13) }, > + [SKY1_DP0_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(14) }, > + [SKY1_DP1_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(15) }, > + [SKY1_DP2_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(16) }, > + [SKY1_DP3_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(17) }, > + [SKY1_DP4_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(18) }, > + [SKY1_DPU0_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(19) }, > + [SKY1_DPU1_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(20) }, > + [SKY1_DPU2_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(21) }, > + [SKY1_DPU3_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(22) }, > + [SKY1_DPU4_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(23) }, > + [SKY1_DSU_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(24) }, > + [SKY1_FCH_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(25) }, > + [SKY1_GICD_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(26) }, > + [SKY1_GMAC_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(27) }, > + [SKY1_GPU_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(28) }, > + [SKY1_ISP_RCSU0_RESET_N] = { RESET_GROUP0_RCSU, BIT(29) }, > + [SKY1_ISP_RCSU1_RESET_N] = { RESET_GROUP0_RCSU, BIT(30) }, > + [SKY1_NI700_MMHUB_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(31) }, > + > + /* reset group1 for rcsu */ > + [SKY1_NPU_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(0) }, > + [SKY1_NI700_PCIE_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(1) }, > + [SKY1_PCIE_X421_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(2) }, > + [SKY1_PCIE_X8_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(3) }, > + [SKY1_SF_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(4) }, > + [SKY1_RCSU_SMMU_MMHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(5) }, > + [SKY1_RCSU_SMMU_PCIEHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(6) }, > + [SKY1_RCSU_SYSHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(7) }, > + [SKY1_NI700_SMN_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(8) }, > + [SKY1_NI700_SYSHUB_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(9) }, > + [SKY1_RCSU_USB2_HOST0_RESET_N] = { RESET_GROUP1_RCSU, BIT(10) }, > + [SKY1_RCSU_USB2_HOST1_RESET_N] = { RESET_GROUP1_RCSU, BIT(11) }, > + [SKY1_RCSU_USB2_HOST2_RESET_N] = { RESET_GROUP1_RCSU, BIT(12) }, > + [SKY1_RCSU_USB2_HOST3_RESET_N] = { RESET_GROUP1_RCSU, BIT(13) }, > + [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N] = { RESET_GROUP1_RCSU, BIT(14) }, > + [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N] = { RESET_GROUP1_RCSU, BIT(15) }, > + [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N] = { RESET_GROUP1_RCSU, BIT(16) }, > + [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N] = { RESET_GROUP1_RCSU, BIT(17) }, > + [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N] = { RESET_GROUP1_RCSU, BIT(18) }, > + [SKY1_VPU_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(19) }, > +}; > + > +static const struct sky1_src_variant variant_sky1 = { > + .signals = sky1_src_signals, > + .signals_num = ARRAY_SIZE(sky1_src_signals), > +}; > + > +enum { > + FCH_SW_RST_FUNC = 0x8, > + FCH_SW_RST_BUS = 0xc, > + FCH_SW_XSPI = 0x10, > +}; > + > +static const struct sky1_src_signal sky1_src_fch_signals[] = { > + /* resets for fch_sw_rst_func */ > + [SW_I3C0_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(0) }, > + [SW_I3C0_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(1) }, > + [SW_I3C1_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(2) }, > + [SW_I3C1_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(3) }, > + [SW_UART0_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(4) }, > + [SW_UART1_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(5) }, > + [SW_UART2_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(6) }, > + [SW_UART3_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(7) }, > + [SW_TIMER_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(20) }, > + > + /* resets for fch_sw_rst_bus */ > + [SW_I3C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(0) }, > + [SW_I3C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(1) }, > + [SW_DMA_RST_AXI_N] = { FCH_SW_RST_BUS, BIT(2) }, > + [SW_UART0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(4) }, > + [SW_UART1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(5) }, > + [SW_UART2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(6) }, > + [SW_UART3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(7) }, > + [SW_SPI0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(8) }, > + [SW_SPI1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(9) }, > + [SW_I2C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(12) }, > + [SW_I2C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(13) }, > + [SW_I2C2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(14) }, > + [SW_I2C3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(15) }, > + [SW_I2C4_RST_APB_N] = { FCH_SW_RST_BUS, BIT(16) }, > + [SW_I2C5_RST_APB_N] = { FCH_SW_RST_BUS, BIT(17) }, > + [SW_I2C6_RST_APB_N] = { FCH_SW_RST_BUS, BIT(18) }, > + [SW_I2C7_RST_APB_N] = { FCH_SW_RST_BUS, BIT(19) }, > + [SW_GPIO_RST_APB_N] = { FCH_SW_RST_BUS, BIT(21) }, > + > + /* resets for fch_sw_xspi */ > + [SW_XSPI_REG_RST_N] = { FCH_SW_XSPI, BIT(0) }, > + [SW_XSPI_SYS_RST_N] = { FCH_SW_XSPI, BIT(1) }, > +}; > + > +static const struct sky1_src_variant variant_sky1_fch = { > + .signals = sky1_src_fch_signals, > + .signals_num = ARRAY_SIZE(sky1_src_fch_signals), > +}; > + > +static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev) > +{ > + return container_of(rcdev, struct sky1_src, rcdev); > +} > + > +static int sky1_reset_set(struct reset_controller_dev *rcdev, > + unsigned long id, bool assert) > +{ > + struct sky1_src *sky1src = to_sky1_src(rcdev); > + const struct sky1_src_signal *signal = &sky1src->signals[id]; > + unsigned int value = assert ? 0 : sky1src->signals[id].bit; This could be shortened to: unsigned int value = assert ? 0 : signal->bit; > + > + return regmap_update_bits(sky1src->regmap, > + signal->offset, signal->bit, value); > +} > + > +static int sky1_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + sky1_reset_set(rcdev, id, true); > + usleep_range(SKY1_RESET_SLEEP_MIN_US, > + SKY1_RESET_SLEEP_MAX_US); > + return 0; > +} > + > +static int sky1_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + sky1_reset_set(rcdev, id, false); > + usleep_range(SKY1_RESET_SLEEP_MIN_US, > + SKY1_RESET_SLEEP_MAX_US); > + return 0; > +} > + > +static int sky1_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + sky1_reset_assert(rcdev, id); > + sky1_reset_deassert(rcdev, id); > + return 0; > +} > + > +static int sky1_reset_status(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + unsigned int value = 0; > + struct sky1_src *sky1src = to_sky1_src(rcdev); > + const struct sky1_src_signal *signal = &sky1src->signals[id]; > + > + regmap_read(sky1src->regmap, signal->offset, &value); > + return !(value & signal->bit); > +} > + > +static const struct reset_control_ops sky1_src_ops = { > + .reset = sky1_reset, > + .assert = sky1_reset_assert, > + .deassert = sky1_reset_deassert, > + .status = sky1_reset_status > +}; > + > +static int sky1_reset_probe(struct platform_device *pdev) > +{ > + struct sky1_src *sky1src; > + struct device *dev = &pdev->dev; > + const struct sky1_src_variant *variant; > + > + sky1src = devm_kzalloc(dev, sizeof(*sky1src), GFP_KERNEL); > + if (!sky1src) > + return -ENOMEM; > + > + variant = of_device_get_match_data(dev); > + > + sky1src->regmap = device_node_to_regmap(dev->of_node); > + if (IS_ERR(sky1src->regmap)) { > + dev_err(dev, "Unable to get sky1-src regmap"); > + return PTR_ERR(sky1src->regmap); This can be simplified with dev_err_probe(). regards Philipp ^ permalink raw reply [flat|nested] 10+ messages in thread
* 回复: [PATCH v9 2/3] reset: add Sky1 soc reset support 2026-02-24 10:12 ` Philipp Zabel @ 2026-02-24 10:34 ` Gary Yang 0 siblings, 0 replies; 10+ messages in thread From: Gary Yang @ 2026-02-24 10:34 UTC (permalink / raw) To: Philipp Zabel, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Peter Chen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cix-kernel-upstream Hi Philipp: Thanks for your comments > EXTERNAL EMAIL > > CAUTION: Suspicious Email from unusual domain. > > On Di, 2026-02-24 at 17:21 +0800, Gary Yang wrote: > > Add support for the resets on Cix's Sky1 SoC. > > There are two reset controllers on Cix Sky1 Soc. One is located in S0 > > domain, and the other is located in S5 domain. > > The second controller is not in S0 domain anymore? > This change was not explained in the change log. > > This seems to contradict a comment in > "cix,sky1-s5-system-control" -> variant_sky1 -> sky1_src_signals: > > /* reset group1 for s0 domain modules */ > I'm sorry. It makes you confuse. It doesn't have any changes. The reset controller in S0 domain is only used in S0 domain. The other one in S5 domain is both used in S0 and S5 domain. This description maybe be different from the different views. > > Signed-off-by: Gary Yang <gary.yang@cixtech.com> > > --- > > drivers/reset/Kconfig | 7 + > > drivers/reset/Makefile | 1 + > > drivers/reset/reset-sky1.c | 367 > > +++++++++++++++++++++++++++++++++++++ > > 3 files changed, 375 insertions(+) > > create mode 100644 drivers/reset/reset-sky1.c > > > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index > > 6e5d6deffa7d..0aaac1b88d02 100644 > > --- a/drivers/reset/Kconfig > > +++ b/drivers/reset/Kconfig > > @@ -291,6 +291,13 @@ config RESET_SIMPLE > > - SiFive FU740 SoCs > > - Sophgo SoCs > > > > +config RESET_SKY1 > > + bool "Cix Sky1 reset controller" > > + depends on OF && REGMAP_MMIO > > Select REGMAP_MMIO instead. > OK, we will do it next version. > > + depends on ARCH_CIX || COMPILE_TEST > > + help > > + This enables the reset controller for Cix Sky1. > > + > > config RESET_SOCFPGA > > bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM > || !ARCH_INTEL_SOCFPGA) > > default ARM && ARCH_INTEL_SOCFPGA diff --git > > a/drivers/reset/Makefile b/drivers/reset/Makefile index > > 9c3e484dfd81..0d2e1329561d 100644 > > --- a/drivers/reset/Makefile > > +++ b/drivers/reset/Makefile > > @@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += > > reset-rzg2l-usbphy-ctrl.o > > obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o > > obj-$(CONFIG_RESET_SCMI) += reset-scmi.o > > obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o > > +obj-$(CONFIG_RESET_SKY1) += reset-sky1.o > > obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o > > obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o > > obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o diff --git > > a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c new file > > mode 100644 index 000000000000..fb8a919fd3f7 > > --- /dev/null > > +++ b/drivers/reset/reset-sky1.c > > @@ -0,0 +1,367 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * > > + * CIX System Reset Controller (SRC) driver > > + * > > + * Author: Jerry Zhu <jerry.zhu@cixtech.com> */ > > + > > +#include <linux/delay.h> > > +#include <linux/mfd/syscon.h> > > +#include <linux/module.h> > > +#include <linux/of.h> > > +#include <linux/platform_device.h> > > +#include <linux/regmap.h> > > +#include <linux/reset-controller.h> > > + > > +#include <dt-bindings/reset/cix,sky1-rst.h> > > +#include <dt-bindings/reset/cix,sky1-rst-fch.h> > > + > > +#define SKY1_RESET_SLEEP_MIN_US 50 > > +#define SKY1_RESET_SLEEP_MAX_US 100 > > + > > +struct sky1_src_signal { > > + unsigned int offset; > > + unsigned int bit; > > +}; > > + > > +struct sky1_src_variant { > > + const struct sky1_src_signal *signals; > > + unsigned int signals_num; > > +}; > > + > > +struct sky1_src { > > + struct reset_controller_dev rcdev; > > + const struct sky1_src_signal *signals; > > + struct regmap *regmap; > > +}; > > + > > +enum { > > + CSU_PM_RESET = 0x304, > > + SENSORFUSION_RESET = 0x308, > > + SENSORFUSION_NOC_RESET = 0x30c, > > + RESET_GROUP0_S0_DOMAIN_0 = 0x400, > > + RESET_GROUP0_S0_DOMAIN_1 = 0x404, > > + RESET_GROUP1_USB_PHYS = 0x408, > > + RESET_GROUP1_USB_CONTROLLERS = 0x40c, > > + RESET_GROUP0_RCSU = 0x800, > > + RESET_GROUP1_RCSU = 0x804, > > +}; > > + > > +static const struct sky1_src_signal sky1_src_signals[] = { > > + /* reset group1 for s0 domain modules */ > > + [SKY1_CSU_PM_RESET_N] = { CSU_PM_RESET, BIT(0) }, > > + [SKY1_SENSORFUSION_RESET_N] = { SENSORFUSION_RESET, > BIT(0) }, > > + [SKY1_SENSORFUSION_NOC_RESET_N] = > { SENSORFUSION_NOC_RESET, BIT(0) }, > > + [SKY1_DDRC_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(0) }, > > + [SKY1_GIC_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(1) }, > > + [SKY1_CI700_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(2) }, > > + [SKY1_SYS_NI700_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(3) }, > > + [SKY1_MM_NI700_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(4) }, > > + [SKY1_PCIE_NI700_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(5) }, > > + [SKY1_GPU_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(6) }, > > + [SKY1_NPUTOP_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(7) }, > > + [SKY1_NPUCORE0_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(8) }, > > + [SKY1_NPUCORE1_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(9) }, > > + [SKY1_NPUCORE2_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(10) }, > > + [SKY1_VPU_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(11) }, > > + [SKY1_ISP_SRESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(12) }, > > + [SKY1_ISP_ARESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(13) }, > > + [SKY1_ISP_HRESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(14) }, > > + [SKY1_ISP_GDCRESET_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(15) }, > > + [SKY1_DPU_RESET0_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(16) }, > > + [SKY1_DPU_RESET1_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(17) }, > > + [SKY1_DPU_RESET2_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(18) }, > > + [SKY1_DPU_RESET3_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(19) }, > > + [SKY1_DPU_RESET4_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(20) }, > > + [SKY1_DP_RESET0_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(21) }, > > + [SKY1_DP_RESET1_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(22) }, > > + [SKY1_DP_RESET2_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(23) }, > > + [SKY1_DP_RESET3_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(24) }, > > + [SKY1_DP_RESET4_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(25) }, > > + [SKY1_DP_PHY_RST_N] = > { RESET_GROUP0_S0_DOMAIN_0, BIT(26) }, > > + > > + /* reset group1 for s0 domain modules */ > > + [SKY1_AUDIO_HIFI5_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(0) }, > > + [SKY1_AUDIO_HIFI5_NOC_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(1) }, > > + [SKY1_CSIDPHY_PRST0_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(2) }, > > + [SKY1_CSIDPHY_CMNRST0_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(3) }, > > + [SKY1_CSI0_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(4) }, > > + [SKY1_CSIDPHY_PRST1_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(5) }, > > + [SKY1_CSIDPHY_CMNRST1_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(6) }, > > + [SKY1_CSI1_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(7) }, > > + [SKY1_CSI2_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(8) }, > > + [SKY1_CSI3_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(9) }, > > + [SKY1_CSIBRDGE0_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(10) }, > > + [SKY1_CSIBRDGE1_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(11) }, > > + [SKY1_CSIBRDGE2_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(12) }, > > + [SKY1_CSIBRDGE3_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(13) }, > > + [SKY1_GMAC0_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(14) }, > > + [SKY1_GMAC1_RST_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(15) }, > > + [SKY1_PCIE0_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(16) }, > > + [SKY1_PCIE1_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(17) }, > > + [SKY1_PCIE2_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(18) }, > > + [SKY1_PCIE3_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(19) }, > > + [SKY1_PCIE4_RESET_N] = > { RESET_GROUP0_S0_DOMAIN_1, BIT(20) }, > > + > > + /* reset group1 for usb phys */ > > + [SKY1_USB_DP_PHY0_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(0) }, > > + [SKY1_USB_DP_PHY1_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(1) }, > > + [SKY1_USB_DP_PHY2_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(2) }, > > + [SKY1_USB_DP_PHY3_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(3) }, > > + [SKY1_USB_DP_PHY0_RST_N] = > { RESET_GROUP1_USB_PHYS, BIT(4) }, > > + [SKY1_USB_DP_PHY1_RST_N] = > { RESET_GROUP1_USB_PHYS, BIT(5) }, > > + [SKY1_USB_DP_PHY2_RST_N] = > { RESET_GROUP1_USB_PHYS, BIT(6) }, > > + [SKY1_USB_DP_PHY3_RST_N] = > { RESET_GROUP1_USB_PHYS, BIT(7) }, > > + [SKY1_USBPHY_SS_PST_N] = > { RESET_GROUP1_USB_PHYS, BIT(8) }, > > + [SKY1_USBPHY_SS_RST_N] = > { RESET_GROUP1_USB_PHYS, BIT(9) }, > > + [SKY1_USBPHY_HS0_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(10) }, > > + [SKY1_USBPHY_HS1_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(11) }, > > + [SKY1_USBPHY_HS2_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(12) }, > > + [SKY1_USBPHY_HS3_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(13) }, > > + [SKY1_USBPHY_HS4_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(14) }, > > + [SKY1_USBPHY_HS5_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(15) }, > > + [SKY1_USBPHY_HS6_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(16) }, > > + [SKY1_USBPHY_HS7_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(17) }, > > + [SKY1_USBPHY_HS8_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(18) }, > > + [SKY1_USBPHY_HS9_PRST_N] = > { RESET_GROUP1_USB_PHYS, BIT(19) }, > > + > > + /* reset group1 for usb controllers */ > > + [SKY1_USBC_SS0_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(0) }, > > + [SKY1_USBC_SS1_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(1) }, > > + [SKY1_USBC_SS2_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(2) }, > > + [SKY1_USBC_SS3_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(3) }, > > + [SKY1_USBC_SS4_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(4) }, > > + [SKY1_USBC_SS5_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(5) }, > > + [SKY1_USBC_SS0_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(6) }, > > + [SKY1_USBC_SS1_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(7) }, > > + [SKY1_USBC_SS2_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(8) }, > > + [SKY1_USBC_SS3_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(9) }, > > + [SKY1_USBC_SS4_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(10) }, > > + [SKY1_USBC_SS5_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(11) }, > > + [SKY1_USBC_HS0_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(12) }, > > + [SKY1_USBC_HS1_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(13) }, > > + [SKY1_USBC_HS2_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(14) }, > > + [SKY1_USBC_HS3_PRST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(15) }, > > + [SKY1_USBC_HS0_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(16) }, > > + [SKY1_USBC_HS1_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(17) }, > > + [SKY1_USBC_HS2_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(18) }, > > + [SKY1_USBC_HS3_RST_N] = > { RESET_GROUP1_USB_CONTROLLERS, BIT(19) }, > > + > > + /* reset group0 for rcsu */ > > + [SKY1_AUDIO_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(0) }, > > + [SKY1_CI700_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(1) }, > > + [SKY1_CSI_RCSU0_RESET_N] = > { RESET_GROUP0_RCSU, BIT(2) }, > > + [SKY1_CSI_RCSU1_RESET_N] = > { RESET_GROUP0_RCSU, BIT(3) }, > > + [SKY1_CSU_PM_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(4) }, > > + [SKY1_DDR_BROADCAST_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(5) }, > > + [SKY1_DDR_CTRL_RCSU_0_RESET_N] = > { RESET_GROUP0_RCSU, BIT(6) }, > > + [SKY1_DDR_CTRL_RCSU_1_RESET_N] = > { RESET_GROUP0_RCSU, BIT(7) }, > > + [SKY1_DDR_CTRL_RCSU_2_RESET_N] = > { RESET_GROUP0_RCSU, BIT(8) }, > > + [SKY1_DDR_CTRL_RCSU_3_RESET_N] = > { RESET_GROUP0_RCSU, BIT(9) }, > > + [SKY1_DDR_TZC400_RCSU_0_RESET_N] = > { RESET_GROUP0_RCSU, BIT(10) }, > > + [SKY1_DDR_TZC400_RCSU_1_RESET_N] = > { RESET_GROUP0_RCSU, BIT(11) }, > > + [SKY1_DDR_TZC400_RCSU_2_RESET_N] = > { RESET_GROUP0_RCSU, BIT(12) }, > > + [SKY1_DDR_TZC400_RCSU_3_RESET_N] = > { RESET_GROUP0_RCSU, BIT(13) }, > > + [SKY1_DP0_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(14) }, > > + [SKY1_DP1_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(15) }, > > + [SKY1_DP2_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(16) }, > > + [SKY1_DP3_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(17) }, > > + [SKY1_DP4_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(18) }, > > + [SKY1_DPU0_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(19) }, > > + [SKY1_DPU1_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(20) }, > > + [SKY1_DPU2_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(21) }, > > + [SKY1_DPU3_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(22) }, > > + [SKY1_DPU4_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(23) }, > > + [SKY1_DSU_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(24) }, > > + [SKY1_FCH_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(25) }, > > + [SKY1_GICD_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(26) }, > > + [SKY1_GMAC_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(27) }, > > + [SKY1_GPU_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(28) }, > > + [SKY1_ISP_RCSU0_RESET_N] = > { RESET_GROUP0_RCSU, BIT(29) }, > > + [SKY1_ISP_RCSU1_RESET_N] = > { RESET_GROUP0_RCSU, BIT(30) }, > > + [SKY1_NI700_MMHUB_RCSU_RESET_N] = > { RESET_GROUP0_RCSU, BIT(31) }, > > + > > + /* reset group1 for rcsu */ > > + [SKY1_NPU_RCSU_RESET_N] = > { RESET_GROUP1_RCSU, BIT(0) }, > > + [SKY1_NI700_PCIE_RCSU_RESET_N] = > { RESET_GROUP1_RCSU, BIT(1) }, > > + [SKY1_PCIE_X421_RCSU_RESET_N] = > { RESET_GROUP1_RCSU, BIT(2) }, > > + [SKY1_PCIE_X8_RCSU_RESET_N] = > { RESET_GROUP1_RCSU, BIT(3) }, > > + [SKY1_SF_RCSU_RESET_N] = > { RESET_GROUP1_RCSU, BIT(4) }, > > + [SKY1_RCSU_SMMU_MMHUB_RESET_N] = > { RESET_GROUP1_RCSU, BIT(5) }, > > + [SKY1_RCSU_SMMU_PCIEHUB_RESET_N] = > { RESET_GROUP1_RCSU, BIT(6) }, > > + [SKY1_RCSU_SYSHUB_RESET_N] = > { RESET_GROUP1_RCSU, BIT(7) }, > > + [SKY1_NI700_SMN_RCSU_RESET_N] = > { RESET_GROUP1_RCSU, BIT(8) }, > > + [SKY1_NI700_SYSHUB_RCSU_RESET_N] = > { RESET_GROUP1_RCSU, BIT(9) }, > > + [SKY1_RCSU_USB2_HOST0_RESET_N] = > { RESET_GROUP1_RCSU, BIT(10) }, > > + [SKY1_RCSU_USB2_HOST1_RESET_N] = > { RESET_GROUP1_RCSU, BIT(11) }, > > + [SKY1_RCSU_USB2_HOST2_RESET_N] = > { RESET_GROUP1_RCSU, BIT(12) }, > > + [SKY1_RCSU_USB2_HOST3_RESET_N] = > { RESET_GROUP1_RCSU, BIT(13) }, > > + [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N] = > { RESET_GROUP1_RCSU, BIT(14) }, > > + [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N] = > { RESET_GROUP1_RCSU, BIT(15) }, > > + [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N] = > { RESET_GROUP1_RCSU, BIT(16) }, > > + [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N] = > { RESET_GROUP1_RCSU, BIT(17) }, > > + [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N] = > { RESET_GROUP1_RCSU, BIT(18) }, > > + [SKY1_VPU_RCSU_RESET_N] = > { RESET_GROUP1_RCSU, BIT(19) }, > > +}; > > + > > +static const struct sky1_src_variant variant_sky1 = { > > + .signals = sky1_src_signals, > > + .signals_num = ARRAY_SIZE(sky1_src_signals), }; > > + > > +enum { > > + FCH_SW_RST_FUNC = 0x8, > > + FCH_SW_RST_BUS = 0xc, > > + FCH_SW_XSPI = 0x10, > > +}; > > + > > +static const struct sky1_src_signal sky1_src_fch_signals[] = { > > + /* resets for fch_sw_rst_func */ > > + [SW_I3C0_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(0) }, > > + [SW_I3C0_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(1) }, > > + [SW_I3C1_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(2) }, > > + [SW_I3C1_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(3) }, > > + [SW_UART0_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(4) }, > > + [SW_UART1_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(5) }, > > + [SW_UART2_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(6) }, > > + [SW_UART3_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(7) }, > > + [SW_TIMER_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(20) }, > > + > > + /* resets for fch_sw_rst_bus */ > > + [SW_I3C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(0) }, > > + [SW_I3C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(1) }, > > + [SW_DMA_RST_AXI_N] = { FCH_SW_RST_BUS, BIT(2) }, > > + [SW_UART0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(4) }, > > + [SW_UART1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(5) }, > > + [SW_UART2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(6) }, > > + [SW_UART3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(7) }, > > + [SW_SPI0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(8) }, > > + [SW_SPI1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(9) }, > > + [SW_I2C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(12) }, > > + [SW_I2C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(13) }, > > + [SW_I2C2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(14) }, > > + [SW_I2C3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(15) }, > > + [SW_I2C4_RST_APB_N] = { FCH_SW_RST_BUS, BIT(16) }, > > + [SW_I2C5_RST_APB_N] = { FCH_SW_RST_BUS, BIT(17) }, > > + [SW_I2C6_RST_APB_N] = { FCH_SW_RST_BUS, BIT(18) }, > > + [SW_I2C7_RST_APB_N] = { FCH_SW_RST_BUS, BIT(19) }, > > + [SW_GPIO_RST_APB_N] = { FCH_SW_RST_BUS, BIT(21) }, > > + > > + /* resets for fch_sw_xspi */ > > + [SW_XSPI_REG_RST_N] = { FCH_SW_XSPI, BIT(0) }, > > + [SW_XSPI_SYS_RST_N] = { FCH_SW_XSPI, BIT(1) }, > > +}; > > + > > +static const struct sky1_src_variant variant_sky1_fch = { > > + .signals = sky1_src_fch_signals, > > + .signals_num = ARRAY_SIZE(sky1_src_fch_signals), }; > > + > > +static struct sky1_src *to_sky1_src(struct reset_controller_dev > > +*rcdev) { > > + return container_of(rcdev, struct sky1_src, rcdev); } > > + > > +static int sky1_reset_set(struct reset_controller_dev *rcdev, > > + unsigned long id, bool assert) { > > + struct sky1_src *sky1src = to_sky1_src(rcdev); > > + const struct sky1_src_signal *signal = &sky1src->signals[id]; > > + unsigned int value = assert ? 0 : sky1src->signals[id].bit; > > This could be shortened to: > > unsigned int value = assert ? 0 : signal->bit; > Yes, you're right. We will do it next version > > + > > + return regmap_update_bits(sky1src->regmap, > > + signal->offset, signal->bit, value); } > > + > > +static int sky1_reset_assert(struct reset_controller_dev *rcdev, > > + unsigned long id) { > > + sky1_reset_set(rcdev, id, true); > > + usleep_range(SKY1_RESET_SLEEP_MIN_US, > > + SKY1_RESET_SLEEP_MAX_US); > > + return 0; > > +} > > + > > +static int sky1_reset_deassert(struct reset_controller_dev *rcdev, > > + unsigned long id) { > > + sky1_reset_set(rcdev, id, false); > > + usleep_range(SKY1_RESET_SLEEP_MIN_US, > > + SKY1_RESET_SLEEP_MAX_US); > > + return 0; > > +} > > + > > +static int sky1_reset(struct reset_controller_dev *rcdev, > > + unsigned long id) > > +{ > > + sky1_reset_assert(rcdev, id); > > + sky1_reset_deassert(rcdev, id); > > + return 0; > > +} > > + > > +static int sky1_reset_status(struct reset_controller_dev *rcdev, > > + unsigned long id) { > > + unsigned int value = 0; > > + struct sky1_src *sky1src = to_sky1_src(rcdev); > > + const struct sky1_src_signal *signal = &sky1src->signals[id]; > > + > > + regmap_read(sky1src->regmap, signal->offset, &value); > > + return !(value & signal->bit); > > +} > > + > > +static const struct reset_control_ops sky1_src_ops = { > > + .reset = sky1_reset, > > + .assert = sky1_reset_assert, > > + .deassert = sky1_reset_deassert, > > + .status = sky1_reset_status > > +}; > > + > > +static int sky1_reset_probe(struct platform_device *pdev) { > > + struct sky1_src *sky1src; > > + struct device *dev = &pdev->dev; > > + const struct sky1_src_variant *variant; > > + > > + sky1src = devm_kzalloc(dev, sizeof(*sky1src), GFP_KERNEL); > > + if (!sky1src) > > + return -ENOMEM; > > + > > + variant = of_device_get_match_data(dev); > > + > > + sky1src->regmap = device_node_to_regmap(dev->of_node); > > + if (IS_ERR(sky1src->regmap)) { > > + dev_err(dev, "Unable to get sky1-src regmap"); > > + return PTR_ERR(sky1src->regmap); > > This can be simplified with dev_err_probe(). > The same If miss any information, please remind me. Thanks Best Regards Gary > regards > Philipp ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v9 3/3] arm64: dts: cix: add support for cix sky1 resets 2026-02-24 9:21 [PATCH v9 0/3] Add support for Cix Sky1 resets Gary Yang 2026-02-24 9:21 ` [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC Gary Yang 2026-02-24 9:21 ` [PATCH v9 2/3] reset: add Sky1 soc reset support Gary Yang @ 2026-02-24 9:21 ` Gary Yang 2 siblings, 0 replies; 10+ messages in thread From: Gary Yang @ 2026-02-24 9:21 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, p.zabel, peter.chen Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream, Gary Yang There are two reset conctrollers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. Signed-off-by: Gary Yang <gary.yang@cixtech.com> --- arch/arm64/boot/dts/cix/sky1.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 64b76905cbff..a28b877cced2 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -348,6 +348,12 @@ i3c1: i3c@4100000 { status = "disabled"; }; + syscon: syscon@4160000 { + compatible = "cix,sky1-system-control", "syscon"; + reg = <0x0 0x4160000 0x0 0x100>; + #reset-cells = <1>; + }; + iomuxc: pinctrl@4170000 { compatible = "cix,sky1-pinctrl"; reg = <0x0 0x04170000 0x0 0x1000>; @@ -568,6 +574,12 @@ ppi_partition1: interrupt-partition-1 { }; }; + s5_syscon: syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x0 0x16000000 0x0 0x1000>; + #reset-cells = <1>; + }; + iomuxc_s5: pinctrl@16007000 { compatible = "cix,sky1-pinctrl-s5"; reg = <0x0 0x16007000 0x0 0x1000>; -- 2.49.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2026-02-25 11:46 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-02-24 9:21 [PATCH v9 0/3] Add support for Cix Sky1 resets Gary Yang 2026-02-24 9:21 ` [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC Gary Yang 2026-02-25 10:29 ` Krzysztof Kozlowski 2026-02-25 10:30 ` Krzysztof Kozlowski 2026-02-25 11:15 ` 回复: " Gary Yang 2026-02-25 11:46 ` Krzysztof Kozlowski 2026-02-24 9:21 ` [PATCH v9 2/3] reset: add Sky1 soc reset support Gary Yang 2026-02-24 10:12 ` Philipp Zabel 2026-02-24 10:34 ` 回复: " Gary Yang 2026-02-24 9:21 ` [PATCH v9 3/3] arm64: dts: cix: add support for cix sky1 resets Gary Yang
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox