[PATCH 0/2] ARM: dts: Add CPU clock and OPP table for i.MX7ULP

[PATCH 0/2] ARM: dts: Add CPU clock and OPP table for i.MX7ULP

[Peng Fan (OSS)]

Patch 1 is a binding update to add missing #clock-cells, otherwise
there is CHECK_DTBS warning.
clock-controller@40410000 (fsl,imx7ulp-smc1): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'

And the clock will be used for cpufreq as done in patch 2.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Peng Fan (2):
      dt-bindings: fsl: fsl,imx7ulp-smc1: Add #clock-cells
      ARM: dts: imx7ulp: Add CPU clock and OPP table support

 .../bindings/arm/freescale/fsl,imx7ulp-pm.yaml     |  5 ++++
 arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi             | 28 ++++++++++++++++++++++
 2 files changed, 33 insertions(+)
---
base-commit: 3ef088b0c5772a6f75634e54aa34f5fc0a2c041c
change-id: 20260226-imx7ulp-c48516ee22b4

Best regards,
-- 
Peng Fan <peng.fan@nxp.com>

[PATCH 1/2] dt-bindings: fsl: fsl,imx7ulp-smc1: Add #clock-cells

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add missing #clock-cells to make it work as a clock controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
index 9d377e193c123c7de0ec4db4d4a649ed966b2d9a..7ad470260c0d08bd1e7146ef49e5f60dd6c6d4d7 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
@@ -28,6 +28,9 @@ properties:
   reg:
     maxItems: 1
 
+  '#clock-cells':
+    const: 1
+
   clocks:
     maxItems: 2
 
@@ -39,6 +42,7 @@ properties:
 required:
   - compatible
   - reg
+  - '#clock-cells'
 
 additionalProperties: false
 
@@ -47,4 +51,5 @@ examples:
     smc1@40410000 {
         compatible = "fsl,imx7ulp-smc1";
         reg = <0x40410000 0x1000>;
+        #clock-cells = <1>;
     };

-- 
2.37.1

Re: [PATCH 1/2] dt-bindings: fsl: fsl,imx7ulp-smc1: Add #clock-cells

[Conor Dooley]

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On Thu, Feb 26, 2026 at 07:04:15PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add missing #clock-cells to make it work as a clock controller.

Yes, that is what adding #clock-cells would do, but why is it correct to
do? That's what your commit message needs to explain.

> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
> index 9d377e193c123c7de0ec4db4d4a649ed966b2d9a..7ad470260c0d08bd1e7146ef49e5f60dd6c6d4d7 100644
> --- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
> +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
> @@ -28,6 +28,9 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  '#clock-cells':
> +    const: 1
> +
>    clocks:
>      maxItems: 2
>  
> @@ -39,6 +42,7 @@ properties:
>  required:
>    - compatible
>    - reg
> +  - '#clock-cells'
>  
>  additionalProperties: false
>  
> @@ -47,4 +51,5 @@ examples:
>      smc1@40410000 {
>          compatible = "fsl,imx7ulp-smc1";
>          reg = <0x40410000 0x1000>;
> +        #clock-cells = <1>;
>      };
> 
> -- 
> 2.37.1
> 

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RE: [PATCH 1/2] dt-bindings: fsl: fsl,imx7ulp-smc1: Add #clock-cells

[Peng Fan]

Hi Conor,

> Subject: Re: [PATCH 1/2] dt-bindings: fsl: fsl,imx7ulp-smc1: Add #clock-
> cells
> 
> On Thu, Feb 26, 2026 at 07:04:15PM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Add missing #clock-cells to make it work as a clock controller.
> 
> Yes, that is what adding #clock-cells would do, but why is it correct to
> do? That's what your commit message needs to explain.

Without #clock-cells, there is CHECK_DTBS error, #clock-cells
was added in imx7ulp.dtsi, but missed in dt-bindings.

smc1 supports run mode control
00b - Normal Run mode (RUN)
01b - Reserved
10b - Very-Low-Power Run mode (VLPR)
11b - High Speed Run mode (HSRUN)

This is taken as cpu clock settings. When set this registers,
the cpu will be configured to run as specified frequencies as written
in patch 2(OPP table).

I will update commit msg in V2.

Thanks,
Peng.

> 
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-
> pm.yaml |
> > 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-
> pm.yaml
> > b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-
> pm.yaml
> > index
> >
> 9d377e193c123c7de0ec4db4d4a649ed966b2d9a..7ad470260c0d08b
> d1e7146ef49e5
> > f60dd6c6d4d7 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-
> pm.yaml
> > +++
> b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.y
> > +++ aml
> > @@ -28,6 +28,9 @@ properties:
> >    reg:
> >      maxItems: 1
> >
> > +  '#clock-cells':
> > +    const: 1
> > +
> >    clocks:
> >      maxItems: 2
> >
> > @@ -39,6 +42,7 @@ properties:
> >  required:
> >    - compatible
> >    - reg
> > +  - '#clock-cells'
> >
> >  additionalProperties: false
> >
> > @@ -47,4 +51,5 @@ examples:
> >      smc1@40410000 {
> >          compatible = "fsl,imx7ulp-smc1";
> >          reg = <0x40410000 0x1000>;
> > +        #clock-cells = <1>;
> >      };
> >
> > --
> > 2.37.1
> >

[PATCH 2/2] ARM: dts: imx7ulp: Add CPU clock and OPP table support

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add missing CPU clock definitions and operating-points-v2 table for the
Cortex-A7 on i.MX7ULP to enable proper CPU frequency scaling and
integration with the cpufreq/OPP frameworks.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
index 880b9a4f32b0846a773dbf9ad30715c84ac2fda6..1355feda1aa72d88dcf56033dfdeaae631c108f8 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
@@ -41,6 +41,34 @@ cpu0: cpu@f00 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0xf00>;
+			clocks = <&smc1 IMX7ULP_CLK_ARM>,
+				 <&scg1 IMX7ULP_CLK_CORE>,
+				 <&scg1 IMX7ULP_CLK_SYS_SEL>,
+				 <&scg1 IMX7ULP_CLK_HSRUN_CORE>,
+				 <&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>,
+				 <&scg1 IMX7ULP_CLK_FIRC>;
+			clock-names = "arm", "core", "scs_sel",
+				      "hsrun_core", "hsrun_scs_sel",
+				      "firc";
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+	};
+
+	cpu0_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-500210000 {
+			opp-hz = /bits/ 64 <500210000>;
+			opp-microvolt = <1025000>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+
+		opp-720000000 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <1125000>;
+			clock-latency-ns = <150000>;
 		};
 	};
 

-- 
2.37.1