* [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37
@ 2026-02-26 4:52 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 02/10] perf vendor events intel: Update arrowlake events from 1.14 to 1.16 Ian Rogers
` (9 more replies)
0 siblings, 10 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:52 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/632936400cfc5978c7b4519c865c137de523bfdd
https://github.com/intel/perfmon/commit/a96d6bf4b50d6ce31e2ffd0be8d13022d07ae319
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/alderlake/cache.json | 27 +++-----
.../arch/x86/alderlake/frontend.json | 18 +++++
.../arch/x86/alderlake/pipeline.json | 66 +++++++++++++++++--
.../pmu-events/arch/x86/alderlaken/cache.json | 27 +++-----
.../arch/x86/alderlaken/pipeline.json | 60 +++++++++++++++--
tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +-
6 files changed, 152 insertions(+), 50 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/cache.json b/tools/perf/pmu-events/arch/x86/alderlake/cache.json
index be15a7f83717..5d0d824f3e7e 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/cache.json
@@ -876,105 +876,97 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
@@ -1030,12 +1022,11 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
+ "BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
- "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x6",
"Unit": "cpu_atom"
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json
index ff3b30c2619a..11fc853f2d0b 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json
@@ -327,6 +327,24 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_INUSE",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_INUSE",
+ "SampleAfterValue": "200003",
+ "UMask": "0x10",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_ISB",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_ISB",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
index 57a8c78cdc49..80cad3c49d20 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
@@ -244,6 +244,15 @@
"UMask": "0xfb",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of near indirect JMP branch instructions retired.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.INDIRECT_JMP",
+ "SampleAfterValue": "200003",
+ "UMask": "0xef",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL",
"Counter": "0,1,2,3,4,5",
@@ -464,6 +473,15 @@
"UMask": "0x2",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of mispredicted near indirect JMP branch instructions retired.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.INDIRECT_JMP",
+ "SampleAfterValue": "200003",
+ "UMask": "0xef",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL",
"Counter": "0,1,2,3,4,5",
@@ -573,7 +591,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
@@ -582,7 +600,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
@@ -651,7 +669,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles at TSC frequency.",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
@@ -689,7 +707,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
@@ -707,7 +725,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
@@ -875,7 +893,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
+ "BriefDescription": "Fixed Counter: Counts the total number of instructions retired.",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. Available PDIST counters: 32",
@@ -1273,6 +1291,42 @@
"UMask": "0x20",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.CL_INST",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of LFENCE instructions retired.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.LFENCE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of misses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x11",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json
index 76a841675337..1f97a4dc6fb1 100644
--- a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json
+++ b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json
@@ -246,98 +246,90 @@
"UMask": "0x82"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
- "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
@@ -387,12 +379,11 @@
"UMask": "0x12"
},
{
- "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
+ "BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
- "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json
index d650cbd48c1f..a13851071624 100644
--- a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json
@@ -108,6 +108,14 @@
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
+ {
+ "BriefDescription": "Counts the number of near indirect JMP branch instructions retired.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.INDIRECT_JMP",
+ "SampleAfterValue": "200003",
+ "UMask": "0xef"
+ },
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL",
"Counter": "0,1,2,3,4,5",
@@ -225,6 +233,14 @@
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
+ {
+ "BriefDescription": "Counts the number of mispredicted near indirect JMP branch instructions retired.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.INDIRECT_JMP",
+ "SampleAfterValue": "200003",
+ "UMask": "0xef"
+ },
{
"BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL",
"Counter": "0,1,2,3,4,5",
@@ -278,7 +294,7 @@
"UMask": "0xfe"
},
{
- "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
@@ -286,7 +302,7 @@
"UMask": "0x2"
},
{
- "BriefDescription": "Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
@@ -303,7 +319,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles at TSC frequency.",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
@@ -320,7 +336,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
@@ -328,7 +344,7 @@
"UMask": "0x2"
},
{
- "BriefDescription": "Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
@@ -336,7 +352,7 @@
"SampleAfterValue": "2000003"
},
{
- "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
+ "BriefDescription": "Fixed Counter: Counts the total number of instructions retired.",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. Available PDIST counters: 32",
@@ -426,6 +442,38 @@
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.CL_INST",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff"
+ },
+ {
+ "BriefDescription": "Counts the number of LFENCE instructions retired.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.LFENCE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "Counts the number of misses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x11"
+ },
{
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)",
"Counter": "0,1,2,3,4,5",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 149bbe7abaf5..9370722dc564 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -1,6 +1,6 @@
Family-model,Version,Filename,EventType
-GenuineIntel-6-(97|9A|B7|BA|BF),v1.35,alderlake,core
-GenuineIntel-6-BE,v1.35,alderlaken,core
+GenuineIntel-6-(97|9A|B7|BA|BF),v1.37,alderlake,core
+GenuineIntel-6-BE,v1.37,alderlaken,core
GenuineIntel-6-C[56],v1.14,arrowlake,core
GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
GenuineIntel-6-(3D|47),v30,broadwell,core
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 02/10] perf vendor events intel: Update arrowlake events from 1.14 to 1.16
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
@ 2026-02-26 4:52 ` Ian Rogers
2026-02-26 4:52 ` [PATCH v1 03/10] perf vendor events intel: Update emeraldrapid events from 1.20 to 1.21 Ian Rogers
` (8 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:52 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/f0267f720eeab3b5416886c9e0e132fafcb38bbd
https://github.com/intel/perfmon/commit/d40cfa317e567fb5e8f6cbd92c81feeb7e6bd3dd
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/arrowlake/cache.json | 103 ++++++++++++++----
.../arch/x86/arrowlake/frontend.json | 18 +++
.../arch/x86/arrowlake/pipeline.json | 40 +++++--
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
4 files changed, 135 insertions(+), 28 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/cache.json b/tools/perf/pmu-events/arch/x86/arrowlake/cache.json
index fba4a0672f6c..4c3aa1fab5a8 100644
--- a/tools/perf/pmu-events/arch/x86/arrowlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/arrowlake/cache.json
@@ -628,6 +628,15 @@
"UMask": "0x7f",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x35",
+ "EventName": "MEM_BOUND_STALLS_IFETCH.ALL",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x7f",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -731,6 +740,24 @@
"UMask": "0x6",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles that the core is stalled due to a demand load miss which hit in the LLC, no snoop was required, and the LLC provided data",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -749,6 +776,24 @@
"UMask": "0x78",
"Unit": "cpu_lowpower"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1081,6 +1126,15 @@
"UMask": "0x20",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of retired load ops with an unknown source",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xd4",
+ "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LOCAL_DRAM",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1181,6 +1235,15 @@
"UMask": "0x1c",
"Unit": "cpu_lowpower"
},
+ {
+ "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xd1",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT_NO_SNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1331,7 +1394,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1343,7 +1406,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1355,7 +1418,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1367,7 +1430,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1379,7 +1442,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1391,7 +1454,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1403,7 +1466,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1415,7 +1478,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1427,7 +1490,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1439,7 +1502,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1451,7 +1514,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1463,7 +1526,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1475,7 +1538,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1487,7 +1550,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1499,7 +1562,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1511,7 +1574,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1523,7 +1586,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1535,7 +1598,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1707,7 +1770,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
+ "BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1717,7 +1780,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
+ "BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/frontend.json b/tools/perf/pmu-events/arch/x86/arrowlake/frontend.json
index a15de050a76c..21f00eafa98a 100644
--- a/tools/perf/pmu-events/arch/x86/arrowlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/arrowlake/frontend.json
@@ -627,6 +627,24 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full",
+ "Counter": "0,1,2,3,4,5,6,7,8,9",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_INUSE",
+ "SampleAfterValue": "200003",
+ "UMask": "0x10",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full",
+ "Counter": "0,1,2,3,4,5,6,7,8,9",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_ISB",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3,4,5,6,7,8,9",
diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json b/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json
index 805616052925..fb973c75be57 100644
--- a/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json
@@ -822,7 +822,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
@@ -839,7 +839,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
@@ -909,7 +909,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
@@ -947,7 +947,7 @@
"Unit": "cpu_lowpower"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
@@ -964,7 +964,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
@@ -1134,10 +1134,10 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
+ "BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
- "PublicDescription": "Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32",
+ "PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
"SampleAfterValue": "2000003",
"UMask": "0x1",
"Unit": "cpu_lowpower"
@@ -1607,6 +1607,14 @@
"SampleAfterValue": "20003",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc3",
+ "EventName": "MACHINE_CLEARS.ANY",
+ "SampleAfterValue": "20003",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1813,6 +1821,15 @@
"UMask": "0xff",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.CL_INST",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of LFENCE instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1822,6 +1839,15 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of LFENCE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.LFENCE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of RDPMC, RDTSC, and RDTSCP instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 9370722dc564..7e9bc4241c61 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -1,7 +1,7 @@
Family-model,Version,Filename,EventType
GenuineIntel-6-(97|9A|B7|BA|BF),v1.37,alderlake,core
GenuineIntel-6-BE,v1.37,alderlaken,core
-GenuineIntel-6-C[56],v1.14,arrowlake,core
+GenuineIntel-6-C[56],v1.16,arrowlake,core
GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
GenuineIntel-6-(3D|47),v30,broadwell,core
GenuineIntel-6-56,v12,broadwellde,core
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 03/10] perf vendor events intel: Update emeraldrapid events from 1.20 to 1.21
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 02/10] perf vendor events intel: Update arrowlake events from 1.14 to 1.16 Ian Rogers
@ 2026-02-26 4:52 ` Ian Rogers
2026-02-26 4:52 ` [PATCH v1 04/10] perf vendor events intel: Update grandridge events from 1.10 to 1.11 Ian Rogers
` (7 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:52 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/210676cfa8743cd5b9e7cc984fdef1a48542eda4
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/emeraldrapids/cache.json | 4 ++--
.../arch/x86/emeraldrapids/frontend.json | 16 ++++++++++++++++
.../arch/x86/emeraldrapids/uncore-cache.json | 4 ++--
.../arch/x86/emeraldrapids/uncore-io.json | 17 +++++++++--------
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
5 files changed, 30 insertions(+), 13 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
index 26568e4b77f7..b2f8947f6741 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
@@ -514,7 +514,7 @@
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
"PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Available PDIST counters: 0",
- "SampleAfterValue": "1000003",
+ "SampleAfterValue": "100007",
"UMask": "0x2"
},
{
@@ -534,7 +534,7 @@
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
"PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Available PDIST counters: 0",
- "SampleAfterValue": "1000003",
+ "SampleAfterValue": "100007",
"UMask": "0x4"
},
{
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json
index 793c486ffabe..e51f5e85ffd1 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json
@@ -271,6 +271,22 @@
"SampleAfterValue": "200003",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_INUSE",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_INUSE",
+ "SampleAfterValue": "200003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_ISB",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_ISB",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8"
+ },
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json
index 92cf47967f0b..3c8dcd9cff7c 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json
@@ -3501,7 +3501,7 @@
"EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
+ "PublicDescription": "Counts when a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
"UMask": "0x4",
"Unit": "CHA"
},
@@ -3523,7 +3523,7 @@
"EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
+ "PublicDescription": "Counts when a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
"UMask": "0x8",
"Unit": "CHA"
},
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json
index d4cf2199d46b..ddb0f65307f4 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json
@@ -223,6 +223,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0xff",
"UMask": "0xff",
"Unit": "IIO"
},
@@ -234,7 +235,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x01",
"PublicDescription": "x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x1",
"Unit": "IIO"
@@ -247,7 +248,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x02",
"PublicDescription": "x4 card is plugged in to slot 1",
"UMask": "0x2",
"Unit": "IIO"
@@ -260,7 +261,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x04",
"PublicDescription": "x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
"UMask": "0x4",
"Unit": "IIO"
@@ -273,7 +274,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x08",
"PublicDescription": "x4 card is plugged in to slot 3",
"UMask": "0x8",
"Unit": "IIO"
@@ -286,7 +287,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x10",
"PublicDescription": "x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x10",
"Unit": "IIO"
@@ -299,7 +300,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x20",
"PublicDescription": "x4 card is plugged in to slot 1",
"UMask": "0x20",
"Unit": "IIO"
@@ -312,7 +313,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x40",
"PublicDescription": "x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
"UMask": "0x40",
"Unit": "IIO"
@@ -325,7 +326,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x80",
"PublicDescription": "x4 card is plugged in to slot 3",
"UMask": "0x80",
"Unit": "IIO"
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 7e9bc4241c61..92799bc6e9d9 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -9,7 +9,7 @@ GenuineIntel-6-4F,v23,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core
GenuineIntel-6-DD,v1.00,clearwaterforest,core
GenuineIntel-6-9[6C],v1.05,elkhartlake,core
-GenuineIntel-6-CF,v1.20,emeraldrapids,core
+GenuineIntel-6-CF,v1.21,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-B6,v1.10,grandridge,core
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 04/10] perf vendor events intel: Update grandridge events from 1.10 to 1.11
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 02/10] perf vendor events intel: Update arrowlake events from 1.14 to 1.16 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 03/10] perf vendor events intel: Update emeraldrapid events from 1.20 to 1.21 Ian Rogers
@ 2026-02-26 4:52 ` Ian Rogers
2026-02-26 4:52 ` [PATCH v1 05/10] perf vendor events intel: Update graniterapids events from 1.16 to 1.17 Ian Rogers
` (6 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:52 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/8ada944c087300c4fc79afcd8512aa3b91bd34f2
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/grandridge/cache.json | 42 +++++++++----------
.../arch/x86/grandridge/pipeline.json | 42 ++++++++++++++++---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
3 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/cache.json b/tools/perf/pmu-events/arch/x86/grandridge/cache.json
index 9abddb06a837..0aa921ba89b4 100644
--- a/tools/perf/pmu-events/arch/x86/grandridge/cache.json
+++ b/tools/perf/pmu-events/arch/x86/grandridge/cache.json
@@ -285,8 +285,8 @@
"UMask": "0x82"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
@@ -296,8 +296,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
@@ -307,8 +307,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
@@ -318,8 +318,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
@@ -329,8 +329,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
@@ -340,8 +340,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
@@ -351,8 +351,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
@@ -362,8 +362,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
@@ -373,8 +373,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
@@ -384,8 +384,8 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
- "Counter": "0,1,2,3,4,5,6,7",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
@@ -458,7 +458,7 @@
"UMask": "0x12"
},
{
- "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
+ "BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
index f56d8d816e53..20986b987e18 100644
--- a/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
@@ -178,7 +178,7 @@
"UMask": "0xf7"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
@@ -192,7 +192,7 @@
"SampleAfterValue": "2000003"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
@@ -208,7 +208,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
@@ -222,10 +222,10 @@
"SampleAfterValue": "2000003"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
+ "BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
- "PublicDescription": "Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32",
+ "PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
@@ -301,6 +301,38 @@
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.CL_INST",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff"
+ },
+ {
+ "BriefDescription": "Counts the number of LFENCE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.LFENCE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "Counts the number of misses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x11"
+ },
{
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 92799bc6e9d9..b84035dc5b4f 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -12,7 +12,7 @@ GenuineIntel-6-9[6C],v1.05,elkhartlake,core
GenuineIntel-6-CF,v1.21,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
-GenuineIntel-6-B6,v1.10,grandridge,core
+GenuineIntel-6-B6,v1.11,grandridge,core
GenuineIntel-6-A[DE],v1.16,graniterapids,core
GenuineIntel-6-(3C|45|46),v36,haswell,core
GenuineIntel-6-3F,v29,haswellx,core
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 05/10] perf vendor events intel: Update graniterapids events from 1.16 to 1.17
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
` (2 preceding siblings ...)
2026-02-26 4:52 ` [PATCH v1 04/10] perf vendor events intel: Update grandridge events from 1.10 to 1.11 Ian Rogers
@ 2026-02-26 4:52 ` Ian Rogers
2026-02-26 4:52 ` [PATCH v1 06/10] perf vendor events intel: Update lunarlake events from 1.19 to 1.21 Ian Rogers
` (5 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:52 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/c9ebc3ff9c3d408a888fbfbe73d386ef86c7306f
With new IO and SNC metrics in:
https://github.com/intel/perfmon/commit/04cf5e1e804afd775401167870d48cd25864be7b
https://github.com/intel/perfmon/commit/98b2602d83de6625bae1e6fcaab3a39b0a341255
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/graniterapids/frontend.json | 16 +++++++++++
.../arch/x86/graniterapids/gnr-metrics.json | 27 +++++++++++++++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json b/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json
index d580d305c926..1fdeaebb739f 100644
--- a/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json
@@ -325,6 +325,22 @@
"SampleAfterValue": "200003",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_INUSE",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_INUSE",
+ "SampleAfterValue": "200003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_ISB",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_ISB",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8"
+ },
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/gnr-metrics.json b/tools/perf/pmu-events/arch/x86/graniterapids/gnr-metrics.json
index cc3c834ca286..299631fb8d53 100644
--- a/tools/perf/pmu-events/arch/x86/graniterapids/gnr-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/graniterapids/gnr-metrics.json
@@ -143,6 +143,12 @@
"MetricName": "io_full_write_l3_miss",
"ScaleUnit": "100%"
},
+ {
+ "BriefDescription": "The number of times per second that ownership of a cacheline was stolen from the integrated IO controller before it was able to write back the modified line",
+ "MetricExpr": "(UNC_I_MISC1.LOST_FWD + UNC_I_MISC1.SEC_RCVD_INVLD) / duration_time",
+ "MetricName": "io_lost_fwd",
+ "ScaleUnit": "1per_sec"
+ },
{
"BriefDescription": "Message Signaled Interrupts (MSI) per second sent by the integrated I/O traffic controller (IIO) to System Configuration Controller (Ubox)",
"MetricExpr": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED / duration_time",
@@ -294,6 +300,27 @@
"MetricName": "memory_bandwidth_write",
"ScaleUnit": "1MB/s"
},
+ {
+ "BriefDescription": "All reads to the local sub-numa cluster cache as a percentage of total memory read accesses",
+ "MetricExpr": "(L2_LINES_IN.ALL - (OCR.READS_TO_CORE.SNC_CACHE.HITM + OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD + OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD + OCR.READS_TO_CORE.REMOTE_MEMORY + OCR.READS_TO_CORE.L3_MISS_LOCAL)) / L2_LINES_IN.ALL",
+ "MetricName": "numa_percent_all_reads_to_local_cluster_cache",
+ "PublicDescription": "All reads to the local sub-numa cluster cache as a percentage of total memory read accesses. Includes demand and prefetch requests for data reads, code reads, read for ownerships (RFO), does not include LLC prefetches",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "All reads to the local sub-numa cluster memory as a percentage of total memory read accesses",
+ "MetricExpr": "OCR.READS_TO_CORE.L3_MISS_LOCAL / L2_LINES_IN.ALL",
+ "MetricName": "numa_percent_all_reads_to_local_cluster_memory",
+ "PublicDescription": "All reads to the local sub-numa cluster memory as a percentage of total memory read accesses. Includes demand and prefetch requests for data reads, code reads, read for ownerships (RFO), does not include LLC prefetches",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "All reads to a remote sub-numa cluster cache as a percentage of total memory read accesses",
+ "MetricExpr": "(OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD + OCR.READS_TO_CORE.SNC_CACHE.HITM) / L2_LINES_IN.ALL",
+ "MetricName": "numa_percent_all_reads_to_remote_cluster_cache",
+ "PublicDescription": "All reads to a remote sub-numa cluster cache as a percentage of total memory read accesses. Includes demand and prefetch requests for data reads, code reads, read for ownerships (RFO), does not include LLC prefetches",
+ "ScaleUnit": "100%"
+ },
{
"BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches",
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index b84035dc5b4f..96580ffda7bf 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -13,7 +13,7 @@ GenuineIntel-6-CF,v1.21,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-B6,v1.11,grandridge,core
-GenuineIntel-6-A[DE],v1.16,graniterapids,core
+GenuineIntel-6-A[DE],v1.17,graniterapids,core
GenuineIntel-6-(3C|45|46),v36,haswell,core
GenuineIntel-6-3F,v29,haswellx,core
GenuineIntel-6-7[DE],v1.24,icelake,core
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 06/10] perf vendor events intel: Update lunarlake events from 1.19 to 1.21
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
` (3 preceding siblings ...)
2026-02-26 4:52 ` [PATCH v1 05/10] perf vendor events intel: Update graniterapids events from 1.16 to 1.17 Ian Rogers
@ 2026-02-26 4:52 ` Ian Rogers
2026-02-26 4:52 ` [PATCH v1 07/10] perf vendor events intel: Update lunarlake events from 1.18 to 1.20 Ian Rogers
` (4 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:52 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/d6755a30419d02930889497741552309343bdb1e
https://github.com/intel/perfmon/commit/6c9f684ae1de6229511fd56d1196fdc2db242a41
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/lunarlake/cache.json | 36 ++++++++++++++-----
.../arch/x86/lunarlake/frontend.json | 27 ++++++++++++++
.../arch/x86/lunarlake/pipeline.json | 10 +++---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
4 files changed, 61 insertions(+), 14 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
index 3d2616be8ec1..2db3e8a51fbd 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
@@ -550,6 +550,24 @@
"UMask": "0x7e",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x35",
+ "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x78",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches. Local DRAM, MMIO or other local memory type provides the data.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x35",
+ "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS_LOCALMEM",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1088,7 +1106,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1100,7 +1118,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1112,7 +1130,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1124,7 +1142,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1136,7 +1154,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1148,7 +1166,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1160,7 +1178,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1172,7 +1190,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1274,7 +1292,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
+ "BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/frontend.json b/tools/perf/pmu-events/arch/x86/lunarlake/frontend.json
index b21d602e9f1a..798eebf77436 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/frontend.json
@@ -424,6 +424,15 @@
"UMask": "0x1",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that missed in the L2 cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc9",
+ "EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L2_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xe",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -500,6 +509,24 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full",
+ "Counter": "0,1,2,3,4,5,6,7,8,9",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_INUSE",
+ "SampleAfterValue": "200003",
+ "UMask": "0x10",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full",
+ "Counter": "0,1,2,3,4,5,6,7,8,9",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_ISB",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3,4,5,6,7,8,9",
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
index 97797f7b072e..d98723b3cd78 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
@@ -634,7 +634,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
@@ -725,7 +725,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
@@ -1530,8 +1530,9 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
+ "BriefDescription": "This event is deprecated.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Deprecated": "1",
"EventCode": "0xe1",
"EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
"SampleAfterValue": "1000003",
@@ -1539,8 +1540,9 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of misses to KeyLocker cache.",
+ "BriefDescription": "This event is deprecated.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Deprecated": "1",
"EventCode": "0xe1",
"EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
"SampleAfterValue": "1000003",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 96580ffda7bf..a2dde3faad5e 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -22,7 +22,7 @@ GenuineIntel-6-3A,v24,ivybridge,core
GenuineIntel-6-3E,v24,ivytown,core
GenuineIntel-6-2D,v24,jaketown,core
GenuineIntel-6-(57|85),v16,knightslanding,core
-GenuineIntel-6-BD,v1.19,lunarlake,core
+GenuineIntel-6-BD,v1.21,lunarlake,core
GenuineIntel-6-(AA|AC|B5),v1.18,meteorlake,core
GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 07/10] perf vendor events intel: Update lunarlake events from 1.18 to 1.20
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
` (4 preceding siblings ...)
2026-02-26 4:52 ` [PATCH v1 06/10] perf vendor events intel: Update lunarlake events from 1.19 to 1.21 Ian Rogers
@ 2026-02-26 4:52 ` Ian Rogers
2026-02-26 7:20 ` Mi, Dapeng
2026-02-26 4:52 ` [PATCH v1 08/10] perf vendor events intel: Update pantherlake events from 1.02 to 1.04 Ian Rogers
` (3 subsequent siblings)
9 siblings, 1 reply; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:52 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/2eebd8e2612a0655e82b88e1d2fab960315c025b
https://github.com/intel/perfmon/commit/81c4ce2c16f05b839d2c40e8cf183ed110357b73
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../pmu-events/arch/x86/meteorlake/cache.json | 67 ++++++++++++++++---
.../arch/x86/meteorlake/frontend.json | 18 +++++
.../arch/x86/meteorlake/pipeline.json | 46 +++++++++++--
4 files changed, 116 insertions(+), 17 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index a2dde3faad5e..8d8fd8b08166 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -23,7 +23,7 @@ GenuineIntel-6-3E,v24,ivytown,core
GenuineIntel-6-2D,v24,jaketown,core
GenuineIntel-6-(57|85),v16,knightslanding,core
GenuineIntel-6-BD,v1.21,lunarlake,core
-GenuineIntel-6-(AA|AC|B5),v1.18,meteorlake,core
+GenuineIntel-6-(AA|AC|B5),v1.20,meteorlake,core
GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core
GenuineIntel-6-CC,v1.02,pantherlake,core
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
index d3fc04b2ffbd..4c1220c19456 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
@@ -513,6 +513,15 @@
"UMask": "0x6",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x35",
+ "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT_NOSNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -522,6 +531,15 @@
"UMask": "0x78",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x35",
+ "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS_LOCALMEM",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -559,6 +577,24 @@
"UMask": "0x6",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but NO_FWD. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -568,6 +604,15 @@
"UMask": "0x78",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition",
"Counter": "0,1,2,3,4,5,6,7",
@@ -969,7 +1014,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -981,7 +1026,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -993,7 +1038,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1005,7 +1050,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1017,7 +1062,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1029,7 +1074,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1041,7 +1086,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1053,7 +1098,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1065,7 +1110,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1077,7 +1122,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -1159,7 +1204,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
+ "BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
index 6484834b1127..dcf8c8e720f3 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
@@ -430,6 +430,24 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_INUSE",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_INUSE",
+ "SampleAfterValue": "200003",
+ "UMask": "0x10",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_ISB",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_ISB",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
index bfdaabe9377d..7662846745bd 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
@@ -517,7 +517,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
@@ -583,7 +583,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
@@ -620,7 +620,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
@@ -804,10 +804,10 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
+ "BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
- "PublicDescription": "Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32",
+ "PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
"SampleAfterValue": "2000003",
"UMask": "0x1",
"Unit": "cpu_atom"
@@ -1207,6 +1207,42 @@
"UMask": "0x20",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.CL_INST",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of LFENCE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.LFENCE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of misses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x11",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"Counter": "0,1,2,3,4,5,6,7",
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 08/10] perf vendor events intel: Update pantherlake events from 1.02 to 1.04
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
` (5 preceding siblings ...)
2026-02-26 4:52 ` [PATCH v1 07/10] perf vendor events intel: Update lunarlake events from 1.18 to 1.20 Ian Rogers
@ 2026-02-26 4:52 ` Ian Rogers
2026-02-26 4:53 ` [PATCH v1 09/10] perf vendor events intel: Update sapphirerapids events from 1.35 to 1.36 Ian Rogers
` (2 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:52 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/1f46fa264d202d57dade1d3fd5b58e79c4706147
https://github.com/intel/perfmon/commit/e49581aeb2903dde6fb1d187e9d412df58e01038
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../arch/x86/pantherlake/cache.json | 159 +++++++++++++-
.../arch/x86/pantherlake/floating-point.json | 28 +++
.../arch/x86/pantherlake/frontend.json | 36 ++++
.../arch/x86/pantherlake/memory.json | 27 +++
.../arch/x86/pantherlake/other.json | 10 +
.../arch/x86/pantherlake/pipeline.json | 200 +++++++++++++++++-
.../arch/x86/pantherlake/virtual-memory.json | 30 +++
8 files changed, 485 insertions(+), 7 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 8d8fd8b08166..0839e21d4006 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -26,7 +26,7 @@ GenuineIntel-6-BD,v1.21,lunarlake,core
GenuineIntel-6-(AA|AC|B5),v1.20,meteorlake,core
GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core
-GenuineIntel-6-CC,v1.02,pantherlake,core
+GenuineIntel-6-CC,v1.04,pantherlake,core
GenuineIntel-6-A7,v1.04,rocketlake,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-8F,v1.35,sapphirerapids,core
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/cache.json b/tools/perf/pmu-events/arch/x86/pantherlake/cache.json
index 91f5ab908926..e5323093eec0 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/cache.json
@@ -149,6 +149,60 @@
"UMask": "0xff",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests. Does not include rejects or recycles, per core event.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x24",
+ "EventName": "L2_REQUEST.DEMAND_CODE_RD",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xc4",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x24",
+ "EventName": "L2_REQUEST.DEMAND_CODE_RD_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x44",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests. Does not include rejects or recycles, per core event.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x24",
+ "EventName": "L2_REQUEST.DEMAND_DATA_RD",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xc1",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x24",
+ "EventName": "L2_REQUEST.DEMAND_DATA_RD_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x41",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests. Does not include rejects or recycles, per core event.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x24",
+ "EventName": "L2_REQUEST.DEMAND_RFO",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xc2",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests that resulted in a Miss. Does not include rejects or recycles, per core event.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x24",
+ "EventName": "L2_REQUEST.DEMAND_RFO_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x42",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of L2 cache accesses from front door requests that resulted in a Hit. Does not include rejects or recycles, per core event.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -158,6 +212,24 @@
"UMask": "0x1bf",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of L2 cache accesses from front door Hardware Prefetch requests. Does not include rejects or recycles, per core event.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x24",
+ "EventName": "L2_REQUEST.HWPF",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xc8",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of L2 cache accesses from front door requests that resulted in a Miss. Does not include rejects or recycles, per core event.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x24",
+ "EventName": "L2_REQUEST.MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x17f",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -365,6 +437,24 @@
"UMask": "0x6",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provided data.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -716,6 +806,16 @@
"UMask": "0x20",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the total number of load ops retired that miss the L3 cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xd3",
+ "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.ALL",
+ "PublicDescription": "Counts the total number of load ops retired that miss the L3 cache. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM",
"Counter": "0,1,2,3,4,5,6,7",
@@ -746,6 +846,26 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and no data was forwarded.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xd4",
+ "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_NO_FWD",
+ "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and no data was forwarded. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x20",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and non-modified data was forwarded.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xd4",
+ "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_WITH_FWD",
+ "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and non-modified data was forwarded. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -796,6 +916,26 @@
"UMask": "0x1c",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xd1",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT_NO_SNOOP",
+ "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and it hit and forwarded data, it hit and did not forward data, or it hit and the forwarded data was modified.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xd1",
+ "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT_SNOOP_HIT",
+ "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and it hit and forwarded data, it hit and did not forward data, or it hit and the forwarded data was modified. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -880,13 +1020,14 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
"MSRIndex": "0x3F6",
"MSRValue": "0x400",
- "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
+ "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Available PDIST counters: 0,1",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
@@ -894,6 +1035,7 @@
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
@@ -906,6 +1048,7 @@
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
@@ -916,13 +1059,14 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
"MSRIndex": "0x3F6",
"MSRValue": "0x800",
- "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
+ "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Available PDIST counters: 0,1",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
@@ -930,6 +1074,7 @@
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
@@ -942,6 +1087,7 @@
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
@@ -954,6 +1100,7 @@
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
@@ -966,6 +1113,7 @@
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
@@ -978,6 +1126,7 @@
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
@@ -990,6 +1139,7 @@
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
@@ -1072,6 +1222,7 @@
{
"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
"Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
"PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES Available PDIST counters: 0,1",
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/floating-point.json b/tools/perf/pmu-events/arch/x86/pantherlake/floating-point.json
index e306a45b22ee..77f6c9028d93 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/floating-point.json
@@ -1,4 +1,14 @@
[
+ {
+ "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "CounterMask": "1",
+ "EventCode": "0xcd",
+ "EventName": "ARITH.FPDIV_ACTIVE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Cycles when floating-point divide unit is busy executing divide or square root operations.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -10,6 +20,24 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of floating point dividers per cycle in the loop stage.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xcd",
+ "EventName": "ARITH.FPDIV_OCCUPANCY",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of floating point divider uops executed per cycle.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xcd",
+ "EventName": "ARITH.FPDIV_UOPS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts all microcode FP assists.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/frontend.json b/tools/perf/pmu-events/arch/x86/pantherlake/frontend.json
index d36faa683d3f..5e69b81742f5 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/frontend.json
@@ -422,6 +422,24 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full",
+ "Counter": "0,1,2,3,4,5,6,7,8,9",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_INUSE",
+ "SampleAfterValue": "200003",
+ "UMask": "0x10",
+ "Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full",
+ "Counter": "0,1,2,3,4,5,6,7,8,9",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_ISB",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -561,5 +579,23 @@
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_core"
+ },
+ {
+ "BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe7",
+ "EventName": "MS_DECODED.MS_BUSY",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe7",
+ "EventName": "MS_DECODED.MS_ENTRY",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/memory.json b/tools/perf/pmu-events/arch/x86/pantherlake/memory.json
index 3d31e620383d..4248cc101391 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/memory.json
@@ -8,6 +8,24 @@
"UMask": "0xf4",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x05",
+ "EventName": "LD_HEAD.L1_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x05",
+ "EventName": "LD_HEAD.L1_MISS_AT_RET",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x81",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -17,6 +35,15 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x05",
+ "EventName": "LD_HEAD.WCB_FULL_AT_RET",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x82",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/other.json b/tools/perf/pmu-events/arch/x86/pantherlake/other.json
index d49651d4f112..915c52f5abd1 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/other.json
@@ -30,6 +30,16 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the total number of BTCLEARS.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe8",
+ "EventName": "PREDICTION.BTCLEAR",
+ "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Cycles the uncore cannot take further requests",
"Counter": "0,1,2,3,4,5,6,7,8,9",
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json b/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json
index fb87d30c403d..86009237df2f 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json
@@ -1,4 +1,14 @@
[
+ {
+ "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "CounterMask": "1",
+ "EventCode": "0xcd",
+ "EventName": "ARITH.DIV_ACTIVE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x3",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -10,6 +20,16 @@
"UMask": "0x9",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of cycles when any of the integer dividers are active.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "CounterMask": "1",
+ "EventCode": "0xcd",
+ "EventName": "ARITH.IDIV_ACTIVE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Cycles when integer divide unit is busy executing divide or square root operations.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -21,6 +41,24 @@
"UMask": "0x8",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts number of active integer dividers per cycle.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xcd",
+ "EventName": "ARITH.IDIV_OCCUPANCY",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of integer divider uops executed per cycle.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xcd",
+ "EventName": "ARITH.IDIV_UOPS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -58,6 +96,38 @@
"SampleAfterValue": "400009",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT]",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "Deprecated": "1",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.ALL_NEAR_IND",
+ "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT] Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN]",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "Deprecated": "1",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.ALL_NEAR_IND_OR_RET",
+ "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN] Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x58",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.COND",
+ "PublicDescription": "Counts the number of conditional branch instructions retired. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x7",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Conditional branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -88,6 +158,16 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of taken conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.COND_TAKEN",
+ "PublicDescription": "Counts the number of taken conditional branch instructions retired. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x3",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Taken conditional branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -98,6 +178,16 @@
"UMask": "0x3",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of taken backward conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.COND_TAKEN_BWD",
+ "PublicDescription": "Counts the number of taken backward conditional branch instructions retired. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Taken backward conditional branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -108,6 +198,16 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of taken forward conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD",
+ "PublicDescription": "Counts the number of taken forward conditional branch instructions retired. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Taken forward conditional branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -178,6 +278,16 @@
"UMask": "0x80",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND]",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.NEAR_INDIRECT",
+ "PublicDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND] Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Indirect near branch instructions retired (excluding returns) [This event is alias to BR_INST_RETIRED.INDIRECT]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -208,6 +318,16 @@
"UMask": "0x40",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET]",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN",
+ "PublicDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET] Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x58",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_CALL]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -283,7 +403,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Taken branch instructions retired.",
+ "BriefDescription": "Near Taken branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@@ -755,7 +875,7 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
@@ -1549,6 +1669,16 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.CL_INST",
+ "PublicDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of LFENCE instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1620,6 +1750,15 @@
"UMask": "0x4",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x75",
+ "EventName": "SERIALIZATION.COLOR_STALLS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1732,6 +1871,15 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x3",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1795,6 +1943,15 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x40",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb",
"Counter": "0,1,2,3,4,5,6,7",
@@ -2076,6 +2233,15 @@
"UMask": "0x10",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of uops issued by the front end every cycle.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x0e",
+ "EventName": "UOPS_ISSUED.ANY",
+ "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
+ "SampleAfterValue": "1000003",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Uops that RAT issues to RS",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -2107,6 +2273,16 @@
"UMask": "0x2",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of uops retired that are the last uop of a macro-instruction.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc2",
+ "EventName": "UOPS_RETIRED.EOM",
+ "PublicDescription": "Counts the number of uops retired that are the last uop of a macro-instruction. EOM uops indicate the 'end of a macro-instruction' and play a crucial role in the processor's control flow and recovery mechanisms.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Retired uops except the last uop of each instruction.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -2127,6 +2303,16 @@
"UMask": "0x80",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops retired that originated from a loop stream detector.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc2",
+ "EventName": "UOPS_RETIRED.LSD",
+ "PublicDescription": "Counts the number of uops retired that originated from a loop stream detector. Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x20",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -2161,6 +2347,16 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "UOPS_RETIRED.NANO_CODE",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc2",
+ "EventName": "UOPS_RETIRED.NANO_CODE",
+ "PublicDescription": "UOPS_RETIRED.NANO_CODE Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/pantherlake/virtual-memory.json
index 8d56c16b2a39..8f3dd36707dc 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/virtual-memory.json
@@ -78,6 +78,16 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x08",
+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
+ "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -178,6 +188,16 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x49",
+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
+ "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -267,6 +287,16 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x85",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
+ "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3,4,5,6,7,8,9",
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 09/10] perf vendor events intel: Update sapphirerapids events from 1.35 to 1.36
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
` (6 preceding siblings ...)
2026-02-26 4:52 ` [PATCH v1 08/10] perf vendor events intel: Update pantherlake events from 1.02 to 1.04 Ian Rogers
@ 2026-02-26 4:53 ` Ian Rogers
2026-02-26 4:53 ` [PATCH v1 10/10] perf vendor events intel: Update sierraforest events from 1.13 to 1.15 Ian Rogers
2026-02-26 7:47 ` [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Mi, Dapeng
9 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:53 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/bda7f1e1839e2f9ea1ac45da338e6fe5ca6fdbb0
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../arch/x86/sapphirerapids/cache.json | 4 ++--
.../arch/x86/sapphirerapids/frontend.json | 16 ++++++++++++++++
.../arch/x86/sapphirerapids/uncore-cache.json | 4 ++--
.../arch/x86/sapphirerapids/uncore-io.json | 17 +++++++++--------
5 files changed, 30 insertions(+), 13 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 0839e21d4006..8ef03af9f150 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -29,7 +29,7 @@ GenuineIntel-6-2E,v4,nehalemex,core
GenuineIntel-6-CC,v1.04,pantherlake,core
GenuineIntel-6-A7,v1.04,rocketlake,core
GenuineIntel-6-2A,v19,sandybridge,core
-GenuineIntel-6-8F,v1.35,sapphirerapids,core
+GenuineIntel-6-8F,v1.36,sapphirerapids,core
GenuineIntel-6-AF,v1.13,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
index c66324d41a89..373b26c84448 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
@@ -514,7 +514,7 @@
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
"PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Available PDIST counters: 0",
- "SampleAfterValue": "1000003",
+ "SampleAfterValue": "100007",
"UMask": "0x2"
},
{
@@ -534,7 +534,7 @@
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
"PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Available PDIST counters: 0",
- "SampleAfterValue": "1000003",
+ "SampleAfterValue": "100007",
"UMask": "0x4"
},
{
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
index 793c486ffabe..e51f5e85ffd1 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
@@ -271,6 +271,22 @@
"SampleAfterValue": "200003",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_INUSE",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_INUSE",
+ "SampleAfterValue": "200003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "ICACHE_TAG.STALLS_ISB",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x83",
+ "EventName": "ICACHE_TAG.STALLS_ISB",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8"
+ },
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json
index 1bdda3c3ccbf..59f6fd2c7a8f 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json
@@ -3501,7 +3501,7 @@
"EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
+ "PublicDescription": "Counts when a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
"UMask": "0x4",
"Unit": "CHA"
},
@@ -3523,7 +3523,7 @@
"EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
+ "PublicDescription": "Counts when a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
"UMask": "0x8",
"Unit": "CHA"
},
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json
index dac7e6c50f31..45675a1099e2 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json
@@ -303,6 +303,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0xff",
"UMask": "0xff",
"Unit": "IIO"
},
@@ -314,7 +315,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x01",
"PublicDescription": "x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x1",
"Unit": "IIO"
@@ -327,7 +328,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x02",
"PublicDescription": "x4 card is plugged in to slot 1",
"UMask": "0x2",
"Unit": "IIO"
@@ -340,7 +341,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x04",
"PublicDescription": "x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
"UMask": "0x4",
"Unit": "IIO"
@@ -353,7 +354,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x08",
"PublicDescription": "x4 card is plugged in to slot 3",
"UMask": "0x8",
"Unit": "IIO"
@@ -366,7 +367,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x10",
"PublicDescription": "x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x10",
"Unit": "IIO"
@@ -379,7 +380,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x20",
"PublicDescription": "x4 card is plugged in to slot 1",
"UMask": "0x20",
"Unit": "IIO"
@@ -392,7 +393,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x40",
"PublicDescription": "x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
"UMask": "0x40",
"Unit": "IIO"
@@ -405,7 +406,7 @@
"Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x0000",
+ "PortMask": "0x80",
"PublicDescription": "x4 card is plugged in to slot 3",
"UMask": "0x80",
"Unit": "IIO"
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v1 10/10] perf vendor events intel: Update sierraforest events from 1.13 to 1.15
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
` (7 preceding siblings ...)
2026-02-26 4:53 ` [PATCH v1 09/10] perf vendor events intel: Update sapphirerapids events from 1.35 to 1.36 Ian Rogers
@ 2026-02-26 4:53 ` Ian Rogers
2026-02-26 7:47 ` [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Mi, Dapeng
9 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 4:53 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Ian Rogers,
Adrian Hunter, James Clark, Andreas Färber,
Manivannan Sadhasivam, Dapeng Mi, linux-perf-users, linux-kernel,
linux-arm-kernel
The updated events were published in:
https://github.com/intel/perfmon/commit/996bacad8f144e675b32f0096b9fe6813380695c
https://github.com/intel/perfmon/commit/93b6ef08ca9b01788458e8f5a0e7cbb716715b7c
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../arch/x86/sierraforest/cache.json | 22 +++++-----
.../arch/x86/sierraforest/pipeline.json | 42 ++++++++++++++++---
3 files changed, 49 insertions(+), 17 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 8ef03af9f150..8a9e1735e21e 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -30,7 +30,7 @@ GenuineIntel-6-CC,v1.04,pantherlake,core
GenuineIntel-6-A7,v1.04,rocketlake,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-8F,v1.36,sapphirerapids,core
-GenuineIntel-6-AF,v1.13,sierraforest,core
+GenuineIntel-6-AF,v1.15,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core
GenuineIntel-6-55-[01234],v1.37,skylakex,core
diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/cache.json b/tools/perf/pmu-events/arch/x86/sierraforest/cache.json
index de0e7661a52d..168f43557a0e 100644
--- a/tools/perf/pmu-events/arch/x86/sierraforest/cache.json
+++ b/tools/perf/pmu-events/arch/x86/sierraforest/cache.json
@@ -326,7 +326,7 @@
"UMask": "0x82"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -337,7 +337,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -348,7 +348,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -359,7 +359,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -370,7 +370,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -381,7 +381,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -392,7 +392,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -403,7 +403,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -414,7 +414,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -425,7 +425,7 @@
"UMask": "0x5"
},
{
- "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
@@ -499,7 +499,7 @@
"UMask": "0x12"
},
{
- "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
+ "BriefDescription": "Counts the number of stores uops retired.",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json b/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
index 70af13143024..cf67ff6135e0 100644
--- a/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
@@ -186,7 +186,7 @@
"UMask": "0xf7"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
@@ -200,7 +200,7 @@
"SampleAfterValue": "2000003"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
@@ -216,7 +216,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
@@ -230,10 +230,10 @@
"SampleAfterValue": "2000003"
},
{
- "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
+ "BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
- "PublicDescription": "Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32",
+ "PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
@@ -309,6 +309,38 @@
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.CL_INST",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff"
+ },
+ {
+ "BriefDescription": "Counts the number of LFENCE instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe0",
+ "EventName": "MISC_RETIRED1.LFENCE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "Counts the number of misses to KeyLocker cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xe1",
+ "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x11"
+ },
{
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.",
"Counter": "0,1,2,3,4,5,6,7",
--
2.53.0.414.gf7e9f6c205-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v1 07/10] perf vendor events intel: Update lunarlake events from 1.18 to 1.20
2026-02-26 4:52 ` [PATCH v1 07/10] perf vendor events intel: Update lunarlake events from 1.18 to 1.20 Ian Rogers
@ 2026-02-26 7:20 ` Mi, Dapeng
2026-02-26 16:54 ` Ian Rogers
0 siblings, 1 reply; 13+ messages in thread
From: Mi, Dapeng @ 2026-02-26 7:20 UTC (permalink / raw)
To: Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Adrian Hunter,
James Clark, Andreas Färber, Manivannan Sadhasivam,
linux-perf-users, linux-kernel, linux-arm-kernel
It seems a typo in the shortlog, it should be meteorlake instead of
lunarlake. :)
On 2/26/2026 12:52 PM, Ian Rogers wrote:
> The updated events were published in:
> https://github.com/intel/perfmon/commit/2eebd8e2612a0655e82b88e1d2fab960315c025b
> https://github.com/intel/perfmon/commit/81c4ce2c16f05b839d2c40e8cf183ed110357b73
>
> Signed-off-by: Ian Rogers <irogers@google.com>
> ---
> tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
> .../pmu-events/arch/x86/meteorlake/cache.json | 67 ++++++++++++++++---
> .../arch/x86/meteorlake/frontend.json | 18 +++++
> .../arch/x86/meteorlake/pipeline.json | 46 +++++++++++--
> 4 files changed, 116 insertions(+), 17 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
> index a2dde3faad5e..8d8fd8b08166 100644
> --- a/tools/perf/pmu-events/arch/x86/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
> @@ -23,7 +23,7 @@ GenuineIntel-6-3E,v24,ivytown,core
> GenuineIntel-6-2D,v24,jaketown,core
> GenuineIntel-6-(57|85),v16,knightslanding,core
> GenuineIntel-6-BD,v1.21,lunarlake,core
> -GenuineIntel-6-(AA|AC|B5),v1.18,meteorlake,core
> +GenuineIntel-6-(AA|AC|B5),v1.20,meteorlake,core
> GenuineIntel-6-1[AEF],v4,nehalemep,core
> GenuineIntel-6-2E,v4,nehalemex,core
> GenuineIntel-6-CC,v1.02,pantherlake,core
> diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
> index d3fc04b2ffbd..4c1220c19456 100644
> --- a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
> @@ -513,6 +513,15 @@
> "UMask": "0x6",
> "Unit": "cpu_atom"
> },
> + {
> + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x35",
> + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT_NOSNOOP",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2",
> + "Unit": "cpu_atom"
> + },
> {
> "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
> "Counter": "0,1,2,3,4,5,6,7",
> @@ -522,6 +531,15 @@
> "UMask": "0x78",
> "Unit": "cpu_atom"
> },
> + {
> + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x35",
> + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS_LOCALMEM",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x50",
> + "Unit": "cpu_atom"
> + },
> {
> "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
> "Counter": "0,1,2,3,4,5,6,7",
> @@ -559,6 +577,24 @@
> "UMask": "0x6",
> "Unit": "cpu_atom"
> },
> + {
> + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2",
> + "Unit": "cpu_atom"
> + },
> + {
> + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but NO_FWD. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x4",
> + "Unit": "cpu_atom"
> + },
> {
> "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
> "Counter": "0,1,2,3,4,5,6,7",
> @@ -568,6 +604,15 @@
> "UMask": "0x78",
> "Unit": "cpu_atom"
> },
> + {
> + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x50",
> + "Unit": "cpu_atom"
> + },
> {
> "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition",
> "Counter": "0,1,2,3,4,5,6,7",
> @@ -969,7 +1014,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -981,7 +1026,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -993,7 +1038,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -1005,7 +1050,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -1017,7 +1062,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -1029,7 +1074,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -1041,7 +1086,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -1053,7 +1098,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -1065,7 +1110,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -1077,7 +1122,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> @@ -1159,7 +1204,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
> + "BriefDescription": "Counts the number of stores uops retired.",
> "Counter": "0,1,2,3,4,5,6,7",
> "Data_LA": "1",
> "EventCode": "0xd0",
> diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
> index 6484834b1127..dcf8c8e720f3 100644
> --- a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
> +++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
> @@ -430,6 +430,24 @@
> "UMask": "0x4",
> "Unit": "cpu_core"
> },
> + {
> + "BriefDescription": "ICACHE_TAG.STALLS_INUSE",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x83",
> + "EventName": "ICACHE_TAG.STALLS_INUSE",
> + "SampleAfterValue": "200003",
> + "UMask": "0x10",
> + "Unit": "cpu_core"
> + },
> + {
> + "BriefDescription": "ICACHE_TAG.STALLS_ISB",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x83",
> + "EventName": "ICACHE_TAG.STALLS_ISB",
> + "SampleAfterValue": "200003",
> + "UMask": "0x8",
> + "Unit": "cpu_core"
> + },
> {
> "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
> "Counter": "0,1,2,3",
> diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
> index bfdaabe9377d..7662846745bd 100644
> --- a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
> +++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
> @@ -517,7 +517,7 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
> "Counter": "Fixed counter 1",
> "EventName": "CPU_CLK_UNHALTED.CORE",
> "SampleAfterValue": "2000003",
> @@ -583,7 +583,7 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
> "Counter": "Fixed counter 2",
> "EventName": "CPU_CLK_UNHALTED.REF_TSC",
> "SampleAfterValue": "2000003",
> @@ -620,7 +620,7 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
> "Counter": "Fixed counter 1",
> "EventName": "CPU_CLK_UNHALTED.THREAD",
> "SampleAfterValue": "2000003",
> @@ -804,10 +804,10 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
> + "BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
> "Counter": "Fixed counter 0",
> "EventName": "INST_RETIRED.ANY",
> - "PublicDescription": "Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32",
> + "PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
> "SampleAfterValue": "2000003",
> "UMask": "0x1",
> "Unit": "cpu_atom"
> @@ -1207,6 +1207,42 @@
> "UMask": "0x20",
> "Unit": "cpu_core"
> },
> + {
> + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xe0",
> + "EventName": "MISC_RETIRED1.CL_INST",
> + "SampleAfterValue": "1000003",
> + "UMask": "0xff",
> + "Unit": "cpu_atom"
> + },
> + {
> + "BriefDescription": "Counts the number of LFENCE instructions retired.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xe0",
> + "EventName": "MISC_RETIRED1.LFENCE",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2",
> + "Unit": "cpu_atom"
> + },
> + {
> + "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xe1",
> + "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x10",
> + "Unit": "cpu_atom"
> + },
> + {
> + "BriefDescription": "Counts the number of misses to KeyLocker cache.",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xe1",
> + "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x11",
> + "Unit": "cpu_atom"
> + },
> {
> "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
> "Counter": "0,1,2,3,4,5,6,7",
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37
2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
` (8 preceding siblings ...)
2026-02-26 4:53 ` [PATCH v1 10/10] perf vendor events intel: Update sierraforest events from 1.13 to 1.15 Ian Rogers
@ 2026-02-26 7:47 ` Mi, Dapeng
9 siblings, 0 replies; 13+ messages in thread
From: Mi, Dapeng @ 2026-02-26 7:47 UTC (permalink / raw)
To: Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Adrian Hunter,
James Clark, Andreas Färber, Manivannan Sadhasivam,
linux-perf-users, linux-kernel, linux-arm-kernel
The whole patch-set looks good to me. Building the patches on Sapphire
rapids and Arrowlake, no issue is found. Thanks.
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
On 2/26/2026 12:52 PM, Ian Rogers wrote:
> The updated events were published in:
> https://github.com/intel/perfmon/commit/632936400cfc5978c7b4519c865c137de523bfdd
> https://github.com/intel/perfmon/commit/a96d6bf4b50d6ce31e2ffd0be8d13022d07ae319
>
> Signed-off-by: Ian Rogers <irogers@google.com>
> ---
> .../pmu-events/arch/x86/alderlake/cache.json | 27 +++-----
> .../arch/x86/alderlake/frontend.json | 18 +++++
> .../arch/x86/alderlake/pipeline.json | 66 +++++++++++++++++--
> .../pmu-events/arch/x86/alderlaken/cache.json | 27 +++-----
> .../arch/x86/alderlaken/pipeline.json | 60 +++++++++++++++--
> tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +-
> 6 files changed, 152 insertions(+), 50 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/alderlake/cache.json b/tools/perf/pmu-events/arch/x86/alderlake/cache.json
> index be15a7f83717..5d0d824f3e7e 100644
> --- a/tools/perf/pmu-events/arch/x86/alderlake/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/alderlake/cache.json
> @@ -876,105 +876,97 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x80",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5",
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x10",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5",
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x100",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5",
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x20",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5",
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x4",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5",
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x200",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5",
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x40",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5",
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x8",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5",
> "Unit": "cpu_atom"
> @@ -1030,12 +1022,11 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
> + "BriefDescription": "Counts the number of stores uops retired.",
> "Counter": "0,1,2,3,4,5",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
> - "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x6",
> "Unit": "cpu_atom"
> diff --git a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json
> index ff3b30c2619a..11fc853f2d0b 100644
> --- a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json
> +++ b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json
> @@ -327,6 +327,24 @@
> "UMask": "0x4",
> "Unit": "cpu_core"
> },
> + {
> + "BriefDescription": "ICACHE_TAG.STALLS_INUSE",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x83",
> + "EventName": "ICACHE_TAG.STALLS_INUSE",
> + "SampleAfterValue": "200003",
> + "UMask": "0x10",
> + "Unit": "cpu_core"
> + },
> + {
> + "BriefDescription": "ICACHE_TAG.STALLS_ISB",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x83",
> + "EventName": "ICACHE_TAG.STALLS_ISB",
> + "SampleAfterValue": "200003",
> + "UMask": "0x8",
> + "Unit": "cpu_core"
> + },
> {
> "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
> "Counter": "0,1,2,3",
> diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
> index 57a8c78cdc49..80cad3c49d20 100644
> --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
> +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
> @@ -244,6 +244,15 @@
> "UMask": "0xfb",
> "Unit": "cpu_atom"
> },
> + {
> + "BriefDescription": "Counts the number of near indirect JMP branch instructions retired.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xc4",
> + "EventName": "BR_INST_RETIRED.INDIRECT_JMP",
> + "SampleAfterValue": "200003",
> + "UMask": "0xef",
> + "Unit": "cpu_atom"
> + },
> {
> "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL",
> "Counter": "0,1,2,3,4,5",
> @@ -464,6 +473,15 @@
> "UMask": "0x2",
> "Unit": "cpu_core"
> },
> + {
> + "BriefDescription": "Counts the number of mispredicted near indirect JMP branch instructions retired.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xc5",
> + "EventName": "BR_MISP_RETIRED.INDIRECT_JMP",
> + "SampleAfterValue": "200003",
> + "UMask": "0xef",
> + "Unit": "cpu_atom"
> + },
> {
> "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL",
> "Counter": "0,1,2,3,4,5",
> @@ -573,7 +591,7 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
> "Counter": "Fixed counter 1",
> "EventName": "CPU_CLK_UNHALTED.CORE",
> "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
> @@ -582,7 +600,7 @@
> "Unit": "cpu_atom"
> },
> {
> - "BriefDescription": "Counts the number of unhalted core clock cycles.",
> + "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
> "Counter": "0,1,2,3,4,5",
> "EventCode": "0x3c",
> "EventName": "CPU_CLK_UNHALTED.CORE_P",
> @@ -651,7 +669,7 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles at TSC frequency.",
> "Counter": "Fixed counter 2",
> "EventName": "CPU_CLK_UNHALTED.REF_TSC",
> "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
> @@ -689,7 +707,7 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
> "Counter": "Fixed counter 1",
> "EventName": "CPU_CLK_UNHALTED.THREAD",
> "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
> @@ -707,7 +725,7 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Counts the number of unhalted core clock cycles.",
> + "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
> "Counter": "0,1,2,3,4,5",
> "EventCode": "0x3c",
> "EventName": "CPU_CLK_UNHALTED.THREAD_P",
> @@ -875,7 +893,7 @@
> "Unit": "cpu_core"
> },
> {
> - "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
> + "BriefDescription": "Fixed Counter: Counts the total number of instructions retired.",
> "Counter": "Fixed counter 0",
> "EventName": "INST_RETIRED.ANY",
> "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. Available PDIST counters: 32",
> @@ -1273,6 +1291,42 @@
> "UMask": "0x20",
> "Unit": "cpu_core"
> },
> + {
> + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xe0",
> + "EventName": "MISC_RETIRED1.CL_INST",
> + "SampleAfterValue": "1000003",
> + "UMask": "0xff",
> + "Unit": "cpu_atom"
> + },
> + {
> + "BriefDescription": "Counts the number of LFENCE instructions retired.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xe0",
> + "EventName": "MISC_RETIRED1.LFENCE",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2",
> + "Unit": "cpu_atom"
> + },
> + {
> + "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xe1",
> + "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x10",
> + "Unit": "cpu_atom"
> + },
> + {
> + "BriefDescription": "Counts the number of misses to KeyLocker cache.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xe1",
> + "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x11",
> + "Unit": "cpu_atom"
> + },
> {
> "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
> "Counter": "0,1,2,3,4,5,6,7",
> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json
> index 76a841675337..1f97a4dc6fb1 100644
> --- a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json
> @@ -246,98 +246,90 @@
> "UMask": "0x82"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x80",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x10",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x100",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x20",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x4",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x200",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x40",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5"
> },
> {
> - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
> + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
> "Counter": "0,1",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
> "MSRIndex": "0x3F6",
> "MSRValue": "0x8",
> - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x5"
> },
> @@ -387,12 +379,11 @@
> "UMask": "0x12"
> },
> {
> - "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
> + "BriefDescription": "Counts the number of stores uops retired.",
> "Counter": "0,1,2,3,4,5",
> "Data_LA": "1",
> "EventCode": "0xd0",
> "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
> - "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",
> "SampleAfterValue": "1000003",
> "UMask": "0x6"
> },
> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json
> index d650cbd48c1f..a13851071624 100644
> --- a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json
> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json
> @@ -108,6 +108,14 @@
> "SampleAfterValue": "200003",
> "UMask": "0xfb"
> },
> + {
> + "BriefDescription": "Counts the number of near indirect JMP branch instructions retired.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xc4",
> + "EventName": "BR_INST_RETIRED.INDIRECT_JMP",
> + "SampleAfterValue": "200003",
> + "UMask": "0xef"
> + },
> {
> "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL",
> "Counter": "0,1,2,3,4,5",
> @@ -225,6 +233,14 @@
> "SampleAfterValue": "200003",
> "UMask": "0xfb"
> },
> + {
> + "BriefDescription": "Counts the number of mispredicted near indirect JMP branch instructions retired.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xc5",
> + "EventName": "BR_MISP_RETIRED.INDIRECT_JMP",
> + "SampleAfterValue": "200003",
> + "UMask": "0xef"
> + },
> {
> "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL",
> "Counter": "0,1,2,3,4,5",
> @@ -278,7 +294,7 @@
> "UMask": "0xfe"
> },
> {
> - "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
> "Counter": "Fixed counter 1",
> "EventName": "CPU_CLK_UNHALTED.CORE",
> "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
> @@ -286,7 +302,7 @@
> "UMask": "0x2"
> },
> {
> - "BriefDescription": "Counts the number of unhalted core clock cycles.",
> + "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
> "Counter": "0,1,2,3,4,5",
> "EventCode": "0x3c",
> "EventName": "CPU_CLK_UNHALTED.CORE_P",
> @@ -303,7 +319,7 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles at TSC frequency.",
> "Counter": "Fixed counter 2",
> "EventName": "CPU_CLK_UNHALTED.REF_TSC",
> "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
> @@ -320,7 +336,7 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
> + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
> "Counter": "Fixed counter 1",
> "EventName": "CPU_CLK_UNHALTED.THREAD",
> "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
> @@ -328,7 +344,7 @@
> "UMask": "0x2"
> },
> {
> - "BriefDescription": "Counts the number of unhalted core clock cycles.",
> + "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
> "Counter": "0,1,2,3,4,5",
> "EventCode": "0x3c",
> "EventName": "CPU_CLK_UNHALTED.THREAD_P",
> @@ -336,7 +352,7 @@
> "SampleAfterValue": "2000003"
> },
> {
> - "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
> + "BriefDescription": "Fixed Counter: Counts the total number of instructions retired.",
> "Counter": "Fixed counter 0",
> "EventName": "INST_RETIRED.ANY",
> "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. Available PDIST counters: 32",
> @@ -426,6 +442,38 @@
> "SampleAfterValue": "1000003",
> "UMask": "0x1"
> },
> + {
> + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xe0",
> + "EventName": "MISC_RETIRED1.CL_INST",
> + "SampleAfterValue": "1000003",
> + "UMask": "0xff"
> + },
> + {
> + "BriefDescription": "Counts the number of LFENCE instructions retired.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xe0",
> + "EventName": "MISC_RETIRED1.LFENCE",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xe1",
> + "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Counts the number of misses to KeyLocker cache.",
> + "Counter": "0,1,2,3,4,5",
> + "EventCode": "0xe1",
> + "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x11"
> + },
> {
> "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)",
> "Counter": "0,1,2,3,4,5",
> diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
> index 149bbe7abaf5..9370722dc564 100644
> --- a/tools/perf/pmu-events/arch/x86/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
> @@ -1,6 +1,6 @@
> Family-model,Version,Filename,EventType
> -GenuineIntel-6-(97|9A|B7|BA|BF),v1.35,alderlake,core
> -GenuineIntel-6-BE,v1.35,alderlaken,core
> +GenuineIntel-6-(97|9A|B7|BA|BF),v1.37,alderlake,core
> +GenuineIntel-6-BE,v1.37,alderlaken,core
> GenuineIntel-6-C[56],v1.14,arrowlake,core
> GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
> GenuineIntel-6-(3D|47),v30,broadwell,core
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 07/10] perf vendor events intel: Update lunarlake events from 1.18 to 1.20
2026-02-26 7:20 ` Mi, Dapeng
@ 2026-02-26 16:54 ` Ian Rogers
0 siblings, 0 replies; 13+ messages in thread
From: Ian Rogers @ 2026-02-26 16:54 UTC (permalink / raw)
To: Mi, Dapeng
Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Alexander Shishkin, Jiri Olsa, Adrian Hunter,
James Clark, Andreas Färber, Manivannan Sadhasivam,
linux-perf-users, linux-kernel, linux-arm-kernel
On Wed, Feb 25, 2026 at 11:20 PM Mi, Dapeng <dapeng1.mi@linux.intel.com> wrote:
>
> It seems a typo in the shortlog, it should be meteorlake instead of
> lunarlake. :)
You're right, wil fix in v2.
Thanks,
Ian
>
> On 2/26/2026 12:52 PM, Ian Rogers wrote:
> > The updated events were published in:
> > https://github.com/intel/perfmon/commit/2eebd8e2612a0655e82b88e1d2fab960315c025b
> > https://github.com/intel/perfmon/commit/81c4ce2c16f05b839d2c40e8cf183ed110357b73
> >
> > Signed-off-by: Ian Rogers <irogers@google.com>
> > ---
> > tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
> > .../pmu-events/arch/x86/meteorlake/cache.json | 67 ++++++++++++++++---
> > .../arch/x86/meteorlake/frontend.json | 18 +++++
> > .../arch/x86/meteorlake/pipeline.json | 46 +++++++++++--
> > 4 files changed, 116 insertions(+), 17 deletions(-)
> >
> > diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
> > index a2dde3faad5e..8d8fd8b08166 100644
> > --- a/tools/perf/pmu-events/arch/x86/mapfile.csv
> > +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
> > @@ -23,7 +23,7 @@ GenuineIntel-6-3E,v24,ivytown,core
> > GenuineIntel-6-2D,v24,jaketown,core
> > GenuineIntel-6-(57|85),v16,knightslanding,core
> > GenuineIntel-6-BD,v1.21,lunarlake,core
> > -GenuineIntel-6-(AA|AC|B5),v1.18,meteorlake,core
> > +GenuineIntel-6-(AA|AC|B5),v1.20,meteorlake,core
> > GenuineIntel-6-1[AEF],v4,nehalemep,core
> > GenuineIntel-6-2E,v4,nehalemex,core
> > GenuineIntel-6-CC,v1.02,pantherlake,core
> > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
> > index d3fc04b2ffbd..4c1220c19456 100644
> > --- a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
> > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
> > @@ -513,6 +513,15 @@
> > "UMask": "0x6",
> > "Unit": "cpu_atom"
> > },
> > + {
> > + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0x35",
> > + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT_NOSNOOP",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0x2",
> > + "Unit": "cpu_atom"
> > + },
> > {
> > "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
> > "Counter": "0,1,2,3,4,5,6,7",
> > @@ -522,6 +531,15 @@
> > "UMask": "0x78",
> > "Unit": "cpu_atom"
> > },
> > + {
> > + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0x35",
> > + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS_LOCALMEM",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0x50",
> > + "Unit": "cpu_atom"
> > + },
> > {
> > "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
> > "Counter": "0,1,2,3,4,5,6,7",
> > @@ -559,6 +577,24 @@
> > "UMask": "0x6",
> > "Unit": "cpu_atom"
> > },
> > + {
> > + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0x34",
> > + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0x2",
> > + "Unit": "cpu_atom"
> > + },
> > + {
> > + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but NO_FWD. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0x34",
> > + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0x4",
> > + "Unit": "cpu_atom"
> > + },
> > {
> > "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
> > "Counter": "0,1,2,3,4,5,6,7",
> > @@ -568,6 +604,15 @@
> > "UMask": "0x78",
> > "Unit": "cpu_atom"
> > },
> > + {
> > + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0x34",
> > + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0x50",
> > + "Unit": "cpu_atom"
> > + },
> > {
> > "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition",
> > "Counter": "0,1,2,3,4,5,6,7",
> > @@ -969,7 +1014,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -981,7 +1026,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -993,7 +1038,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -1005,7 +1050,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -1017,7 +1062,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -1029,7 +1074,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -1041,7 +1086,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -1053,7 +1098,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -1065,7 +1110,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -1077,7 +1122,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
> > + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.",
> > "Counter": "0,1",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > @@ -1159,7 +1204,7 @@
> > "Unit": "cpu_atom"
> > },
> > {
> > - "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
> > + "BriefDescription": "Counts the number of stores uops retired.",
> > "Counter": "0,1,2,3,4,5,6,7",
> > "Data_LA": "1",
> > "EventCode": "0xd0",
> > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
> > index 6484834b1127..dcf8c8e720f3 100644
> > --- a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
> > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
> > @@ -430,6 +430,24 @@
> > "UMask": "0x4",
> > "Unit": "cpu_core"
> > },
> > + {
> > + "BriefDescription": "ICACHE_TAG.STALLS_INUSE",
> > + "Counter": "0,1,2,3",
> > + "EventCode": "0x83",
> > + "EventName": "ICACHE_TAG.STALLS_INUSE",
> > + "SampleAfterValue": "200003",
> > + "UMask": "0x10",
> > + "Unit": "cpu_core"
> > + },
> > + {
> > + "BriefDescription": "ICACHE_TAG.STALLS_ISB",
> > + "Counter": "0,1,2,3",
> > + "EventCode": "0x83",
> > + "EventName": "ICACHE_TAG.STALLS_ISB",
> > + "SampleAfterValue": "200003",
> > + "UMask": "0x8",
> > + "Unit": "cpu_core"
> > + },
> > {
> > "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
> > "Counter": "0,1,2,3",
> > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
> > index bfdaabe9377d..7662846745bd 100644
> > --- a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
> > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
> > @@ -517,7 +517,7 @@
> > "Unit": "cpu_core"
> > },
> > {
> > - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
> > + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
> > "Counter": "Fixed counter 1",
> > "EventName": "CPU_CLK_UNHALTED.CORE",
> > "SampleAfterValue": "2000003",
> > @@ -583,7 +583,7 @@
> > "Unit": "cpu_core"
> > },
> > {
> > - "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
> > + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
> > "Counter": "Fixed counter 2",
> > "EventName": "CPU_CLK_UNHALTED.REF_TSC",
> > "SampleAfterValue": "2000003",
> > @@ -620,7 +620,7 @@
> > "Unit": "cpu_core"
> > },
> > {
> > - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
> > + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
> > "Counter": "Fixed counter 1",
> > "EventName": "CPU_CLK_UNHALTED.THREAD",
> > "SampleAfterValue": "2000003",
> > @@ -804,10 +804,10 @@
> > "Unit": "cpu_core"
> > },
> > {
> > - "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
> > + "BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
> > "Counter": "Fixed counter 0",
> > "EventName": "INST_RETIRED.ANY",
> > - "PublicDescription": "Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32",
> > + "PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
> > "SampleAfterValue": "2000003",
> > "UMask": "0x1",
> > "Unit": "cpu_atom"
> > @@ -1207,6 +1207,42 @@
> > "UMask": "0x20",
> > "Unit": "cpu_core"
> > },
> > + {
> > + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0xe0",
> > + "EventName": "MISC_RETIRED1.CL_INST",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0xff",
> > + "Unit": "cpu_atom"
> > + },
> > + {
> > + "BriefDescription": "Counts the number of LFENCE instructions retired.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0xe0",
> > + "EventName": "MISC_RETIRED1.LFENCE",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0x2",
> > + "Unit": "cpu_atom"
> > + },
> > + {
> > + "BriefDescription": "Counts the number of accesses to KeyLocker cache.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0xe1",
> > + "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0x10",
> > + "Unit": "cpu_atom"
> > + },
> > + {
> > + "BriefDescription": "Counts the number of misses to KeyLocker cache.",
> > + "Counter": "0,1,2,3,4,5,6,7",
> > + "EventCode": "0xe1",
> > + "EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
> > + "SampleAfterValue": "1000003",
> > + "UMask": "0x11",
> > + "Unit": "cpu_atom"
> > + },
> > {
> > "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
> > "Counter": "0,1,2,3,4,5,6,7",
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-02-26 16:54 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
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2026-02-26 4:52 [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 02/10] perf vendor events intel: Update arrowlake events from 1.14 to 1.16 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 03/10] perf vendor events intel: Update emeraldrapid events from 1.20 to 1.21 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 04/10] perf vendor events intel: Update grandridge events from 1.10 to 1.11 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 05/10] perf vendor events intel: Update graniterapids events from 1.16 to 1.17 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 06/10] perf vendor events intel: Update lunarlake events from 1.19 to 1.21 Ian Rogers
2026-02-26 4:52 ` [PATCH v1 07/10] perf vendor events intel: Update lunarlake events from 1.18 to 1.20 Ian Rogers
2026-02-26 7:20 ` Mi, Dapeng
2026-02-26 16:54 ` Ian Rogers
2026-02-26 4:52 ` [PATCH v1 08/10] perf vendor events intel: Update pantherlake events from 1.02 to 1.04 Ian Rogers
2026-02-26 4:53 ` [PATCH v1 09/10] perf vendor events intel: Update sapphirerapids events from 1.35 to 1.36 Ian Rogers
2026-02-26 4:53 ` [PATCH v1 10/10] perf vendor events intel: Update sierraforest events from 1.13 to 1.15 Ian Rogers
2026-02-26 7:47 ` [PATCH v1 01/10] perf vendor events intel: Update alderlake events from 1.35 to 1.37 Mi, Dapeng
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