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smtpout-01.galae.net (Postfix) with ESMTPS id 76D035FE46; Fri, 27 Feb 2026 07:52:51 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 334181036921D; Fri, 27 Feb 2026 08:52:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772178770; h=from:subject:date:message-id:to:cc:mime-version:content-type: in-reply-to:references; bh=XeSGj5Dm4pJG5BITfxYeiMkJ31GOO56vEhVegrdik1Y=; b=GDsbHRpskTwbgPCwbTo43xynJyZkgTgFYfyHpCTsnpwEHZpZCegYn4WbFulSq7CjsIYAYK mJrzWuXbigpntKfAPj/UMVo8J+bpYYQjVnMRYUtSKdcFYeA2AoHrZ3MQ7wRLJZUYlvHE83 VVXalmgapClSSjRbBdOTDLXJNfyYdt+1da79GtxntUpwxIEQVoaEcmX8siASRnWz4o/GZD 4/3b2U3gJzPmfUv7oebo/n/KCI5PB/Z7QTQIPnGaquuEEuv5bnIjQEH69WjFBhRzqFmGTZ iLkR4odNOe2XKtAClS6o6i0258v24jEmGHC1PZwoxvdiq4hwCo/EE9M9jP/RGQ== Date: Fri, 27 Feb 2026 08:52:39 +0100 From: Alexandre Belloni To: Balakrishnan Sambath Cc: wim@linux-watchdog.org, linux@roeck-us.net, nicolas.ferre@microchip.com, claudiu.beznea@tuxon.dev, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrei Simion Subject: Re: [PATCH 1/3] watchdog: at91sam9_wdt.h: Cleanup the header file Message-ID: <202602270752399219b90c@mail.local> References: <20260227073116.30447-1-balakrishnan.s@microchip.com> <20260227073116.30447-2-balakrishnan.s@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260227073116.30447-2-balakrishnan.s@microchip.com> X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260226_235256_953973_253475C1 X-CRM114-Status: GOOD ( 21.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 27/02/2026 13:01:14+0530, Balakrishnan Sambath wrote: > From: Andrei Simion > > This patch reorganizes the header file by renaming the registers using > a general pattern also this patch simplifies the watchdog disable logic > in the at91sam9_wdt.h header by differentiating between modern > (SAM9X60, SAMA7G5, SAM9X7) and legacy (SAMA5, AT91SAM9261) chips based > on the watchdog disable bit. > For modern chips, the disable bit is at bit 12, while for legacy chips > it is at bit 15. > > Signed-off-by: Andrei Simion > [Remove Kconfig-based WDDIS selection and define explicit legacy and > modern masks] > Signed-off-by: Balakrishnan Sambath > --- > drivers/watchdog/at91sam9_wdt.h | 65 ++++++++++++++++----------------- > 1 file changed, 32 insertions(+), 33 deletions(-) > > diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wdt.h > index 298d545df1a1..1e0aeecb489f 100644 > --- a/drivers/watchdog/at91sam9_wdt.h > +++ b/drivers/watchdog/at91sam9_wdt.h > @@ -3,59 +3,58 @@ > * drivers/watchdog/at91sam9_wdt.h > * > * Copyright (C) 2007 Andrew Victor > * Copyright (C) 2007 Atmel Corporation. > * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries > * > * Watchdog Timer (WDT) - System peripherals regsters. > * Based on AT91SAM9261 datasheet revision D. > * Based on SAM9X60 datasheet. > + * Based on SAMA7G5 datasheet. > + * Based on SAM9X75 datasheet. > * > */ > > #ifndef AT91_WDT_H > #define AT91_WDT_H > > #include > > -#define AT91_WDT_CR 0x00 /* Watchdog Control Register */ > -#define AT91_WDT_WDRSTT BIT(0) /* Restart */ > -#define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ > - > -#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ > -#define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ > -#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) > -#define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */ > -#define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */ > +#define AT91_WDT_CR 0x00 /* Watchdog Control Register */ > +#define AT91_WDT_WDRSTT BIT(0) /* Restart */ > +#define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ > +#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ > +#define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ > #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */ > -#define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */ > -#define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */ > -#define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */ > -#define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */ > -#define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */ > -#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) > -#define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */ > -#define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */ > - > +#define AT91_WDT_WDRSTEN BIT(13) > +#define AT91_WDT_WDRPROC BIT(14) > +#define AT91_WDT_WDD (0xfffUL << 16) > +#define AT91_WDT_WDDBGHLT BIT(28) > +#define AT91_WDT_WDIDLEHLT BIT(29) > #define AT91_WDT_SR 0x08 /* Watchdog Status Register */ > #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */ > #define AT91_WDT_WDERR BIT(1) /* Watchdog Error */ > > -/* Watchdog Timer Value Register */ > -#define AT91_SAM9X60_VR 0x08 > +#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) > +#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) > > -/* Watchdog Window Level Register */ > -#define AT91_SAM9X60_WLR 0x0c > -/* Watchdog Period Value */ > -#define AT91_SAM9X60_COUNTER (0xfffUL << 0) > -#define AT91_SAM9X60_SET_COUNTER(x) ((x) & AT91_SAM9X60_COUNTER) > +#define AT91_WDT_VR 0x08 /* Watchdog Timer Value Register */ > +#define AT91_WDT_ISR 0x1c /* Interrupt Status Register */ > +#define AT91_WDT_IER 0x14 /* Interrupt Enable Register */ > +#define AT91_WDT_IDR 0x18 /* Interrupt Disable Register */ > +#define AT91_WDT_WLR 0x0c /* Watchdog Window Level Register */ > +#define AT91_WDT_PERIODRST BIT(4) /* Period Reset */ > +#define AT91_WDT_RPTHRST BIT(5) /* Minimum Restart Period */ > +#define AT91_WDT_PERINT BIT(0) /* Period Interrupt Enable */ > +#define AT91_WDT_COUNTER (0xfffUL << 0) /* Watchdog Period Value */ > +#define AT91_WDT_SET_COUNTER(x) ((x) & AT91_WDT_COUNTER) > > -/* Interrupt Enable Register */ > -#define AT91_SAM9X60_IER 0x14 > -/* Period Interrupt Enable */ > -#define AT91_SAM9X60_PERINT BIT(0) > -/* Interrupt Disable Register */ > -#define AT91_SAM9X60_IDR 0x18 > -/* Interrupt Status Register */ > -#define AT91_SAM9X60_ISR 0x1c > +/* > + * WDDIS bit differs by SoC: > + * - SAMA5, AT91SAM9261: bit 15 > + * - SAM9X60, SAMA7G5, SAM9X75: bit 12 > + * Select at runtime via compatible string. > + */ > +#define AT91_WDT_WDDIS_LEGACY BIT(15) > +#define AT91_WDT_WDDIS_MODERN BIT(12) This is bad naming, we are going to end up with AT91_WDT_WDDIS_LEGACY_LEGACY, AT91_WDT_WDDIS_MODERN_LEGACY and AT91_WDT_WDDIS_MODERN next time. The proper name would use the name of the SoC introducing the new position. > > #endif > -- > 2.34.1 > -- Alexandre Belloni, co-owner and COO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com