From: Chen-Yu Tsai <wens@kernel.org>
To: Chen-Yu Tsai <wens@kernel.org>,
Jernej Skrabec <jernej@kernel.org>,
Samuel Holland <samuel@sholland.org>,
Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org,
linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Jernej Skrabec <jernej.skrabec@gmail.com>
Subject: [PATCH v2 2/3] arm64: dts: allwinner: sun55i-a523: Add pinmux for spi0 on PJ pins
Date: Mon, 2 Mar 2026 23:35:57 +0800 [thread overview]
Message-ID: <20260302153559.3199783-3-wens@kernel.org> (raw)
In-Reply-To: <20260302153559.3199783-1-wens@kernel.org>
The Avaota A1 board uses spi0 on the PJ pins to connect a SPI NAND
chip.
Add the full set of pins. Even though this board doesn't use CS1, other
boards may do so in the future.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
---
.../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 92aecb90d4e1..da85cecb66c0 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -228,6 +228,13 @@ spi0_pc_pins: spi0-pc-pins {
allwinner,pinmux = <4>;
};
+ /omit-if-no-ref/
+ spi0_pj_pins: spi0-pj-pins {
+ pins = "PJ21", "PJ22", "PJ23";
+ function = "spi0";
+ allwinner,pinmux = <5>;
+ };
+
/omit-if-no-ref/
spi0_cs0_pc_pin: spi0-cs0-pc-pin {
pins = "PC3";
@@ -235,6 +242,13 @@ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
allwinner,pinmux = <4>;
};
+ /omit-if-no-ref/
+ spi0_cs0_pj_pin: spi0-cs0-pj-pin {
+ pins = "PJ20";
+ function = "spi0";
+ allwinner,pinmux = <5>;
+ };
+
/omit-if-no-ref/
spi0_cs1_pc_pin: spi0-cs1-pc-pin {
pins = "PC7";
@@ -242,6 +256,13 @@ spi0_cs1_pc_pin: spi0-cs1-pc-pin {
allwinner,pinmux = <4>;
};
+ /omit-if-no-ref/
+ spi0_cs1_pj_pin: spi0-cs1-pj-pin {
+ pins = "PJ24";
+ function = "spi0";
+ allwinner,pinmux = <5>;
+ };
+
/omit-if-no-ref/
spi0_hold_pc_pin: spi0-hold-pc-pin {
/* conflicts with eMMC D7 */
@@ -250,6 +271,13 @@ spi0_hold_pc_pin: spi0-hold-pc-pin {
allwinner,pinmux = <4>;
};
+ /omit-if-no-ref/
+ spi0_hold_pj_pin: spi0-hold-pj-pin {
+ pins = "PJ26";
+ function = "spi0";
+ allwinner,pinmux = <5>;
+ };
+
/omit-if-no-ref/
spi0_wp_pc_pin: spi0-wp-pc-pin {
/* conflicts with eMMC D2 */
@@ -258,6 +286,13 @@ spi0_wp_pc_pin: spi0-wp-pc-pin {
allwinner,pinmux = <4>;
};
+ /omit-if-no-ref/
+ spi0_wp_pj_pin: spi0-wp-pj-pin {
+ pins = "PJ25";
+ function = "spi0";
+ allwinner,pinmux = <5>;
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
allwinner,pinmux = <2>;
--
2.47.3
next prev parent reply other threads:[~2026-03-02 15:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 15:35 [PATCH v2 0/3] arm64: allwinner: sun55i-t527: avaota-a1: Add SPI NAND Chen-Yu Tsai
2026-03-02 15:35 ` [PATCH v2 1/3] spi: dt-bindings: sun6i: Allow Dual SPI and Quad SPI for newer SoCs Chen-Yu Tsai
2026-03-02 15:35 ` Chen-Yu Tsai [this message]
2026-03-02 15:35 ` [PATCH v2 3/3] arm64: dts: allwinner: sun55i-t527: avaota-a1: Add SPI NAND Chen-Yu Tsai
2026-03-10 19:41 ` [PATCH v2 0/3] arm64: " Chen-Yu Tsai
2026-03-10 19:42 ` Mark Brown
2026-03-10 19:44 ` Chen-Yu Tsai
2026-03-10 19:47 ` Mark Brown
2026-03-10 19:49 ` Chen-Yu Tsai
2026-03-11 18:57 ` (subset) " Mark Brown
2026-03-14 21:59 ` Mark Brown
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