From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37EA3D58E48 for ; Mon, 2 Mar 2026 16:58:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=yqJk7rYnuDyozvN+TtrMWyCy0G9Ky0Mjgcfz2sX6lvw=; b=2WdSGnPXkNwoRqWoeOOPHjCjZl GRhm5GXH9Cmm5+ZqsFZwM+hyfkIeIodq1pjcCpGExWooAvC91aXBn9wM1oRAJl3GvXT8uQMJKNKKT QblnsAXCQUXIwJsDer5P2cc+Vtspaq/6JJQ9PImE+qq8mJtAsUviT6wvx+rWll6JRiFZGQgGxtAPp FSCr+SU41a8wfS+glsn/9cCzIVHe65RCla6T6EVlNwR4X/7MfBAATJWo/LvqoqSVNqMOzvOYVmBWe wPLrWY+Br/CJRuBdVhdvYV9P3beub0LbqmxpyZBVReFJKNrpKg5plwglNiHc1asNXWFVmM9gl/mML TG+Hz8ug==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vx6b6-0000000DXir-1dDW; Mon, 02 Mar 2026 16:58:20 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vx6b3-0000000DXgd-2cG4 for linux-arm-kernel@lists.infradead.org; Mon, 02 Mar 2026 16:58:19 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 54B6843D1D; Mon, 2 Mar 2026 16:58:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18CE3C2BC86; Mon, 2 Mar 2026 16:58:14 +0000 (UTC) From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org Cc: Will Deacon , Marc Zyngier , Oliver Upton , Lorenzo Pieralisi , Sudeep Holla , James Morse , Mark Rutland , Mark Brown , kvmarm@lists.linux.dev Subject: [PATCH 4/4] KVM: arm64: Add SMC hook for SME dvmsync erratum Date: Mon, 2 Mar 2026 16:57:57 +0000 Message-ID: <20260302165801.3014607-5-catalin.marinas@arm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302165801.3014607-1-catalin.marinas@arm.com> References: <20260302165801.3014607-1-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260302_085817_713118_FDE36714 X-CRM114-Status: GOOD ( 15.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: James Morse C1-Pro cores with SME have an erratum where TLBI+DSB does not complete all outstanding SME accesses. Instead a DSB needs to be executed on the affecteed CPUs. The implication is pages cannot be unmapped from the host stage2 then provided to the guest. Host SME accesses may occur after this point. This erratum breaks pKVM's guarantees, and the workaround is hard to implement as EL2 and EL1 share a security state meaning EL1 can mask IPI sent by EL2, leading to interrupt blackouts. Instead, do this in EL3. This has the advantage of a separate security state, meaning lower EL cannot mask the IPI. It is also simpler for EL3 to know about CPUs that are off or in PSCI's CPU_SUSPEND. Add the needed hook. Signed-off-by: James Morse Signed-off-by: Catalin Marinas Cc: Marc Zyngier Cc: Oliver Upton Cc: Will Deacon Cc: Mark Rutland Cc: Lorenzo Pieralisi Cc: Sudeep Holla --- arch/arm64/kvm/hyp/nvhe/mem_protect.c | 17 +++++++++++++++++ include/linux/arm-smccc.h | 5 +++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c index 38f66a56a766..ab7f9273fddf 100644 --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c @@ -5,6 +5,8 @@ */ #include +#include + #include #include #include @@ -28,6 +30,15 @@ static struct hyp_pool host_s2_pool; static DEFINE_PER_CPU(struct pkvm_hyp_vm *, __current_vm); #define current_vm (*this_cpu_ptr(&__current_vm)) +static void pkvm_sme_dvmsync_fw_call(void) +{ + if (cpus_have_final_cap(ARM64_WORKAROUND_SME_DVMSYNC)) { + struct arm_smccc_res res; + + arm_smccc_1_1_smc(ARM_SMCCC_CPU_SME_DVMSYNC_WORKAROUND, &res); + } +} + static void guest_lock_component(struct pkvm_hyp_vm *vm) { hyp_spin_lock(&vm->lock); @@ -553,6 +564,12 @@ int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id) if (ret) return ret; + /* + * After stage2 maintenance has happened, but before the page owner has + * changed. + */ + pkvm_sme_dvmsync_fw_call(); + /* Don't forget to update the vmemmap tracking for the host */ if (owner_id == PKVM_ID_HOST) __host_update_page_state(addr, size, PKVM_PAGE_OWNED); diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 50b47eba7d01..3489db78b0bd 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -105,6 +105,11 @@ ARM_SMCCC_SMC_32, \ 0, 0x3fff) +#define ARM_SMCCC_CPU_SME_DVMSYNC_WORKAROUND \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_CPU, 0x10) + #define ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ARM_SMCCC_SMC_32, \