From: Leo Yan <leo.yan@arm.com>
To: Will Deacon <will@kernel.org>
Cc: kvmarm@lists.linux.dev, mark.rutland@arm.com,
linux-arm-kernel@lists.infradead.org,
Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
James Clark <james.clark@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Fuad Tabba <tabba@google.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Yabin Cui <yabinc@google.com>
Subject: Re: [PATCH v2 1/3] KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context
Date: Tue, 3 Mar 2026 17:39:56 +0000 [thread overview]
Message-ID: <20260303173956.GI1098637@e132581.arm.com> (raw)
In-Reply-To: <20260227212136.7660-2-will@kernel.org>
On Fri, Feb 27, 2026 at 09:21:33PM +0000, Will Deacon wrote:
> The nVHE world-switch code relies on zeroing TRFCR_EL1 to disable trace
> generation in guest context when self-hosted TRBE is in use by the host.
>
> Per D3.2.1 ("Controls to prohibit trace at Exception levels"), clearing
> TRFCR_EL1 means that trace generation is prohibited at EL1 and EL0 but
> per R_YCHKJ the Trace Buffer Unit will still be enabled if
> TRBLIMITR_EL1.E is set. R_SJFRQ goes on to state that, when enabled, the
> Trace Buffer Unit can perform address translation for the "owning
> exception level" even when it is out of context.
>
> Consequently, we can end up in a state where TRBE performs speculative
> page-table walks for a host VA/IPA in guest/hypervisor context depending
> on the value of MDCR_EL2.E2TB, which changes over world-switch. The
> potential result appears to be a heady mixture of SErrors, data
> corruption and hardware lockups.
>
> Extend the TRBE world-switch code to clear TRBLIMITR_EL1.E after
> draining the buffer, restoring the register on return to the host. This
> unfortunately means we need to tackle CPU errata #2064142 and #2038923
> which add additional synchronisation requirements around manipulations
> of the limit register. Hopefully this doesn't need to be fast.
>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oupton@kernel.org>
> Cc: James Clark <james.clark@linaro.org>
> Cc: Leo Yan <leo.yan@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Fuad Tabba <tabba@google.com>
> Cc: Alexandru Elisei <alexandru.elisei@arm.com>
> Fixes: a1319260bf62 ("arm64: KVM: Enable access to TRBE support for host")
> Signed-off-by: Will Deacon <will@kernel.org>
I tested this on my Orion6 board in nVHE mode (kvm-arm.mode=nvhe).
I launched a VM with several threads running sleep 0.1 in a loop inside
the VM shell. Then, I collected TRBE trace data on the host side:
$ perf record -e cs_etm// -a -- sleep 100
[ perf record: Woken up 74 times to write data ]
Warning:
Processed 4798137 events and lost 4 chunks!
Check IO/CPU overload!
Warning:
Processed 9608 samples and lost 100.00%!
Failed to open /proc/schedstat
[ perf record: Captured and wrote 42401.333 MB perf.data ]
Tested-by: Leo Yan <leo.yan@arm.com>
next prev parent reply other threads:[~2026-03-03 17:40 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-27 21:21 [PATCH v2 0/3] KVM: arm64: Fix SPE and TRBE nVHE world switch Will Deacon
2026-02-27 21:21 ` [PATCH v2 1/3] KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context Will Deacon
2026-03-03 9:23 ` Suzuki K Poulose
2026-03-03 17:39 ` Leo Yan [this message]
2026-03-25 19:27 ` Fuad Tabba
2026-03-26 12:49 ` Will Deacon
2026-02-27 21:21 ` [PATCH v2 2/3] KVM: arm64: Disable SPE Profiling Buffer " Will Deacon
2026-03-03 9:48 ` Suzuki K Poulose
2026-03-03 14:39 ` Will Deacon
2026-03-03 15:01 ` Suzuki K Poulose
2026-03-25 16:34 ` Alexandru Elisei
2026-03-25 19:28 ` Fuad Tabba
2026-02-27 21:21 ` [PATCH v2 3/3] KVM: arm64: Don't pass host_debug_state to BRBE world-switch routines Will Deacon
2026-03-25 19:28 ` Fuad Tabba
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