From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E120F47CAD for ; Thu, 5 Mar 2026 18:09:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Subject: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Cc:To:From:Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=OPlku5o6NmWNt5xE1J8XWlwRvWxXMHrbYsyBJHmoHWE=; b=DrXdkoCzjOe9PJnJlHor0TS/CJ A7N4wRsywTdQK2WC8kEUw5/QKxemf3QdGhNqHcKHCJ57FpQ0X63dvbk5EH5dfwSYT9u3ay0ug4dA/ 29z/E54jfEimam/NJNS8fWLzX+PQBrD26jt2yqY4VMPcL0eoQh/wvfyHkw3oaSw4jnn7o3iDY6Ooj jbQNr+mR+xieS+Me47ZpzHjHzk38uczRLUHjuRPOMyl0tl1kOGrsos3yA7mO7wsqZIx3vcn9Pts2o sGdHUrildWcehYNEXH4ec1NlFhL7lAq7PmPnP768yqA59oGFTpM461lbY1aHhQOCnW5OYSWwRLcS3 KdP0oIAQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vyD8E-00000002Lnx-1vYb; Thu, 05 Mar 2026 18:09:06 +0000 Received: from mail.hugovil.com ([162.243.120.170]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vyD8B-00000002Li6-0btG for linux-arm-kernel@lists.infradead.org; Thu, 05 Mar 2026 18:09:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=OPlku5o6NmWNt5xE1J8XWlwRvWxXMHrbYsyBJHmoHWE=; b=L6NmrfgWcIhLOxk7csggSdHBP2 Tk85P3tMNcFM1TKsSeivGAl2gNHNSsHC7Oy8KspxMqMRDngkHqhUtyaLUtOBZtE+rF4UHeoYXfAob gchY+s0JeX1lWnkcjoLZKBXd6glNgQ7i1QaN4JV/F7eXmdF7TAkHnE7aDMSJhfZlMhlc=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:37706 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vyD80-0002aR-CK; Thu, 05 Mar 2026 13:08:53 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:27 -0500 Message-ID: <20260305180651.1827087-13-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305180651.1827087-1-hugo@hugovil.com> References: <20260305180651.1827087-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH v2 12/15] ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1) X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260305_100903_280185_A3F35F32 X-CRM114-Status: GOOD ( 21.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Hugo Villeneuve ENET1 is currently disabled and not supported/working on the concerto EVK. Add support for this optional configuration in a separate dtsi, so that it can be selectively enabled/disabled. Signed-off-by: Hugo Villeneuve --- In order for this to work, imx6ul-var-som-enet2.dtsi must be included first, and thus enabled, even if not used. Maybe there is a better way to support both independantly, but I'm not sure how. --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 50 ------------------- .../imx/imx6ul-var-som-concerto-common.dtsi | 4 -- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-enet1.dtsi | 44 ++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi | 11 ++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 6 +++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 6 +++ 8 files changed, 69 insertions(+), 54 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index af9b92f7709b4..70d19eccddb4c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -44,57 +44,7 @@ &clks { assigned-clock-rates = <786432000>; }; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <1>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - &iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet1_gpio: enet1-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index fead54ac8c6b9..f099ca5d0e8f0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -52,10 +52,6 @@ &can1 { status = "okay"; }; -&fec1 { - status = "disabled"; -}; - &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 3905171b47b32..b5e6a3306e1cd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi new file mode 100644 index 0000000000000..6b1e34347bec7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ethernet ENET1 support for Variscite VAR-SOM-6UL module with + * the EC configuration option ((ethernet PHY assembled on SOM). + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; +}; + +&mdio_enet2 { + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi index 334ed3bbe02ce..b29fcdc079e37 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi @@ -26,6 +26,17 @@ mdio_enet2: mdio { #address-cells = <1>; #size-cells = <0>; + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; + ethphy1: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index b4e6a9316dd81..feea24c0e0683 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -29,4 +29,10 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 89b6032203a28..86f558c76fb3e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi index 3067ff6a1bc74..f120b1dca75ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -27,4 +27,10 @@ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; -- 2.47.3