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Mon, 09 Mar 2026 05:05:21 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 9 Mar 2026 20:05:18 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 9 Mar 2026 20:05:18 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Richard Cochran , Bartosz Golaszewski , Chen-Yu Tsai , Miles Chen CC: , , , , , , , Qiqi Wang , , , , Subject: [PATCH v6 10/18] clk: mediatek: Add MT8189 dvfsrc clock support Date: Mon, 9 Mar 2026 20:04:52 +0800 Message-ID: <20260309120512.3624804-11-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260309120512.3624804-1-irving-ch.lin@mediatek.com> References: <20260309120512.3624804-1-irving-ch.lin@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260309_120533_626542_10DC8420 X-CRM114-Status: GOOD ( 18.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Irving-CH Lin Add support for the MT8189 dvfsrc clock controller, which provides clock gate control for dram dvfs. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 10 +++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dvfsrc.c | 54 ++++++++++++++++++++++++ 3 files changed, 65 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-dvfsrc.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 89f68cb56bb3..5def42855b62 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -860,6 +860,16 @@ config COMMON_CLK_MT8189_DBGAO vcore debug system clocks. If you want to control its clocks, say Y or M to include this driver in your kernel build. +config COMMON_CLK_MT8189_DVFSRC + tristate "Clock driver for MediaTek MT8189 dvfsrc" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the dvfsrc + on MediaTek MT8189 SoCs. This includes enabling and disabling + vcore dvfs clocks. If you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index eabe2cab4b8d..3a8dad865c97 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -128,6 +128,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o obj-$(CONFIG_COMMON_CLK_MT8189_CAM) += clk-mt8189-cam.o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o +obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dvfsrc.c b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c new file mode 100644 index 000000000000..f8ab656af6e6 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs dvfsrc_top_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +#define GATE_DVFSRC_TOP_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &dvfsrc_top_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, _flags) + +static const struct mtk_gate dvfsrc_top_clks[] = { + GATE_DVFSRC_TOP_FLAGS(CLK_DVFSRC_TOP_DVFSRC_EN, "dvfsrc_dvfsrc_en", + "clk26m", 0, CLK_IS_CRITICAL), +}; + +static const struct mtk_clk_desc dvfsrc_top_mcd = { + .clks = dvfsrc_top_clks, + .num_clks = ARRAY_SIZE(dvfsrc_top_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dvfsrc[] = { + { .compatible = "mediatek,mt8189-dvfsrc-top", .data = &dvfsrc_top_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dvfsrc); + +static struct platform_driver clk_mt8189_dvfsrc_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8189-dvfsrc", + .of_match_table = of_match_clk_mt8189_dvfsrc, + }, +}; + +module_platform_driver(clk_mt8189_dvfsrc_drv); +MODULE_DESCRIPTION("MediaTek MT8189 dvfsrc clocks driver"); +MODULE_LICENSE("GPL"); -- 2.45.2