From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA48DFED2CC for ; Thu, 12 Mar 2026 04:21:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XWT9nqwLuvjnCTg1wstFXwMoVH05aJNdEDwKXs7mmXc=; b=nk090O1EMeZvbm4UcWKESbSVzB nqsoONOMoVGn3Vtjb1DdAsNY57UkD8zLhf0wtUaGbdLB+dPczp6UYz1+CuIZRmdbqp/kPb1gBhh1K d3zIXO3dzg/LODFdkwFh5KLBqMK5xxPmd8TgsyIeNaT55zkWBHzaD1sJpiVtuRKUWWPGzV1ojQcvD ynVHhsbL4F2mbDXvG+bNo5r/cf9MPH8sjQqOhOvSjOsJqVMwEDH/UMo/ks1wWWYt9eoLQ6wYa/lP/ tUxdSYi9JAygQE4qst+GMxjpXGqO8xBLsT9zD2w3dcxbDraTttzDzFodo2MUxa/VkQJP7k7p+yzjw bVr6hnGw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w0XYP-0000000DFIh-3kDB; Thu, 12 Mar 2026 04:21:45 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1w0XYM-0000000DFHh-3xOG; Thu, 12 Mar 2026 04:21:44 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773289302; x=1804825302; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mfapho4KyK74MRDmiN5G9sod8x6U/8WWa0F9VXk3Lfo=; b=J0YqbX+FSICXi1FGf3GDsa/9vF+1bxMMH2C1j9kQfJRel8KMAxttVPhz a9TmfL1QN5/0DwiSLM3Qo7vRGArrzdxPn/uKSUs9Oi0M0z+M3seEXzHJI bLThggA6wA5hsFrTozCQFq1PyUVsQ8jzBpn5gCX+Y2wNC1GQ9yFPI8R6K KkHGkih7Y0O5xm/qhKI+VVineOMP7qiG2W+LIazUXZ3blALZYJX0ENDhR 6wdreaz2SKxEx2GGFefc67ZLJWQyAEXvn1wlUXOdiB49p3CdTgf608Nrf aoipgI2x4hE7kYCwsPyTIHxSL/x0VcfMsGRNTC6YuDkJLcDplrz2rvSw4 Q==; X-CSE-ConnectionGUID: fvtvzCBGTY2f4cyuaBkSKA== X-CSE-MsgGUID: hKcz80kJRvGUhvYdZ4CKGQ== X-IronPort-AV: E=Sophos;i="6.23,115,1770620400"; d="scan'208";a="54551532" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 11 Mar 2026 21:21:39 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 11 Mar 2026 21:21:39 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 11 Mar 2026 21:21:30 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v3 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the appropriate quirk Date: Thu, 12 Mar 2026 09:50:54 +0530 Message-ID: <20260312042056.309237-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260312042056.309237-1-manikandan.m@microchip.com> References: <20260312042056.309237-1-manikandan.m@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260311_212143_019946_6175D2C7 X-CRM114-Status: GOOD ( 17.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for microchip sama7d65 SoC I3C HCI master only IP with additional clock support to enable bulk clock acquisition for Microchip platforms using HCI_QUIRK_CLK_SUPPORT quirk. Introduce MCHP_I3C_CLK_IDX to define the maximum peripheral clock index Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Make use of existing HCI_QUIRK_* code base - Introduce HCI_QUIRK_CLK_SUPPORT to handle/enable the required Peripheral and system generic clk in bulk Changes in v2: - Platform specific changes are integrated in the existing mipi-i3c-hci driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor specific quirk files --- drivers/i3c/master/mipi-i3c-hci/core.c | 12 ++++++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index 5879bba78164..6b7716bd517e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -918,6 +919,7 @@ static int i3c_hci_probe(struct platform_device *pdev) { const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data; struct i3c_hci *hci; + struct clk_bulk_data *clks; int irq, ret; hci = devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL); @@ -946,6 +948,13 @@ static int i3c_hci_probe(struct platform_device *pdev) if (!hci->quirks && platform_get_device_id(pdev)) hci->quirks = platform_get_device_id(pdev)->driver_data; + if (hci->quirks & HCI_QUIRK_CLK_SUPPORT) { + ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < MCHP_I3C_CLK_IDX) + return dev_err_probe(&pdev->dev, ret, + "Failed to get clocks\n"); + } + ret = i3c_hci_init(hci); if (ret) return ret; @@ -971,6 +980,9 @@ static void i3c_hci_remove(struct platform_device *pdev) static const __maybe_unused struct of_device_id i3c_hci_of_match[] = { { .compatible = "mipi-i3c-hci", }, + { .compatible = "microchip,sama7d65-i3c-hci", + .data = (void *)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | + HCI_QUIRK_RESP_BUF_THLD | HCI_QUIRK_CLK_SUPPORT) }, {}, }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index 337b7ab1cb06..2571ef6374ce 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -140,12 +140,16 @@ struct i3c_hci_dev_data { void *ibi_data; }; +#define MCHP_I3C_CLK_IDX 2 /* Max peripheral clock index for Microchip platforms */ + /* list of quirks */ #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ #define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ +#define HCI_QUIRK_CLK_SUPPORT BIT(6) /* Enable Clocks for Microchip platforms*/ + /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); -- 2.25.1