* [PATCH v4 01/10] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 19:15 ` Frank Li
2026-03-13 14:20 ` [PATCH v4 02/10] arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit Josua Mayer
` (8 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer, stable
Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
support bus recovery") introduced pinmux nodes for lx2160 i2c
interfaces, allowing runtime change between i2c and gpio functions
implementing bus recovery.
This has caused unintended side-effects on SolidRun boards where the
first application of a pinmux node cleared all bits in a 32-bit word,
corrupting the configuration previously set by bootloader.
The LX2160 SoC is configured at power-on from RCW (Reset
Configuration Word) typically located in the first 4k of boot media.
This blob configures various clock rates and pin functions.
The pinmux for i2c specifically is part of configuration words RCWSR12,
RCWSR13 and RCWSR14 size 32 bit each.
These values are accessible at read-only addresses 0x01e0012c following.
For runtime (re-)configuration the SoC has a dynamic configuration area
where alternative settings can be applied. The counterparts of
RCWSR[12-14] can be overridden at 0x70010012c following.
The commit in question used this area to switch i2c pins between i2c and
gpio function at runtime using the pinctrl-single driver - which reads a
32-bit value, makes particular changes by bitmask and writes back the
new value.
SolidRun have observed that if the dynamic configuration is read first
(before a write), it reads as zero regardless the initial values set by
RCW. After the first write consecutive reads reflect the written value.
Because multiple pins are configured from a single 32-bit value, this
causes unintentional change of all bits (except those for i2c) being set
to zero when the pinctrl driver applies the first configuration.
See below a short list of which functions RCWSR12 alone controls:
LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
IIC3_PMUX ||| ||| || | ||| XXX : I2C/GPIO/CAN/EVT
IIC4_PMUX ||| ||| || | |||XXX||| : I2C/GPIO/CAN/EVT
IIC5_PMUX ||| ||| || | XXX ||| : I2C/GPIO/SDHC-CLK
IIC6_PMUX ||| ||| || |XXX||| ||| : I2C/GPIO/SDHC-CLK
XSPI1_A_DATA74_PMUX ||| ||| XX X ||| ||| : XSPI/GPIO
XSPI1_A_DATA30_PMUX ||| |||XXX|| | ||| ||| : XSPI/GPIO
XSPI1_A_BASE_PMUX ||| XXX || | ||| ||| : XSPI/GPIO
SDHC1_BASE_PMUX |||XXX||| || | ||| ||| : SDHC/GPIO/SPI
SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
RESERVED XX||| ||| || | ||| ||| :
On LX2162A Clearfog the initial (and intended) value is 0x08000006 -
enabling card-detect on IIC2_PMUX and control GPIOs on SDHC1_DIR_PMUX.
Everything else is intentional zero (enabling I2C & XSPI).
By reading zero from dynamic configuration area, the commit in question
changes IIC2_PMUX to value 0 (I2C function), and SDHC1_DIR_PMUX to 0
(SDHC data direction function) - breaking card-detect and led gpios.
This issue should affect any board based on LX2160 SoC that is using the
same or earlier versions of NXP bootloader as SolidRun have tested, in
particular: LSDK-21.08 and LS-5.15.71-2.2.0.
Whether NXP added some extra initialisation in the bootloader on later
releases was not investigated. However bootloader upgrade should not be
necessary to run a newer Linux kernel.
To work around this issue it is possible to explicitly define ALL pins
controlled by any 32-bit value so that gradually after processing all
pinctrl nodes the correct value is reached on all bits.
This is a large task that should be done carefully on a per-board basis
and not globally through the SoC dtsi.
Therefore reverting the commit in question altogether was considered,
but received pushback in review with the argument that bus recovery was
important.
Instead add pinmux nodes for all fields of rcwsr12 as used by affected
SolidRun LX2160A Clearfog-CX & Honeycomb, and LX2162A Clearfog boards.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Cc: stable@vger.kernel.org
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 7 +++++++
.../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 ++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++++++++++++++++++++++
.../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 ++
.../boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 7 +++++++
5 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index eec2cd6c6d32a..7f6e39e27ce5c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -162,6 +162,8 @@ rtc@51 {
};
&fspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
status = "okay";
flash@0 {
@@ -177,6 +179,11 @@ flash@0 {
};
};
+&pinmux_i2crv {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_14_12_pins>;
+};
+
&usb0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index af6258b2fe826..580ee9b3026e3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -89,6 +89,8 @@ &emdio2 {
};
&esdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 853b01452813a..af74e77efabc5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1721,6 +1721,10 @@ i2c1_scl_gpio: i2c1-scl-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
+ esdhc0_cd_wp_pins: iic2-sdhc-pins {
+ pinctrl-single,bits = <0x0 0x6 0x7>;
+ };
+
i2c2_scl: i2c2-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
@@ -1753,6 +1757,26 @@ i2c5_scl_gpio: i2c5-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
+ fspi_data74_pins: xspi1-data74-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
+ };
+
+ fspi_data30_pins: xspi1-data30-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
+ };
+
+ fspi_dqs_sck_cs10_pins: xspi1-base-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
+ };
+
+ esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
+ };
+
+ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
+ pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
+ };
+
i2c6_scl: i2c6-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index eafef8718a0fe..8920326a06735 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -223,6 +223,8 @@ ethernet_phy8: ethernet-phy@15 {
};
&esdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
index e914291e63a1a..e1344942eaaee 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
@@ -30,6 +30,8 @@ &esdhc1 {
};
&fspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
status = "okay";
flash@0 {
@@ -80,3 +82,8 @@ rtc@6f {
reg = <0x6f>;
};
};
+
+&pinmux_i2crv {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_14_12_pins>;
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 01/10] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
2026-03-13 14:20 ` [PATCH v4 01/10] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux Josua Mayer
@ 2026-03-13 19:15 ` Frank Li
2026-03-14 12:04 ` Josua Mayer
0 siblings, 1 reply; 14+ messages in thread
From: Frank Li @ 2026-03-13 19:15 UTC (permalink / raw)
To: Josua Mayer
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Carlos Song, Mikhail Anikin, Yazan Shhady, Rabeeh Khoury,
linux-arm-kernel, devicetree, linux-kernel, stable
On Fri, Mar 13, 2026 at 03:20:42PM +0100, Josua Mayer wrote:
> Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
> support bus recovery") introduced pinmux nodes for lx2160 i2c
> interfaces, allowing runtime change between i2c and gpio functions
> implementing bus recovery.
>
> This has caused unintended side-effects on SolidRun boards where the
> first application of a pinmux node cleared all bits in a 32-bit word,
> corrupting the configuration previously set by bootloader.
>
> The LX2160 SoC is configured at power-on from RCW (Reset
> Configuration Word) typically located in the first 4k of boot media.
> This blob configures various clock rates and pin functions.
> The pinmux for i2c specifically is part of configuration words RCWSR12,
> RCWSR13 and RCWSR14 size 32 bit each.
> These values are accessible at read-only addresses 0x01e0012c following.
>
> For runtime (re-)configuration the SoC has a dynamic configuration area
> where alternative settings can be applied. The counterparts of
> RCWSR[12-14] can be overridden at 0x70010012c following.
>
> The commit in question used this area to switch i2c pins between i2c and
> gpio function at runtime using the pinctrl-single driver - which reads a
> 32-bit value, makes particular changes by bitmask and writes back the
> new value.
>
> SolidRun have observed that if the dynamic configuration is read first
> (before a write), it reads as zero regardless the initial values set by
> RCW. After the first write consecutive reads reflect the written value.
>
> Because multiple pins are configured from a single 32-bit value, this
> causes unintentional change of all bits (except those for i2c) being set
> to zero when the pinctrl driver applies the first configuration.
>
> See below a short list of which functions RCWSR12 alone controls:
>
> LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
> IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
> IIC3_PMUX ||| ||| || | ||| XXX : I2C/GPIO/CAN/EVT
> IIC4_PMUX ||| ||| || | |||XXX||| : I2C/GPIO/CAN/EVT
> IIC5_PMUX ||| ||| || | XXX ||| : I2C/GPIO/SDHC-CLK
> IIC6_PMUX ||| ||| || |XXX||| ||| : I2C/GPIO/SDHC-CLK
> XSPI1_A_DATA74_PMUX ||| ||| XX X ||| ||| : XSPI/GPIO
> XSPI1_A_DATA30_PMUX ||| |||XXX|| | ||| ||| : XSPI/GPIO
> XSPI1_A_BASE_PMUX ||| XXX || | ||| ||| : XSPI/GPIO
> SDHC1_BASE_PMUX |||XXX||| || | ||| ||| : SDHC/GPIO/SPI
> SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
> RESERVED XX||| ||| || | ||| ||| :
List two IIC2_PMUX and SDHC1_DIR_PMUX should be enough.
>
> On LX2162A Clearfog the initial (and intended) value is 0x08000006 -
> enabling card-detect on IIC2_PMUX and control GPIOs on SDHC1_DIR_PMUX.
> Everything else is intentional zero (enabling I2C & XSPI).
>
> By reading zero from dynamic configuration area, the commit in question
> changes IIC2_PMUX to value 0 (I2C function), and SDHC1_DIR_PMUX to 0
> (SDHC data direction function) - breaking card-detect and led gpios.
>
> This issue should affect any board based on LX2160 SoC that is using the
> same or earlier versions of NXP bootloader as SolidRun have tested, in
> particular: LSDK-21.08 and LS-5.15.71-2.2.0.
>
> Whether NXP added some extra initialisation in the bootloader on later
> releases was not investigated. However bootloader upgrade should not be
> necessary to run a newer Linux kernel.
>
> To work around this issue it is possible to explicitly define ALL pins
> controlled by any 32-bit value so that gradually after processing all
> pinctrl nodes the correct value is reached on all bits.
>
> This is a large task that should be done carefully on a per-board basis
> and not globally through the SoC dtsi.
> Therefore reverting the commit in question altogether was considered,
> but received pushback in review with the argument that bus recovery was
> important.
>
> Instead add pinmux nodes for all fields of rcwsr12 as used by affected
> SolidRun LX2160A Clearfog-CX & Honeycomb, and LX2162A Clearfog boards.
Thanks you very much. This way is the good. But commit message to too long
Basically the default value of overwrite MUX is 0, which have not reflact
hardware real status, which set by RCW. so update some field of mux impact
other peripherial.
Frank
>
> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
> Cc: stable@vger.kernel.org
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> .../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 7 +++++++
> .../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 ++
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++++++++++++++++++++++
> .../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 ++
> .../boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 7 +++++++
> 5 files changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
> index eec2cd6c6d32a..7f6e39e27ce5c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
> @@ -162,6 +162,8 @@ rtc@51 {
> };
>
> &fspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
> status = "okay";
>
> flash@0 {
> @@ -177,6 +179,11 @@ flash@0 {
> };
> };
>
> +&pinmux_i2crv {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio0_14_12_pins>;
> +};
> +
> &usb0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
> index af6258b2fe826..580ee9b3026e3 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
> @@ -89,6 +89,8 @@ &emdio2 {
> };
>
> &esdhc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
> sd-uhs-sdr104;
> sd-uhs-sdr50;
> sd-uhs-sdr25;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 853b01452813a..af74e77efabc5 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -1721,6 +1721,10 @@ i2c1_scl_gpio: i2c1-scl-gpio-pins {
> pinctrl-single,bits = <0x0 0x1 0x7>;
> };
>
> + esdhc0_cd_wp_pins: iic2-sdhc-pins {
> + pinctrl-single,bits = <0x0 0x6 0x7>;
> + };
> +
> i2c2_scl: i2c2-scl-pins {
> pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
> };
> @@ -1753,6 +1757,26 @@ i2c5_scl_gpio: i2c5-scl-gpio-pins {
> pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
> };
>
> + fspi_data74_pins: xspi1-data74-pins {
> + pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
> + };
> +
> + fspi_data30_pins: xspi1-data30-pins {
> + pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
> + };
> +
> + fspi_dqs_sck_cs10_pins: xspi1-base-pins {
> + pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
> + };
> +
> + esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
> + pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
> + };
> +
> + gpio0_14_12_pins: sdhc1-dir-gpio-pins {
> + pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
> + };
> +
> i2c6_scl: i2c6-scl-pins {
> pinctrl-single,bits = <0x4 0x2 0x7>;
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> index eafef8718a0fe..8920326a06735 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> @@ -223,6 +223,8 @@ ethernet_phy8: ethernet-phy@15 {
> };
>
> &esdhc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
> sd-uhs-sdr104;
> sd-uhs-sdr50;
> sd-uhs-sdr25;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
> index e914291e63a1a..e1344942eaaee 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
> @@ -30,6 +30,8 @@ &esdhc1 {
> };
>
> &fspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
> status = "okay";
>
> flash@0 {
> @@ -80,3 +82,8 @@ rtc@6f {
> reg = <0x6f>;
> };
> };
> +
> +&pinmux_i2crv {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio0_14_12_pins>;
> +};
>
> --
> 2.51.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v4 01/10] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
2026-03-13 19:15 ` Frank Li
@ 2026-03-14 12:04 ` Josua Mayer
0 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-14 12:04 UTC (permalink / raw)
To: Frank Li
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Carlos Song, Mikhail Anikin, Yazan Shhady, Rabeeh Khoury,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Am 13.03.26 um 20:15 schrieb Frank Li:
> On Fri, Mar 13, 2026 at 03:20:42PM +0100, Josua Mayer wrote:
>> Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
>> support bus recovery") introduced pinmux nodes for lx2160 i2c
>> interfaces, allowing runtime change between i2c and gpio functions
>> implementing bus recovery.
>>
>> This has caused unintended side-effects on SolidRun boards where the
>> first application of a pinmux node cleared all bits in a 32-bit word,
>> corrupting the configuration previously set by bootloader.
>>
>> The LX2160 SoC is configured at power-on from RCW (Reset
>> Configuration Word) typically located in the first 4k of boot media.
>> This blob configures various clock rates and pin functions.
>> The pinmux for i2c specifically is part of configuration words RCWSR12,
>> RCWSR13 and RCWSR14 size 32 bit each.
>> These values are accessible at read-only addresses 0x01e0012c following.
>>
>> For runtime (re-)configuration the SoC has a dynamic configuration area
>> where alternative settings can be applied. The counterparts of
>> RCWSR[12-14] can be overridden at 0x70010012c following.
>>
>> The commit in question used this area to switch i2c pins between i2c and
>> gpio function at runtime using the pinctrl-single driver - which reads a
>> 32-bit value, makes particular changes by bitmask and writes back the
>> new value.
>>
>> SolidRun have observed that if the dynamic configuration is read first
>> (before a write), it reads as zero regardless the initial values set by
>> RCW. After the first write consecutive reads reflect the written value.
>>
>> Because multiple pins are configured from a single 32-bit value, this
>> causes unintentional change of all bits (except those for i2c) being set
>> to zero when the pinctrl driver applies the first configuration.
>>
>> See below a short list of which functions RCWSR12 alone controls:
>>
>> LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
>> IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
>> IIC3_PMUX ||| ||| || | ||| XXX : I2C/GPIO/CAN/EVT
>> IIC4_PMUX ||| ||| || | |||XXX||| : I2C/GPIO/CAN/EVT
>> IIC5_PMUX ||| ||| || | XXX ||| : I2C/GPIO/SDHC-CLK
>> IIC6_PMUX ||| ||| || |XXX||| ||| : I2C/GPIO/SDHC-CLK
>> XSPI1_A_DATA74_PMUX ||| ||| XX X ||| ||| : XSPI/GPIO
>> XSPI1_A_DATA30_PMUX ||| |||XXX|| | ||| ||| : XSPI/GPIO
>> XSPI1_A_BASE_PMUX ||| XXX || | ||| ||| : XSPI/GPIO
>> SDHC1_BASE_PMUX |||XXX||| || | ||| ||| : SDHC/GPIO/SPI
>> SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
>> RESERVED XX||| ||| || | ||| ||| :
> List two IIC2_PMUX and SDHC1_DIR_PMUX should be enough.
>
>> On LX2162A Clearfog the initial (and intended) value is 0x08000006 -
>> enabling card-detect on IIC2_PMUX and control GPIOs on SDHC1_DIR_PMUX.
>> Everything else is intentional zero (enabling I2C & XSPI).
>>
>> By reading zero from dynamic configuration area, the commit in question
>> changes IIC2_PMUX to value 0 (I2C function), and SDHC1_DIR_PMUX to 0
>> (SDHC data direction function) - breaking card-detect and led gpios.
>>
>> This issue should affect any board based on LX2160 SoC that is using the
>> same or earlier versions of NXP bootloader as SolidRun have tested, in
>> particular: LSDK-21.08 and LS-5.15.71-2.2.0.
>>
>> Whether NXP added some extra initialisation in the bootloader on later
>> releases was not investigated. However bootloader upgrade should not be
>> necessary to run a newer Linux kernel.
>>
>> To work around this issue it is possible to explicitly define ALL pins
>> controlled by any 32-bit value so that gradually after processing all
>> pinctrl nodes the correct value is reached on all bits.
>>
>> This is a large task that should be done carefully on a per-board basis
>> and not globally through the SoC dtsi.
>> Therefore reverting the commit in question altogether was considered,
>> but received pushback in review with the argument that bus recovery was
>> important.
>>
>> Instead add pinmux nodes for all fields of rcwsr12 as used by affected
>> SolidRun LX2160A Clearfog-CX & Honeycomb, and LX2162A Clearfog boards.
> Thanks you very much. This way is the good. But commit message to too long
>
> Basically the default value of overwrite MUX is 0, which have not reflact
> hardware real status, which set by RCW. so update some field of mux impact
> other peripherial.
Thank you for the feedback, I simplify the commit description for v5,
and that in patch 7 too.
>
> Frank
>
>> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>> ---
>> .../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 7 +++++++
>> .../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 ++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++++++++++++++++++++++
>> .../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 ++
>> .../boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 7 +++++++
>> 5 files changed, 42 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
>> index eec2cd6c6d32a..7f6e39e27ce5c 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
>> @@ -162,6 +162,8 @@ rtc@51 {
>> };
>>
>> &fspi {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
>> status = "okay";
>>
>> flash@0 {
>> @@ -177,6 +179,11 @@ flash@0 {
>> };
>> };
>>
>> +&pinmux_i2crv {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gpio0_14_12_pins>;
>> +};
>> +
>> &usb0 {
>> status = "okay";
>> };
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
>> index af6258b2fe826..580ee9b3026e3 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
>> @@ -89,6 +89,8 @@ &emdio2 {
>> };
>>
>> &esdhc0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
>> sd-uhs-sdr104;
>> sd-uhs-sdr50;
>> sd-uhs-sdr25;
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> index 853b01452813a..af74e77efabc5 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> @@ -1721,6 +1721,10 @@ i2c1_scl_gpio: i2c1-scl-gpio-pins {
>> pinctrl-single,bits = <0x0 0x1 0x7>;
>> };
>>
>> + esdhc0_cd_wp_pins: iic2-sdhc-pins {
>> + pinctrl-single,bits = <0x0 0x6 0x7>;
>> + };
>> +
>> i2c2_scl: i2c2-scl-pins {
>> pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
>> };
>> @@ -1753,6 +1757,26 @@ i2c5_scl_gpio: i2c5-scl-gpio-pins {
>> pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
>> };
>>
>> + fspi_data74_pins: xspi1-data74-pins {
>> + pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
>> + };
>> +
>> + fspi_data30_pins: xspi1-data30-pins {
>> + pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
>> + };
>> +
>> + fspi_dqs_sck_cs10_pins: xspi1-base-pins {
>> + pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
>> + };
>> +
>> + esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
>> + pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
>> + };
>> +
>> + gpio0_14_12_pins: sdhc1-dir-gpio-pins {
>> + pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
>> + };
>> +
>> i2c6_scl: i2c6-scl-pins {
>> pinctrl-single,bits = <0x4 0x2 0x7>;
>> };
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
>> index eafef8718a0fe..8920326a06735 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
>> @@ -223,6 +223,8 @@ ethernet_phy8: ethernet-phy@15 {
>> };
>>
>> &esdhc0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
>> sd-uhs-sdr104;
>> sd-uhs-sdr50;
>> sd-uhs-sdr25;
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
>> index e914291e63a1a..e1344942eaaee 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
>> @@ -30,6 +30,8 @@ &esdhc1 {
>> };
>>
>> &fspi {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
>> status = "okay";
>>
>> flash@0 {
>> @@ -80,3 +82,8 @@ rtc@6f {
>> reg = <0x6f>;
>> };
>> };
>> +
>> +&pinmux_i2crv {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gpio0_14_12_pins>;
>> +};
>>
>> --
>> 2.51.0
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 02/10] arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
2026-03-13 14:20 ` [PATCH v4 01/10] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 14:20 ` [PATCH v4 03/10] arm64: dts: lx2160a: remove duplicate pinmux nodes Josua Mayer
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
LX2160A pinmux is done in groups by various length bitfields within
configuration registers.
The first i2c bus (called IIC1 in reference manual) is configured
through field IIC1_PMUX in register RCWSR14 bit 10 which is described in
the reference manual as a single bit, unlike the other i2c buses.
Change the bitmask for the pinmux nodes from 0x7 to 0x1 to ensure only
single bit is modified.
Further change the zero in the same line to hexadecimal format for
consistency.
This change is of cosmetic nature enforcing consistency with
documentation. There is no known issue when writing the extra two bits
marked in reference manual as reserved.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index af74e77efabc5..d5bb55df03216 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1794,11 +1794,11 @@ i2c7_scl_gpio: i2c7-scl-gpio-pins {
};
i2c0_scl: i2c0-scl-pins {
- pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
+ pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
i2c0_scl_gpio: i2c0-scl-gpio-pins {
- pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
+ pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
};
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 03/10] arm64: dts: lx2160a: remove duplicate pinmux nodes
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
2026-03-13 14:20 ` [PATCH v4 01/10] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux Josua Mayer
2026-03-13 14:20 ` [PATCH v4 02/10] arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 14:20 ` [PATCH v4 04/10] arm64: dts: lx2160a: rename pinmux nodes for readability Josua Mayer
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
LX2160A pinmux is done in groups by various length bitfields within
configuration registers.
The pinmux nodes i2c7-scl-pins and i2c7-scl-gpio-pins are duplicates of
i2c6-scl-gpio and i2c6-scl-gpio-pins, writing to the same register and
bits.
These two i2c buses i2c6/i2c7 (IIC7/IIC8) are configured together in
register RCWSR13 bits 3-0.
Drop the duplicate node name and change references to the i2c6 node.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index d5bb55df03216..41c9b4253f4a5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -862,8 +862,8 @@ i2c7: i2c@2070000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c7_scl>;
- pinctrl-1 = <&i2c7_scl_gpio>;
+ pinctrl-0 = <&i2c6_scl>;
+ pinctrl-1 = <&i2c6_scl_gpio>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -1785,14 +1785,6 @@ i2c6_scl_gpio: i2c6-scl-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
- i2c7_scl: i2c7-scl-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
- };
-
- i2c7_scl_gpio: i2c7-scl-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
- };
-
i2c0_scl: i2c0-scl-pins {
pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 04/10] arm64: dts: lx2160a: rename pinmux nodes for readability
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
` (2 preceding siblings ...)
2026-03-13 14:20 ` [PATCH v4 03/10] arm64: dts: lx2160a: remove duplicate pinmux nodes Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 14:20 ` [PATCH v4 05/10] arm64: dts: lx2160a: add sda gpio references for i2c bus recovery Josua Mayer
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
LX2160A pinmux is done in groups by various length bitfields within
configuration registers.
Each group of pins is named in the reference manual after a primary
function using soc-specific naming, e.g. IIC1 (for i2c0).
Hardware block numbering starts from zero in device-tree but one in the
reference manual.
Rename the already defined pinmux nodes originally added for changing
i2c pins between i2c and gpio functions reflecting the reference manual
name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
label.
This makes it more clear to future developers that these nodes do in
fact configure a group of pins, and helps with cross-referencing
documentation.
No functional change intended.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++++++-------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 41c9b4253f4a5..28500e8873909 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -750,8 +750,8 @@ i2c0: i2c@2000000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c0_scl>;
- pinctrl-1 = <&i2c0_scl_gpio>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&gpio0_3_2_pins>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -766,8 +766,8 @@ i2c1: i2c@2010000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c1_scl>;
- pinctrl-1 = <&i2c1_scl_gpio>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&gpio0_31_30_pins>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -782,8 +782,8 @@ i2c2: i2c@2020000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c2_scl>;
- pinctrl-1 = <&i2c2_scl_gpio>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&gpio0_29_28_pins>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -798,8 +798,8 @@ i2c3: i2c@2030000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c3_scl>;
- pinctrl-1 = <&i2c3_scl_gpio>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-1 = <&gpio0_27_26_pins>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -814,8 +814,8 @@ i2c4: i2c@2040000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c4_scl>;
- pinctrl-1 = <&i2c4_scl_gpio>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&gpio0_25_24_pins>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -830,8 +830,8 @@ i2c5: i2c@2050000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c5_scl>;
- pinctrl-1 = <&i2c5_scl_gpio>;
+ pinctrl-0 = <&i2c5_pins>;
+ pinctrl-1 = <&gpio0_23_22_pins>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -846,8 +846,8 @@ i2c6: i2c@2060000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c6_scl>;
- pinctrl-1 = <&i2c6_scl_gpio>;
+ pinctrl-0 = <&i2c6_i2c7_pins>;
+ pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -862,8 +862,8 @@ i2c7: i2c@2070000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c6_scl>;
- pinctrl-1 = <&i2c6_scl_gpio>;
+ pinctrl-0 = <&i2c6_i2c7_pins>;
+ pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -1713,11 +1713,11 @@ pinmux_i2crv: pinmux@70010012c {
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
- i2c1_scl: i2c1-scl-pins {
+ i2c1_pins: iic2-i2c-pins {
pinctrl-single,bits = <0x0 0 0x7>;
};
- i2c1_scl_gpio: i2c1-scl-gpio-pins {
+ gpio0_31_30_pins: iic2-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
@@ -1725,35 +1725,35 @@ esdhc0_cd_wp_pins: iic2-sdhc-pins {
pinctrl-single,bits = <0x0 0x6 0x7>;
};
- i2c2_scl: i2c2-scl-pins {
+ i2c2_pins: iic3-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
- i2c2_scl_gpio: i2c2-scl-gpio-pins {
+ gpio0_29_28_pins: iic3-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
- i2c3_scl: i2c3-scl-pins {
+ i2c3_pins: iic4-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
};
- i2c3_scl_gpio: i2c3-scl-gpio-pins {
+ gpio0_27_26_pins: iic4-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
- i2c4_scl: i2c4-scl-pins {
+ i2c4_pins: iic5-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
};
- i2c4_scl_gpio: i2c4-scl-gpio-pins {
+ gpio0_25_24_pins: iic5-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
- i2c5_scl: i2c5-scl-pins {
+ i2c5_pins: iic6-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
};
- i2c5_scl_gpio: i2c5-scl-gpio-pins {
+ gpio0_23_22_pins: iic6-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
@@ -1777,19 +1777,19 @@ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
};
- i2c6_scl: i2c6-scl-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
+ gpio1_18_15_pins: iic8-iic7-gpio-pins {
+ pinctrl-single,bits = <0x4 0x1 0x7>;
};
- i2c6_scl_gpio: i2c6-scl-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
+ i2c6_i2c7_pins: iic8-iic7-i2c-pins {
+ pinctrl-single,bits = <0x4 0x2 0x7>;
};
- i2c0_scl: i2c0-scl-pins {
+ i2c0_pins: iic1-i2c-pins {
pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
- i2c0_scl_gpio: i2c0-scl-gpio-pins {
+ gpio0_3_2_pins: iic1-gpio-pins {
pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
};
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 05/10] arm64: dts: lx2160a: add sda gpio references for i2c bus recovery
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
` (3 preceding siblings ...)
2026-03-13 14:20 ` [PATCH v4 04/10] arm64: dts: lx2160a: rename pinmux nodes for readability Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 14:27 ` Josua Mayer
2026-03-13 14:20 ` [PATCH v4 06/10] arm64: dts: lx2160a: change zeros to hexadecimal in pinmux nodes Josua Mayer
` (4 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
LX2160A pinmux is done in groups by various length bitfields within
configuration registers.
In particular i2c sda/scl pins are always configured together. Therefore
bus recovery may control both sda and scl.
When pinmux nodes and bus recovery was enabled originally for LX2160,
only the scl-gpios were added to the i2c controller nodes.
Add references to sda-gpios for each i2c controller.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 28500e8873909..a7fcfb7339f1d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -753,6 +753,7 @@ i2c0: i2c@2000000 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-1 = <&gpio0_3_2_pins>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -769,6 +770,7 @@ i2c1: i2c@2010000 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-1 = <&gpio0_31_30_pins>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -785,6 +787,7 @@ i2c2: i2c@2020000 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&gpio0_29_28_pins>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -801,6 +804,7 @@ i2c3: i2c@2030000 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-1 = <&gpio0_27_26_pins>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -817,6 +821,7 @@ i2c4: i2c@2040000 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-1 = <&gpio0_25_24_pins>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -833,6 +838,7 @@ i2c5: i2c@2050000 {
pinctrl-0 = <&i2c5_pins>;
pinctrl-1 = <&gpio0_23_22_pins>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -849,6 +855,7 @@ i2c6: i2c@2060000 {
pinctrl-0 = <&i2c6_i2c7_pins>;
pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -865,6 +872,7 @@ i2c7: i2c@2070000 {
pinctrl-0 = <&i2c6_i2c7_pins>;
pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 05/10] arm64: dts: lx2160a: add sda gpio references for i2c bus recovery
2026-03-13 14:20 ` [PATCH v4 05/10] arm64: dts: lx2160a: add sda gpio references for i2c bus recovery Josua Mayer
@ 2026-03-13 14:27 ` Josua Mayer
0 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:27 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Am 13.03.26 um 15:20 schrieb Josua Mayer:
> LX2160A pinmux is done in groups by various length bitfields within
> configuration registers.
>
> In particular i2c sda/scl pins are always configured together. Therefore
> bus recovery may control both sda and scl.
>
> When pinmux nodes and bus recovery was enabled originally for LX2160,
> only the scl-gpios were added to the i2c controller nodes.
>
> Add references to sda-gpios for each i2c controller.
>
> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 28500e8873909..a7fcfb7339f1d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -753,6 +753,7 @@ i2c0: i2c@2000000 {
> pinctrl-0 = <&i2c0_pins>;
> pinctrl-1 = <&gpio0_3_2_pins>;
> scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -769,6 +770,7 @@ i2c1: i2c@2010000 {
> pinctrl-0 = <&i2c1_pins>;
> pinctrl-1 = <&gpio0_31_30_pins>;
> scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -785,6 +787,7 @@ i2c2: i2c@2020000 {
> pinctrl-0 = <&i2c2_pins>;
> pinctrl-1 = <&gpio0_29_28_pins>;
> scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -801,6 +804,7 @@ i2c3: i2c@2030000 {
> pinctrl-0 = <&i2c3_pins>;
> pinctrl-1 = <&gpio0_27_26_pins>;
> scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -817,6 +821,7 @@ i2c4: i2c@2040000 {
> pinctrl-0 = <&i2c4_pins>;
> pinctrl-1 = <&gpio0_25_24_pins>;
> scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -833,6 +838,7 @@ i2c5: i2c@2050000 {
> pinctrl-0 = <&i2c5_pins>;
> pinctrl-1 = <&gpio0_23_22_pins>;
> scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -849,6 +855,7 @@ i2c6: i2c@2060000 {
> pinctrl-0 = <&i2c6_i2c7_pins>;
> pinctrl-1 = <&gpio1_18_15_pins>;
> scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -865,6 +872,7 @@ i2c7: i2c@2070000 {
> pinctrl-0 = <&i2c6_i2c7_pins>;
> pinctrl-1 = <&gpio1_18_15_pins>;
> scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Should be &gpio1, queued for v5 ....
> status = "disabled";
> };
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 06/10] arm64: dts: lx2160a: change zeros to hexadecimal in pinmux nodes
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
` (4 preceding siblings ...)
2026-03-13 14:20 ` [PATCH v4 05/10] arm64: dts: lx2160a: add sda gpio references for i2c bus recovery Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 14:20 ` [PATCH v4 07/10] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word Josua Mayer
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
Replace some stray zeros from decimal to hexadecimal format within
pinmux nodes.
No functional change intended.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a7fcfb7339f1d..57c0fd02d6c69 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1722,7 +1722,7 @@ pinmux_i2crv: pinmux@70010012c {
pinctrl-single,function-mask = <0x7>;
i2c1_pins: iic2-i2c-pins {
- pinctrl-single,bits = <0x0 0 0x7>;
+ pinctrl-single,bits = <0x0 0x0 0x7>;
};
gpio0_31_30_pins: iic2-gpio-pins {
@@ -1734,7 +1734,7 @@ esdhc0_cd_wp_pins: iic2-sdhc-pins {
};
i2c2_pins: iic3-i2c-pins {
- pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 3)>;
};
gpio0_29_28_pins: iic3-gpio-pins {
@@ -1742,7 +1742,7 @@ gpio0_29_28_pins: iic3-gpio-pins {
};
i2c3_pins: iic4-i2c-pins {
- pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>;
};
gpio0_27_26_pins: iic4-gpio-pins {
@@ -1750,7 +1750,7 @@ gpio0_27_26_pins: iic4-gpio-pins {
};
i2c4_pins: iic5-i2c-pins {
- pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>;
};
gpio0_25_24_pins: iic5-gpio-pins {
@@ -1758,7 +1758,7 @@ gpio0_25_24_pins: iic5-gpio-pins {
};
i2c5_pins: iic6-i2c-pins {
- pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>;
};
gpio0_23_22_pins: iic6-gpio-pins {
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 07/10] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
` (5 preceding siblings ...)
2026-03-13 14:20 ` [PATCH v4 06/10] arm64: dts: lx2160a: change zeros to hexadecimal in pinmux nodes Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 14:20 ` [PATCH v4 08/10] arm64: dts: lx2160a-cex7: add rtc alias Josua Mayer
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
support bus recovery") introduced pinmux nodes for lx2160 i2c
interfaces, allowing runtime change between i2c and gpio functions
implementing bus recovery.
This can cause unintended side-effects because the dynamic configuration
area where pinmux is modified at runtime reads zero initially, causing
application of the first pinmux node to clear any other bits previously
set during reset configuration.
It is possible for bootloaders to implement a workaround and copy from
the reset values from read-only area to dynamic configuration area,
however bootloader updates should not be required for kernel updates.
Alternatively pinmux in device-tree can be made complete, to cover all
bits of a 32-bit register, not just i2c & gpio functions, e.g. for
RCWSR12 register:
LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
IIC3_PMUX ||| ||| || | ||| XXX : I2C/GPIO/CAN/EVT
IIC4_PMUX ||| ||| || | |||XXX||| : I2C/GPIO/CAN/EVT
IIC5_PMUX ||| ||| || | XXX ||| : I2C/GPIO/SDHC-CLK
IIC6_PMUX ||| ||| || |XXX||| ||| : I2C/GPIO/SDHC-CLK
XSPI1_A_DATA74_PMUX ||| ||| XX X ||| ||| : XSPI/GPIO
XSPI1_A_DATA30_PMUX ||| |||XXX|| | ||| ||| : XSPI/GPIO
XSPI1_A_BASE_PMUX ||| XXX || | ||| ||| : XSPI/GPIO
SDHC1_BASE_PMUX |||XXX||| || | ||| ||| : SDHC/GPIO/SPI
SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
RESERVED XX||| ||| || | ||| ||| :
Add description for all bits of RCWSR12 register, including i2c, gpio,
flextimer, spi, can and sdhc.
Other configuration words, i.e. RCWSR13 & RCWSR14 may be added in the
future for boards setting non-zero values there.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 75 ++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 57c0fd02d6c69..4d7800a697d72 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1721,6 +1721,7 @@ pinmux_i2crv: pinmux@70010012c {
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
+ /* RCWSR12 */
i2c1_pins: iic2-i2c-pins {
pinctrl-single,bits = <0x0 0x0 0x7>;
};
@@ -1729,6 +1730,10 @@ gpio0_31_30_pins: iic2-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
+ ftm0_ch10_pins: iic2-ftm-pins {
+ pinctrl-single,bits = <0x0 0x2 0x7>;
+ };
+
esdhc0_cd_wp_pins: iic2-sdhc-pins {
pinctrl-single,bits = <0x0 0x6 0x7>;
};
@@ -1741,6 +1746,14 @@ gpio0_29_28_pins: iic3-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
+ can0_pins: iic3-can-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>;
+ };
+
+ event65_pins: iic3-event-pins {
+ pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>;
+ };
+
i2c3_pins: iic4-i2c-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>;
};
@@ -1749,6 +1762,14 @@ gpio0_27_26_pins: iic4-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
+ can1_pins: iic4-can-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>;
+ };
+
+ event87_pins: iic4-event-pins {
+ pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>;
+ };
+
i2c4_pins: iic5-i2c-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>;
};
@@ -1757,6 +1778,14 @@ gpio0_25_24_pins: iic5-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
+ esdhc0_clksync_pins: iic5-sdhc-clk-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>;
+ };
+
+ dspi2_miso_mosi_pins: iic5-spi3-pins {
+ pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>;
+ };
+
i2c5_pins: iic6-i2c-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>;
};
@@ -1765,26 +1794,71 @@ gpio0_23_22_pins: iic6-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
+ esdhc1_clksync_pins: iic6-sdhc-clk-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>;
+ };
+
fspi_data74_pins: xspi1-data74-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
};
+ gpio1_31_28_pins: xspi1-data74-gpio-pins {
+ pinctrl-single,bits = <0x0 0x1 (0x7 << 15)>;
+ };
+
fspi_data30_pins: xspi1-data30-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
};
+ gpio1_27_24_pins: xspi1-data30-gpio-pins {
+ pinctrl-single,bits = <0x0 0x1 (0x7 << 18)>;
+ };
+
fspi_dqs_sck_cs10_pins: xspi1-base-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
};
+ gpio1_23_20_pins: xspi1-base-gpio-pins {
+ pinctrl-single,bits = <0x0 0x1 (0x7 << 21)>;
+ };
+
esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
};
+ gpio0_21_15_pins: sdhc1-base-gpio-pins {
+ pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>;
+ };
+
+ dspi0_pins: sdhc1-base-spi1-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>;
+ };
+
+ esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
+ pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>;
+ };
+
+ esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
+ pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>;
+ };
+
+ esdhc0_dir_pins: sdhc1-dir-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>;
+ };
+
gpio0_14_12_pins: sdhc1-dir-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
};
+ dspi2_cs31_pins: sdhc1-dir-spi3-pins {
+ pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>;
+ };
+
+ esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
+ pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>;
+ };
+
+ /* RCWSR13 */
gpio1_18_15_pins: iic8-iic7-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
@@ -1793,6 +1867,7 @@ i2c6_i2c7_pins: iic8-iic7-i2c-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
+ /* RCWSR14 */
i2c0_pins: iic1-i2c-pins {
pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 08/10] arm64: dts: lx2160a-cex7: add rtc alias
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
` (6 preceding siblings ...)
2026-03-13 14:20 ` [PATCH v4 07/10] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 14:20 ` [PATCH v4 09/10] arm64: dts: lx2162a-sr-som: add crypto & rtc aliases, model Josua Mayer
2026-03-13 14:20 ` [PATCH v4 10/10] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source Josua Mayer
9 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
Add alias for rtc0 ensuring that on-COM RTC is assigned first index.
Note that fsl-lx2160a.dtsi already defines an alias for rtc1 which
implicitly achieved the same result.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index 7f6e39e27ce5c..90956ffb8ea9a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -14,6 +14,7 @@ / {
aliases {
crypto = &crypto;
+ rtc0 = &com_rtc;
};
sb_3v3: regulator-sb3v3 {
@@ -154,7 +155,7 @@ &i2c2 {
&i2c4 {
status = "okay";
- rtc@51 {
+ com_rtc: rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>;
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 09/10] arm64: dts: lx2162a-sr-som: add crypto & rtc aliases, model
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
` (7 preceding siblings ...)
2026-03-13 14:20 ` [PATCH v4 08/10] arm64: dts: lx2160a-cex7: add rtc alias Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
2026-03-13 14:20 ` [PATCH v4 10/10] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source Josua Mayer
9 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
Add aliases for crypto accelerator and rtc0 ensuring that on-SoM RTC and
the SoC A72 domain crypto accelerator are assigned first index.
Further set model and compatible strings which are informative but
overridden by actual boards.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
index e1344942eaaee..3ad908d52a18b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
@@ -5,6 +5,16 @@
// Copyright 2021 Rabeeh Khoury <rabeeh@solid-run.com>
// Copyright 2023 Josua Mayer <josua@solid-run.com>
+/ {
+ model = "SolidRun LX2162A System on Module";
+ compatible = "solidrun,lx2162a-som", "fsl,lx2160a";
+
+ aliases {
+ crypto = &crypto;
+ rtc0 = &som_rtc;
+ };
+};
+
&crypto {
status = "okay";
};
@@ -77,7 +87,7 @@ variable_eeprom: eeprom@54 {
&i2c5 {
status = "okay";
- rtc@6f {
+ som_rtc: rtc@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v4 10/10] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source
2026-03-13 14:20 [PATCH v4 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards Josua Mayer
` (8 preceding siblings ...)
2026-03-13 14:20 ` [PATCH v4 09/10] arm64: dts: lx2162a-sr-som: add crypto & rtc aliases, model Josua Mayer
@ 2026-03-13 14:20 ` Josua Mayer
9 siblings, 0 replies; 14+ messages in thread
From: Josua Mayer @ 2026-03-13 14:20 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
LX2162A Clearfog has four LEDs attached physically to the 4-port SFP
connector. They are intended to show information relating to network
interface status.
Select "netdev" as default trigger for each LED, and link each one to
the respective dpmac instance as trigger-source.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index 8920326a06735..9d50d3e2761da 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -41,21 +41,29 @@ leds {
led_sfp_at: led-sfp-at {
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
default-state = "off";
+ linux,default-trigger = "netdev";
+ trigger-sources = <&dpmac3>;
};
led_sfp_ab: led-sfp-ab {
gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
default-state = "off";
+ linux,default-trigger = "netdev";
+ trigger-sources = <&dpmac4>;
};
led_sfp_bt: led-sfp-bt {
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
default-state = "off";
+ linux,default-trigger = "netdev";
+ trigger-sources = <&dpmac5>;
};
led_sfp_bb: led-sfp-bb {
gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
default-state = "off";
+ linux,default-trigger = "netdev";
+ trigger-sources = <&dpmac6>;
};
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread