From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DFE7105F798 for ; Fri, 13 Mar 2026 10:44:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UsbiMY794BaOl5FPe8kvLbYBRj7zwFtvYOKADAiSwjI=; b=0A+qRuAkayjjaqYxvRNOgeZOUX pacbc/AOWIg6nVUuGSkdsTDdzZU2rVoZr0E5q6iMayLdayKGO1/H0FJb4AYqovv1mBP1SAe5DAYIe oSRMIDBTnGtN6Rw62Aioo8oRuRLZfo4+smR+HXphzlM7nJf3HbNgvn+HLMpwF3s++Hiu8fjM0VGXM Tc7vsSbXL+jRJtQ9ur6JkmfOp0YC7PTKrQ+Yw93CW3LHicIpV2tBTNl1en6LGo4QffR7dzyqb2l1J Ulzr7p76QP7gAxEeZh896Et6fkSBNnvsUtWgt9HerBmPkGiO0asCKlqTr9tK8aDGNWFPMQFhA60Bt DR1lrNKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w1005-0000000HX3E-1IbC; Fri, 13 Mar 2026 10:44:13 +0000 Received: from canpmsgout05.his.huawei.com ([113.46.200.220]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1w0zzz-0000000HWxw-3HxT for linux-arm-kernel@lists.infradead.org; Fri, 13 Mar 2026 10:44:09 +0000 dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=UsbiMY794BaOl5FPe8kvLbYBRj7zwFtvYOKADAiSwjI=; b=W/I0E8kLnnPTwXmUPV+AH3na4QH1mW3S68tBnguB9ZYttbznvwcmLdp2j+YJlBlSZA3KYoWgi Ql58MpteOnioXHia1cHs3gycQjo1Kl1yndPqnd0Py9kKWEo9sJvLpzGltqNvKxltHzpXRnDZPPy wBF4yqbAhzLiINFNd1Tl1b4= Received: from mail.maildlp.com (unknown [172.19.162.197]) by canpmsgout05.his.huawei.com (SkyGuard) with ESMTPS id 4fXLYW57C1z12LJy; Fri, 13 Mar 2026 18:38:23 +0800 (CST) Received: from kwepemj200003.china.huawei.com (unknown [7.202.194.15]) by mail.maildlp.com (Postfix) with ESMTPS id F159740363; Fri, 13 Mar 2026 18:43:57 +0800 (CST) Received: from localhost.huawei.com (10.90.31.46) by kwepemj200003.china.huawei.com (7.202.194.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 13 Mar 2026 18:43:57 +0800 From: Qinxin Xia To: , , CC: , , , , , , , Subject: [RFC PATCH 2/5] iommu/arm-smmu-v3: Add register display to debugfs Date: Fri, 13 Mar 2026 18:43:48 +0800 Message-ID: <20260313104351.3502293-3-xiaqinxin@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260313104351.3502293-1-xiaqinxin@huawei.com> References: <20260313104351.3502293-1-xiaqinxin@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="y" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.90.31.46] X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemj200003.china.huawei.com (7.202.194.15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260313_034408_148151_9852BEBF X-CRM114-Status: GOOD ( 12.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add register display functionality to debugfs.This allows reading and displaying key SMMU register values including control registers and queue pointers. The registers file shows: - CR0, CR1, CR2 control registers - Command and Event queue pointers Signed-off-by: Qinxin Xia --- .../arm/arm-smmu-v3/arm-smmu-v3-debugfs.c | 68 ++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-debugfs.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-debugfs.c index 542bd6047f26..f9bf955f3351 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-debugfs.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-debugfs.c @@ -12,11 +12,20 @@ * - Capability reporting covering all major SMMU features and configuration * - Extensible architecture designed for adding future debug functionality * - Comprehensive error handling and resource cleanup + * - Display of control registers (CR0, CR1, CR2) with bitfield decoding + * - Command and Event queue pointer monitoring (PROD/CONS) + * + * Register Information Displayed: + * - CR0: SMMU global control with enable states and queue enables + * - CR1/CR2: Additional control and configuration registers + * - CMDQ_PROD/CONS: Command queue producer and consumer pointers + * - EVTQ_PROD/CONS: Event queue producer and consumer pointers * * Directory Structure: * /sys/kernel/debug/iommu/arm_smmu_v3/ * └── smmu0/ - * └── capabilities # SMMU feature capabilities and configuration + * ├── capabilities # SMMU feature capabilities and configuration + * └── registers # SMMU Key registers * * The capabilities file provides detailed information about: * - Architecture version and translation stage support (Stage1/Stage2) @@ -24,6 +33,11 @@ * - Stream table size and command/event queue depths * - All feature bits from the SMMU device structure * + * The register display provides crucial visibility into: + * - SMMU operational state (enabled/disabled) + * - Queue operation and potential stalls + * - Configuration settings affecting all streams + * * Copyright (C) 2025 HiSilicon Limited. * Author: Qinxin Xia */ @@ -69,6 +83,54 @@ static int smmu_debugfs_capabilities_show(struct seq_file *seq, void *v) } DEFINE_SHOW_ATTRIBUTE(smmu_debugfs_capabilities); +/** + * smmu_debugfs_registers_show() - Display SMMU register values + * @seq: seq_file to write to + * @v: private data (SMMU device) + * + * Return: 0 on success, negative error code on failure + */ +static int smmu_debugfs_registers_show(struct seq_file *seq, void *v) +{ + struct arm_smmu_device *smmu = seq->private; + void __iomem *base; + + if (!smmu || !smmu->base) { + seq_puts(seq, "SMMU not available\n"); + return 0; + } + + base = smmu->base; + + seq_puts(seq, "SMMUv3 Key Registers:\n"); + + /* 32-bit control registers */ + seq_printf(seq, "CR0: 0x%08x [%s%s%s]\n", + readl_relaxed(base + ARM_SMMU_CR0), + readl_relaxed(base + ARM_SMMU_CR0) & CR0_SMMUEN ? + "Enabled " : "Disabled ", + readl_relaxed(base + ARM_SMMU_CR0) & CR0_EVTQEN ? + "EventQ " : "", + readl_relaxed(base + ARM_SMMU_CR0) & CR0_CMDQEN ? + "CmdQ " : ""); + + seq_printf(seq, "CR1: 0x%08x\n", readl_relaxed(base + ARM_SMMU_CR1)); + seq_printf(seq, "CR2: 0x%08x\n", readl_relaxed(base + ARM_SMMU_CR2)); + + /* 32-bit queue pointer registers */ + seq_printf(seq, "CMDQ_PROD: 0x%08x\n", + readl_relaxed(base + ARM_SMMU_CMDQ_PROD)); + seq_printf(seq, "CMDQ_CONS: 0x%08x\n", + readl_relaxed(base + ARM_SMMU_CMDQ_CONS)); + seq_printf(seq, "EVTQ_PROD: 0x%08x\n", + readl_relaxed(base + ARM_SMMU_EVTQ_PROD)); + seq_printf(seq, "EVTQ_CONS: 0x%08x\n", + readl_relaxed(base + ARM_SMMU_EVTQ_CONS)); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(smmu_debugfs_registers); + /** * arm_smmu_debugfs_setup() - Initialize debugfs for SMMU device * @smmu: SMMU device to setup debugfs for @@ -120,6 +182,10 @@ int arm_smmu_debugfs_setup(struct arm_smmu_device *smmu, phys_addr_t ioaddr) &smmu_debugfs_capabilities_fops)) goto err_cleanup; + if (!debugfs_create_file("registers", 0444, smmu_dir, smmu, + &smmu_debugfs_registers_fops)) + goto err_cleanup; + pr_info("SMMUv3 debugfs initialized for smmu%pa\n", &ioaddr); return 0; -- 2.33.0