From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54D36F30298 for ; Mon, 16 Mar 2026 03:01:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=myNJ7+etw54WAWT1BMNWvXj3xvpTZxjGHfqbbRsc6HI=; b=PPPWXLrsEGFHklt3HbVJZSR77V 0qjq3RG7uRnB0FBuZEcQCXDsEpFjdEdA9JLrmjofF71pAzEbeQA8C+djnELr/p16YF8MFBaYRR1s6 ru08Zxs3SRqfLT4l6ivrfH6cgvVGcVkluYshr8NJHzBJs2F7j/lDAwlVvAZ/vnd6Zo4pkPKp9K5T6 UaLyFn5wc80XMQYQUJE0XGsfrQwOqq421u4YNM0TsUCHPmJkLl00i856tout0WF+p6p6ghXYQNEWM gIzCODWOtfOICBYnHKD1sbhXZVEYBpJQFREPeUQTvnREyIR0yQJgVXrLm8oO97VCjNSjY9Z5E9vNV l1CKH1rw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w1yCl-00000003F6i-0VHp; Mon, 16 Mar 2026 03:01:19 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1w1yCW-00000003F1K-3ZKM for linux-arm-kernel@lists.infradead.org; Mon, 16 Mar 2026 03:01:06 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 16 Mar 2026 11:00:48 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 16 Mar 2026 11:00:48 +0800 From: Billy Tsai Date: Mon, 16 Mar 2026 11:00:48 +0800 Subject: [PATCH v2 3/3] iio: adc: aspeed: Reserve battery sensing channel for on-demand use MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260316-adc-v2-3-21475a217b09@aspeedtech.com> References: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> In-Reply-To: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773630047; l=3044; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=NDFWhGINrDRsy3G0bfBO0q4ZxiMyFTtoWTFlKzGT8bg=; b=8+JasgxeNNHI5TmBibZAQ6o3VSNdAtCoMXPHE46zCX4x1ALdv0eCR3VXkTeVQYfJuIc07K160 P2qmexYd5iSCsN5gia0/OnQHF3m7pxjNAjBii10chq1nZ31mI2AqNnB X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260315_200105_186622_DA3D4F43 X-CRM114-Status: GOOD ( 14.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For controllers with battery sensing capability (AST2600/AST2700), the last channel uses a different circuit design optimized for battery voltage measurement. This channel should not be enabled by default along with other channels to avoid potential interference and power efficiency issues. This ensures optimal power efficiency for normal ADC operations while maintaining full functionality when battery sensing is needed. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 81a2dd752541..ab173d8542c6 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -148,6 +148,13 @@ struct aspeed_adc_data { static inline unsigned int aspeed_adc_get_active_channels(const struct aspeed_adc_data *data) { + /* + * For controllers with battery sensing capability, the last channel + * is reserved for battery sensing and should not be included in + * normal channel operations. + */ + if (data->model_data->bat_sense_sup) + return data->model_data->num_channels - 1; return data->model_data->num_channels; } @@ -315,9 +322,26 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_RAW: + adc_engine_control_reg_val = readl(data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * For battery sensing capable controllers, we need to enable + * the specific channel before reading. This is required because + * the battery channel may not be enabled by default. + */ + if (data->model_data->bat_sense_sup && + chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { + u32 ctrl_reg = adc_engine_control_reg_val & ~ASPEED_ADC_CTRL_CHANNEL; + + ctrl_reg |= ASPEED_ADC_CTRL_CHANNEL_ENABLE(chan->channel); + writel(ctrl_reg, data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable a new channel need to wait some time for adc stable + * Experiment result is 1ms. + */ + mdelay(1); + } + if (data->battery_sensing && chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { - adc_engine_control_reg_val = - readl(data->base + ASPEED_REG_ENGINE_CONTROL); writel(adc_engine_control_reg_val | FIELD_PREP(ASPEED_ADC_CH7_MODE, ASPEED_ADC_CH7_BAT) | @@ -331,11 +355,11 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, *val = readw(data->base + chan->address); *val = (*val * data->battery_mode_gain.mult) / data->battery_mode_gain.div; - /* Restore control register value */ - writel(adc_engine_control_reg_val, - data->base + ASPEED_REG_ENGINE_CONTROL); } else *val = readw(data->base + chan->address); + /* Restore control register value */ + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: -- 2.34.1