From: kernel test robot <lkp@intel.com>
To: Jie Gan <jie.gan@oss.qualcomm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@arm.com>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, Jie Gan <jie.gan@oss.qualcomm.com>
Subject: Re: [PATCH v15 6/7] coresight: ctcu: enable byte-cntr for TMC ETR devices
Date: Tue, 17 Mar 2026 18:10:08 +0800 [thread overview]
Message-ID: <202603171821.OtWlpARW-lkp@intel.com> (raw)
In-Reply-To: <20260313-enable-byte-cntr-for-ctcu-v15-6-1777f14ed319@oss.qualcomm.com>
Hi Jie,
kernel test robot noticed the following build errors:
[auto build test ERROR on a0ae2a256046c0c5d3778d1a194ff2e171f16e5f]
url: https://github.com/intel-lab-lkp/linux/commits/Jie-Gan/coresight-core-refactor-ctcu_get_active_port-and-make-it-generic/20260315-052703
base: a0ae2a256046c0c5d3778d1a194ff2e171f16e5f
patch link: https://lore.kernel.org/r/20260313-enable-byte-cntr-for-ctcu-v15-6-1777f14ed319%40oss.qualcomm.com
patch subject: [PATCH v15 6/7] coresight: ctcu: enable byte-cntr for TMC ETR devices
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20260317/202603171821.OtWlpARW-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260317/202603171821.OtWlpARW-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603171821.OtWlpARW-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c:177:3: error: cannot jump from this goto statement to its label
177 | goto out;
| ^
drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c:179:2: note: jump bypasses initialization of variable with __attribute__((cleanup))
179 | guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock);
| ^
include/linux/cleanup.h:419:2: note: expanded from macro 'guard'
419 | CLASS(_name, __UNIQUE_ID(guard))
| ^
include/linux/cleanup.h:300:3: note: expanded from macro 'CLASS'
300 | class_##_name##_constructor
| ^
<scratch space>:18:1: note: expanded from here
18 | class_raw_spinlock_irqsave_constructor
| ^
note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:16:23: note: expanded from macro '__PASTE'
16 | #define __PASTE(a, b) ___PASTE(a, b)
| ^
include/linux/compiler_types.h:15:24: note: expanded from macro '___PASTE'
15 | #define ___PASTE(a, b) a##b
| ^
<scratch space>:24:1: note: expanded from here
24 | __UNIQUE_ID_unlock_802
| ^
drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c:179:2: note: jump bypasses initialization of variable with __attribute__((cleanup))
include/linux/cleanup.h:419:15: note: expanded from macro 'guard'
419 | CLASS(_name, __UNIQUE_ID(guard))
| ^
include/linux/compiler.h:168:2: note: expanded from macro '__UNIQUE_ID'
168 | __PASTE(__UNIQUE_ID_, \
| ^
include/linux/compiler_types.h:16:23: note: expanded from macro '__PASTE'
16 | #define __PASTE(a, b) ___PASTE(a, b)
| ^
include/linux/compiler_types.h:15:24: note: expanded from macro '___PASTE'
15 | #define ___PASTE(a, b) a##b
| ^
<scratch space>:12:1: note: expanded from here
12 | __UNIQUE_ID_guard_801
| ^
1 error generated.
vim +177 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c
156
157 static int tmc_read_prepare_byte_cntr(struct tmc_drvdata *etr_drvdata)
158 {
159 struct coresight_device *ctcu = tmc_etr_get_ctcu_device(etr_drvdata);
160 struct ctcu_byte_cntr *byte_cntr_data;
161 int ret = 0;
162
163 /* byte-cntr is operating with SYSFS mode being enabled only */
164 if (coresight_get_mode(etr_drvdata->csdev) != CS_MODE_SYSFS)
165 return -EINVAL;
166
167 byte_cntr_data = ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev);
168 if (!byte_cntr_data || !byte_cntr_data->irq_enabled)
169 return -EINVAL;
170
171 if (byte_cntr_data->reading)
172 return -EBUSY;
173
174 /* Setup an available etr_buf_list for byte-cntr */
175 ret = tmc_create_etr_buf_list(etr_drvdata, 2);
176 if (ret)
> 177 goto out;
178
179 guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock);
180 atomic_set(&byte_cntr_data->irq_cnt, 0);
181 /*
182 * Configure the byte-cntr register to enable IRQ. The configured
183 * size is 5% of the buffer_size.
184 */
185 ctcu_cfg_byte_cntr_reg(byte_cntr_data->ctcu_drvdata,
186 etr_drvdata->size / MAX_IRQ_CNT,
187 byte_cntr_data->irq_ctrl_offset);
188 enable_irq_wake(byte_cntr_data->irq);
189 byte_cntr_data->buf_node = NULL;
190 byte_cntr_data->reading = true;
191
192 out:
193 return ret;
194 }
195
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2026-03-17 10:10 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 9:02 [PATCH v15 0/7] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2026-03-13 9:02 ` [PATCH v15 1/7] coresight: core: refactor ctcu_get_active_port and make it generic Jie Gan
2026-03-13 9:02 ` [PATCH v15 2/7] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2026-03-17 8:43 ` kernel test robot
2026-03-17 11:01 ` Suzuki K Poulose
2026-03-18 1:06 ` Jie Gan
2026-03-13 9:02 ` [PATCH v15 3/7] coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs read operations Jie Gan
2026-03-13 9:02 ` [PATCH v15 4/7] coresight: etr: add a new function to retrieve the CTCU device Jie Gan
2026-03-13 9:02 ` [PATCH v15 5/7] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2026-03-13 9:02 ` [PATCH v15 6/7] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2026-03-17 10:10 ` kernel test robot [this message]
2026-03-13 9:02 ` [PATCH v15 7/7] arm64: dts: qcom: lemans: add interrupts to CTCU device Jie Gan
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