[PATCH v3 0/3] dmaengine: arm-dma350: support combined IRQ topology

[PATCH v3 0/3] dmaengine: arm-dma350: support combined IRQ topology

[Jun Guo]

DMA-350 can be integrated with either one interrupt per channel or a
single combined interrupt for all channels. This series adds support
for the combined IRQ topology while keeping compatibility with the
per-channel topology.

Patch 1 updates the DT binding to document both interrupt topologies
(1 combined IRQ or 8 per-channel IRQs) and keeps "arm,dma-350" as the
generic compatible, with optional SoC-specific fallback compatible.

Patch 2 updates the driver to detect IRQ topology at runtime using
platform_irq_count(), handles both modes in one code path, and enables
DMANSECCTRL.INTREN_ANYCHINTR only when combined IRQ mode is used.

Patch 3 adds the Sky1 DMA DT node using the combined IRQ topology.

The series was tested on CIX SKY1 with dmatest:
  % echo 2000 > /sys/module/dmatest/parameters/timeout
  % echo 1 > /sys/module/dmatest/parameters/iterations
  % echo "" > /sys/module/dmatest/parameters/channel
  % echo 1 > /sys/module/dmatest/parameters/run

Changes in v3:
- Rework binding compatible description to match generic-first model.
- Keep interrupts schema support for both 1-IRQ and 8-IRQ topologies.
- Drop SoC match-data dependency for IRQ mode selection.
- Detect IRQ topology via platform_irq_count() in probe path.
- Refactor IRQ handling into a shared channel handler.
- Enable DMANSECCTRL.INTREN_ANYCHINTR only in combined IRQ mode.

Changes in v2:
- Update to kernel standards, enhance patch description, and refactor
 driver to use match data for hardware differentiation instead of
 compatible strings.

Jun Guo (3):
  dt-bindings: dma: arm-dma350: document generic and combined IRQ
    topologies
  dma: arm-dma350: support combined IRQ mode with runtime IRQ topology
    detection
  arm64: dts: cix: add DT nodes for DMA

 .../devicetree/bindings/dma/arm,dma-350.yaml  |  31 ++--
 arch/arm64/boot/dts/cix/sky1.dtsi             |   7 +
 drivers/dma/arm-dma350.c                      | 165 +++++++++++++++---
 3 files changed, 167 insertions(+), 36 deletions(-)

-- 
2.34.1

[PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Jun Guo]

Update the DMA-350 DT binding to match the current driver behavior.

Allow both:
- "arm,dma-350" as the generic compatible, and
- "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.

Also document interrupt topology variants supported by hardware
integration:
- one combined interrupt for all channels, or
- one interrupt per channel (up to 8 channels).

This patch is Assisted-by: Cursor: GPT-5.3 Codex.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
Link: https://lore.kernel.org/r/20251216123026.3519923-2-jun.guo@cixtech.com
---
 .../devicetree/bindings/dma/arm,dma-350.yaml  | 31 +++++++++++++------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
index 429f682f15d8..3639ce0d5054 100644
--- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
+++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
@@ -14,7 +14,11 @@ allOf:
 
 properties:
   compatible:
-    const: arm,dma-350
+    oneOf:
+      - const: arm,dma-350
+      - items:
+          - const: cix,sky1-dma-350
+          - const: arm,dma-350
 
   reg:
     items:
@@ -22,15 +26,22 @@ properties:
 
   interrupts:
     minItems: 1
-    items:
-      - description: Channel 0 interrupt
-      - description: Channel 1 interrupt
-      - description: Channel 2 interrupt
-      - description: Channel 3 interrupt
-      - description: Channel 4 interrupt
-      - description: Channel 5 interrupt
-      - description: Channel 6 interrupt
-      - description: Channel 7 interrupt
+    maxItems: 8
+    description: |
+      The DMA controller may be configured with separate interrupts for each channel,
+      or with a single combined interrupt for all channels, depending on the SoC integration.
+    oneOf:
+      - items:
+          - description: Channel 0 interrupt
+          - description: Channel 1 interrupt
+          - description: Channel 2 interrupt
+          - description: Channel 3 interrupt
+          - description: Channel 4 interrupt
+          - description: Channel 5 interrupt
+          - description: Channel 6 interrupt
+          - description: Channel 7 interrupt
+      - items:
+          - description: Combined interrupt shared by all channels
 
   "#dma-cells":
     const: 1
-- 
2.34.1

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Krzysztof Kozlowski]

On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
> Update the DMA-350 DT binding to match the current driver behavior.
> 
> Allow both:
> - "arm,dma-350" as the generic compatible, and
> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
> 
> Also document interrupt topology variants supported by hardware
> integration:
> - one combined interrupt for all channels, or
> - one interrupt per channel (up to 8 channels).
> 
> This patch is Assisted-by: Cursor: GPT-5.3 Codex.

Wrong tag, please read carefully the guideline before using LLM tools.

> 
> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> Link: https://lore.kernel.org/r/20251216123026.3519923-2-jun.guo@cixtech.com

What does this express? Changelog link? Then keep it in the changelog
--- part.


> ---
>  .../devicetree/bindings/dma/arm,dma-350.yaml  | 31 +++++++++++++------
>  1 file changed, 21 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> index 429f682f15d8..3639ce0d5054 100644
> --- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> @@ -14,7 +14,11 @@ allOf:
>  
>  properties:
>    compatible:
> -    const: arm,dma-350
> +    oneOf:
> +      - const: arm,dma-350
> +      - items:
> +          - const: cix,sky1-dma-350
> +          - const: arm,dma-350
>  
>    reg:
>      items:
> @@ -22,15 +26,22 @@ properties:
>  
>    interrupts:
>      minItems: 1
> -    items:
> -      - description: Channel 0 interrupt
> -      - description: Channel 1 interrupt
> -      - description: Channel 2 interrupt
> -      - description: Channel 3 interrupt
> -      - description: Channel 4 interrupt
> -      - description: Channel 5 interrupt
> -      - description: Channel 6 interrupt
> -      - description: Channel 7 interrupt
> +    maxItems: 8
> +    description: |
> +      The DMA controller may be configured with separate interrupts for each channel,
> +      or with a single combined interrupt for all channels, depending on the SoC integration.

And more important - you must review the LLM microslop output before
posting and adjust it to Linux kernel coding style. Don't send
unredacted tool output.

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Peter Chen]

On 26-03-20 10:12:53, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
> > Update the DMA-350 DT binding to match the current driver behavior.
> >
> > Allow both:
> > - "arm,dma-350" as the generic compatible, and
> > - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
> >
> > Also document interrupt topology variants supported by hardware
> > integration:
> > - one combined interrupt for all channels, or
> > - one interrupt per channel (up to 8 channels).
> >
> > This patch is Assisted-by: Cursor: GPT-5.3 Codex.
> 
> Wrong tag, please read carefully the guideline before using LLM tools.
> 

Hi Krzysztof,

It is the trade off for coding-assistants.rst suggestion and
passing checkpatch.pl. Currently, checkpatch.pl reports the
error for tag without email address. So we choose to add tag
description at patch context.

Peter

> >
> > Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> > Link: https://lore.kernel.org/r/20251216123026.3519923-2-jun.guo@cixtech.com
> 
> What does this express? Changelog link? Then keep it in the changelog
> --- part.
> 
> 
> > ---
> >  .../devicetree/bindings/dma/arm,dma-350.yaml  | 31 +++++++++++++------
> >  1 file changed, 21 insertions(+), 10 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> > index 429f682f15d8..3639ce0d5054 100644
> > --- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> > +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> > @@ -14,7 +14,11 @@ allOf:
> >
> >  properties:
> >    compatible:
> > -    const: arm,dma-350
> > +    oneOf:
> > +      - const: arm,dma-350
> > +      - items:
> > +          - const: cix,sky1-dma-350
> > +          - const: arm,dma-350
> >
> >    reg:
> >      items:
> > @@ -22,15 +26,22 @@ properties:
> >
> >    interrupts:
> >      minItems: 1
> > -    items:
> > -      - description: Channel 0 interrupt
> > -      - description: Channel 1 interrupt
> > -      - description: Channel 2 interrupt
> > -      - description: Channel 3 interrupt
> > -      - description: Channel 4 interrupt
> > -      - description: Channel 5 interrupt
> > -      - description: Channel 6 interrupt
> > -      - description: Channel 7 interrupt
> > +    maxItems: 8
> > +    description: |
> > +      The DMA controller may be configured with separate interrupts for each channel,
> > +      or with a single combined interrupt for all channels, depending on the SoC integration.
> 
> And more important - you must review the LLM microslop output before
> posting and adjust it to Linux kernel coding style. Don't send
> unredacted tool output.
> 
> Best regards,
> Krzysztof
> 

-- 

Best regards,
Peter

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Krzysztof Kozlowski]

On 20/03/2026 10:38, Peter Chen wrote:
> On 26-03-20 10:12:53, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL
>>
>> On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
>>> Update the DMA-350 DT binding to match the current driver behavior.
>>>
>>> Allow both:
>>> - "arm,dma-350" as the generic compatible, and
>>> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
>>>
>>> Also document interrupt topology variants supported by hardware
>>> integration:
>>> - one combined interrupt for all channels, or
>>> - one interrupt per channel (up to 8 channels).
>>>
>>> This patch is Assisted-by: Cursor: GPT-5.3 Codex.
>>
>> Wrong tag, please read carefully the guideline before using LLM tools.
>>
> 
> Hi Krzysztof,
> 
> It is the trade off for coding-assistants.rst suggestion and
> passing checkpatch.pl. Currently, checkpatch.pl reports the
> error for tag without email address. So we choose to add tag
> description at patch context.

You still have to use correct tag. You ignored rest of the email
message, so I assume you agree that you should not send LLM microslop?

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Peter Chen]

On 26-03-20 10:43:10, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On 20/03/2026 10:38, Peter Chen wrote:
> > On 26-03-20 10:12:53, Krzysztof Kozlowski wrote:
> >> EXTERNAL EMAIL
> >>
> >> On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
> >>> Update the DMA-350 DT binding to match the current driver behavior.
> >>>
> >>> Allow both:
> >>> - "arm,dma-350" as the generic compatible, and
> >>> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
> >>>
> >>> Also document interrupt topology variants supported by hardware
> >>> integration:
> >>> - one combined interrupt for all channels, or
> >>> - one interrupt per channel (up to 8 channels).
> >>>
> >>> This patch is Assisted-by: Cursor: GPT-5.3 Codex.
> >>
> >> Wrong tag, please read carefully the guideline before using LLM tools.
> >>
> >
> > Hi Krzysztof,
> >
> > It is the trade off for coding-assistants.rst suggestion and
> > passing checkpatch.pl. Currently, checkpatch.pl reports the
> > error for tag without email address. So we choose to add tag
> > description at patch context.
> 
> You still have to use correct tag.

You mean even checkpatch.pl reports below error, we still add it
"Assisted-by: Cursor: GPT-5.3 Codex" as tag?

WARNING: Non-standard signature: Assisted-by:
#14:
Assisted-by: Cursor: GPT-5.3 Codex

ERROR: Unrecognized email address: 'Cursor: GPT-5.3 Codex'
#14:
Assisted-by: Cursor: GPT-5.3 Codex

> You ignored rest of the email
> message, so I assume you agree that you should not send LLM microslop?
> 

I am not the patch author, Jun will reply it.
I come in to discuss this patch duo to I suggested Jun adding LLM tag
at patch context.

-- 

Best regards,
Peter

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Krzysztof Kozlowski]

On 20/03/2026 10:58, Peter Chen wrote:
> On 26-03-20 10:43:10, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL
>>
>> On 20/03/2026 10:38, Peter Chen wrote:
>>> On 26-03-20 10:12:53, Krzysztof Kozlowski wrote:
>>>> EXTERNAL EMAIL
>>>>
>>>> On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
>>>>> Update the DMA-350 DT binding to match the current driver behavior.
>>>>>
>>>>> Allow both:
>>>>> - "arm,dma-350" as the generic compatible, and
>>>>> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
>>>>>
>>>>> Also document interrupt topology variants supported by hardware
>>>>> integration:
>>>>> - one combined interrupt for all channels, or
>>>>> - one interrupt per channel (up to 8 channels).
>>>>>
>>>>> This patch is Assisted-by: Cursor: GPT-5.3 Codex.
>>>>
>>>> Wrong tag, please read carefully the guideline before using LLM tools.
>>>>
>>>
>>> Hi Krzysztof,
>>>
>>> It is the trade off for coding-assistants.rst suggestion and
>>> passing checkpatch.pl. Currently, checkpatch.pl reports the
>>> error for tag without email address. So we choose to add tag
>>> description at patch context.
>>
>> You still have to use correct tag.
> 
> You mean even checkpatch.pl reports below error, we still add it
> "Assisted-by: Cursor: GPT-5.3 Codex" as tag?

Yes, after fixing the contents (that's not entirely correct format I
think). Hopefully someone will fix checkpatch one day...

> 
> WARNING: Non-standard signature: Assisted-by:
> #14:
> Assisted-by: Cursor: GPT-5.3 Codex
> 
> ERROR: Unrecognized email address: 'Cursor: GPT-5.3 Codex'
> #14:
> Assisted-by: Cursor: GPT-5.3 Codex
> 
>> You ignored rest of the email
>> message, so I assume you agree that you should not send LLM microslop?
>>
> 
> I am not the patch author, Jun will reply it.

Ah, sorry, I did not notice that.


Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Jun Guo]

Hi Krzysztof,

On 3/20/2026 6:04 PM, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On 20/03/2026 10:58, Peter Chen wrote:
>> On 26-03-20 10:43:10, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL
>>>
>>> On 20/03/2026 10:38, Peter Chen wrote:
>>>> On 26-03-20 10:12:53, Krzysztof Kozlowski wrote:
>>>>> EXTERNAL EMAIL
>>>>>
>>>>> On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
>>>>>> Update the DMA-350 DT binding to match the current driver behavior.
>>>>>>
>>>>>> Allow both:
>>>>>> - "arm,dma-350" as the generic compatible, and
>>>>>> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
>>>>>>
>>>>>> Also document interrupt topology variants supported by hardware
>>>>>> integration:
>>>>>> - one combined interrupt for all channels, or
>>>>>> - one interrupt per channel (up to 8 channels).
>>>>>>
>>>>>> This patch is Assisted-by: Cursor: GPT-5.3 Codex.
>>>>>
>>>>> Wrong tag, please read carefully the guideline before using LLM tools.
>>>>>
>>>>
>>>> Hi Krzysztof,
>>>>
>>>> It is the trade off for coding-assistants.rst suggestion and
>>>> passing checkpatch.pl. Currently, checkpatch.pl reports the
>>>> error for tag without email address. So we choose to add tag
>>>> description at patch context.
>>>
>>> You still have to use correct tag.
>>
>> You mean even checkpatch.pl reports below error, we still add it
>> "Assisted-by: Cursor: GPT-5.3 Codex" as tag?
> 
> Yes, after fixing the contents (that's not entirely correct format I
> think). Hopefully someone will fix checkpatch one day...
I cannot find any commit records referencing AI via "Co-developed-by" in 
the latest kernel GitHub repository, and I also cannot locate any text 
describing the correct way to cite AI in the submitting-patches.rst 
file. In this case, how can I confirm the current correct format?
> 
>>
>> WARNING: Non-standard signature: Assisted-by:
>> #14:
>> Assisted-by: Cursor: GPT-5.3 Codex
>>
>> ERROR: Unrecognized email address: 'Cursor: GPT-5.3 Codex'
>> #14:
>> Assisted-by: Cursor: GPT-5.3 Codex
>>
>>> You ignored rest of the email
>>> message, so I assume you agree that you should not send LLM microslop?
>>>
>>
>> I am not the patch author, Jun will reply it.
> 
> Ah, sorry, I did not notice that.
> 
> 
> Best regards,
> Krzysztof

Best regards,
Jun

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Krzysztof Kozlowski]

On 23/03/2026 03:09, Jun Guo wrote:
> Hi Krzysztof,
> 
> On 3/20/2026 6:04 PM, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL
>>
>> On 20/03/2026 10:58, Peter Chen wrote:
>>> On 26-03-20 10:43:10, Krzysztof Kozlowski wrote:
>>>> EXTERNAL EMAIL
>>>>
>>>> On 20/03/2026 10:38, Peter Chen wrote:
>>>>> On 26-03-20 10:12:53, Krzysztof Kozlowski wrote:
>>>>>> EXTERNAL EMAIL
>>>>>>
>>>>>> On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
>>>>>>> Update the DMA-350 DT binding to match the current driver behavior.
>>>>>>>
>>>>>>> Allow both:
>>>>>>> - "arm,dma-350" as the generic compatible, and
>>>>>>> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
>>>>>>>
>>>>>>> Also document interrupt topology variants supported by hardware
>>>>>>> integration:
>>>>>>> - one combined interrupt for all channels, or
>>>>>>> - one interrupt per channel (up to 8 channels).
>>>>>>>
>>>>>>> This patch is Assisted-by: Cursor: GPT-5.3 Codex.
>>>>>>
>>>>>> Wrong tag, please read carefully the guideline before using LLM tools.
>>>>>>
>>>>>
>>>>> Hi Krzysztof,
>>>>>
>>>>> It is the trade off for coding-assistants.rst suggestion and
>>>>> passing checkpatch.pl. Currently, checkpatch.pl reports the
>>>>> error for tag without email address. So we choose to add tag
>>>>> description at patch context.
>>>>
>>>> You still have to use correct tag.
>>>
>>> You mean even checkpatch.pl reports below error, we still add it
>>> "Assisted-by: Cursor: GPT-5.3 Codex" as tag?
>>
>> Yes, after fixing the contents (that's not entirely correct format I
>> think). Hopefully someone will fix checkpatch one day...
> I cannot find any commit records referencing AI via "Co-developed-by" in 
> the latest kernel GitHub repository, and I also cannot locate any text 
> describing the correct way to cite AI in the submitting-patches.rst 
> file. In this case, how can I confirm the current correct format?

If you do not want to read coding with assistant guideline and follow
its words, then please don't send code created with such tools. Do you
even have full copyrights to send it here? What license was used by the
tool to generate you this code?

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Jun Guo]

On 3/23/2026 3:27 PM, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On 23/03/2026 03:09, Jun Guo wrote:
>> Hi Krzysztof,
>>
>> On 3/20/2026 6:04 PM, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL
>>>
>>> On 20/03/2026 10:58, Peter Chen wrote:
>>>> On 26-03-20 10:43:10, Krzysztof Kozlowski wrote:
>>>>> EXTERNAL EMAIL
>>>>>
>>>>> On 20/03/2026 10:38, Peter Chen wrote:
>>>>>> On 26-03-20 10:12:53, Krzysztof Kozlowski wrote:
>>>>>>> EXTERNAL EMAIL
>>>>>>>
>>>>>>> On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
>>>>>>>> Update the DMA-350 DT binding to match the current driver behavior.
>>>>>>>>
>>>>>>>> Allow both:
>>>>>>>> - "arm,dma-350" as the generic compatible, and
>>>>>>>> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
>>>>>>>>
>>>>>>>> Also document interrupt topology variants supported by hardware
>>>>>>>> integration:
>>>>>>>> - one combined interrupt for all channels, or
>>>>>>>> - one interrupt per channel (up to 8 channels).
>>>>>>>>
>>>>>>>> This patch is Assisted-by: Cursor: GPT-5.3 Codex.
>>>>>>>
>>>>>>> Wrong tag, please read carefully the guideline before using LLM tools.
>>>>>>>
>>>>>>
>>>>>> Hi Krzysztof,
>>>>>>
>>>>>> It is the trade off for coding-assistants.rst suggestion and
>>>>>> passing checkpatch.pl. Currently, checkpatch.pl reports the
>>>>>> error for tag without email address. So we choose to add tag
>>>>>> description at patch context.
>>>>>
>>>>> You still have to use correct tag.
>>>>
>>>> You mean even checkpatch.pl reports below error, we still add it
>>>> "Assisted-by: Cursor: GPT-5.3 Codex" as tag?
>>>
>>> Yes, after fixing the contents (that's not entirely correct format I
>>> think). Hopefully someone will fix checkpatch one day...
>> I cannot find any commit records referencing AI via "Co-developed-by" in
>> the latest kernel GitHub repository, and I also cannot locate any text
>> describing the correct way to cite AI in the submitting-patches.rst
>> file. In this case, how can I confirm the current correct format?
> 
> If you do not want to read coding with assistant guideline and follow
> its words, then please don't send code created with such tools. Do you
> even have full copyrights to send it here? What license was used by the
> tool to generate you this code?
Sorry, I overlooked the programming assistant guidelines. I will comply 
with the requirements of the programming assistant guidelines and 
resubmit a new patch.
> 
> Best regards,
> Krzysztof

Best regards,
Jun

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Jun Guo]

On 3/20/2026 5:12 PM, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On Thu, Mar 19, 2026 at 06:17:21PM +0800, Jun Guo wrote:
>> Update the DMA-350 DT binding to match the current driver behavior.
>>
>> Allow both:
>> - "arm,dma-350" as the generic compatible, and
>> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
>>
>> Also document interrupt topology variants supported by hardware
>> integration:
>> - one combined interrupt for all channels, or
>> - one interrupt per channel (up to 8 channels).
>>
>> This patch is Assisted-by: Cursor: GPT-5.3 Codex.
> 
> Wrong tag, please read carefully the guideline before using LLM tools.
Okay. I will temporarily disregard the check patch warnings in the next 
version and correct the format of the AI-generated tag.

> 
>>
>> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
>> Link: https://lore.kernel.org/r/20251216123026.3519923-2-jun.guo@cixtech.com
> 
> What does this express? Changelog link? Then keep it in the changelog
> --- part.
Okay, I'll address this in the next version of the patch.

> 
> 
>> ---
>>   .../devicetree/bindings/dma/arm,dma-350.yaml  | 31 +++++++++++++------
>>   1 file changed, 21 insertions(+), 10 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
>> index 429f682f15d8..3639ce0d5054 100644
>> --- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
>> +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
>> @@ -14,7 +14,11 @@ allOf:
>>
>>   properties:
>>     compatible:
>> -    const: arm,dma-350
>> +    oneOf:
>> +      - const: arm,dma-350
>> +      - items:
>> +          - const: cix,sky1-dma-350
>> +          - const: arm,dma-350
>>
>>     reg:
>>       items:
>> @@ -22,15 +26,22 @@ properties:
>>
>>     interrupts:
>>       minItems: 1
>> -    items:
>> -      - description: Channel 0 interrupt
>> -      - description: Channel 1 interrupt
>> -      - description: Channel 2 interrupt
>> -      - description: Channel 3 interrupt
>> -      - description: Channel 4 interrupt
>> -      - description: Channel 5 interrupt
>> -      - description: Channel 6 interrupt
>> -      - description: Channel 7 interrupt
>> +    maxItems: 8
>> +    description: |
>> +      The DMA controller may be configured with separate interrupts for each channel,
>> +      or with a single combined interrupt for all channels, depending on the SoC integration.
> 
> And more important - you must review the LLM microslop output before
> posting and adjust it to Linux kernel coding style. Don't send
> unredacted tool output.
> 
Actually, this part of the description was not AI-generated. However, 
I’d like to confirm the issue you mentioned: are you saying that this 
description is written too verbosely?
Then, do you think there are still issues with the revised version?
   interrupts:
     minItems: 1
     maxItems: 8
     description:
       Either one interrupt per channel (8 interrupts), or one
       combined interrupt for all channels.

> Best regards,
> Krzysztof
> 

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Krzysztof Kozlowski]

On 20/03/2026 11:28, Jun Guo wrote:
>>> +    description: |
>>> +      The DMA controller may be configured with separate interrupts for each channel,
>>> +      or with a single combined interrupt for all channels, depending on the SoC integration.
>>
>> And more important - you must review the LLM microslop output before
>> posting and adjust it to Linux kernel coding style. Don't send
>> unredacted tool output.
>>
> Actually, this part of the description was not AI-generated. However, 
> I’d like to confirm the issue you mentioned: are you saying that this 
> description is written too verbosely?
> Then, do you think there are still issues with the revised version?
>    interrupts:
>      minItems: 1
>      maxItems: 8
>      description:
>        Either one interrupt per channel (8 interrupts), or one
>        combined interrupt for all channels.

No, it is not wrapped according to Linux coding style.

Please wrap code according to the preferred limit expressed in Kernel
coding style (checkpatch is not a coding style description, but only a
tool).  However don't wrap blindly (see Kernel coding style).

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies

[Jun Guo]

On 3/20/2026 9:12 PM, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On 20/03/2026 11:28, Jun Guo wrote:
>>>> +    description: |
>>>> +      The DMA controller may be configured with separate interrupts for each channel,
>>>> +      or with a single combined interrupt for all channels, depending on the SoC integration.
>>>
>>> And more important - you must review the LLM microslop output before
>>> posting and adjust it to Linux kernel coding style. Don't send
>>> unredacted tool output.
>>>
>> Actually, this part of the description was not AI-generated. However,
>> I’d like to confirm the issue you mentioned: are you saying that this
>> description is written too verbosely?
>> Then, do you think there are still issues with the revised version?
>>     interrupts:
>>       minItems: 1
>>       maxItems: 8
>>       description:
>>         Either one interrupt per channel (8 interrupts), or one
>>         combined interrupt for all channels.
> 
> No, it is not wrapped according to Linux coding style.
> 
> Please wrap code according to the preferred limit expressed in Kernel
> coding style (checkpatch is not a coding style description, but only a
> tool).  However don't wrap blindly (see Kernel coding style).
> 
Thank you for your patience. I have clearly understood your points and 
will incorporate all of your feedback when revising the V3 version of 
the patch.

Best regards,
Jun

[PATCH v3 2/3] dma: arm-dma350: support combined IRQ mode with runtime IRQ topology detection

[Jun Guo]

DMA-350 can be integrated with either per-channel IRQ lines or a single
combined IRQ line. Add support for both layouts in a unified way.

Detect IRQ topology at probe time via platform_irq_count(), then:
- request one global IRQ and enable DMANSECCTRL.INTREN_ANYCHINTR for
  combined mode, or
- request per-channel IRQs for channel mode.

Refactor IRQ completion/error handling into a shared channel handler
used by both global and per-channel IRQ paths, and guard against IRQs
arriving without an active descriptor.

This patch is Assisted-by: Cursor: GPT-5.3 Codex.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
Link: https://lore.kernel.org/r/20251216123026.3519923-3-jun.guo@cixtech.com
---
 drivers/dma/arm-dma350.c | 165 +++++++++++++++++++++++++++++++++------
 1 file changed, 139 insertions(+), 26 deletions(-)

diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
index 84220fa83029..2cf6f783b44f 100644
--- a/drivers/dma/arm-dma350.c
+++ b/drivers/dma/arm-dma350.c
@@ -14,6 +14,7 @@
 #include "virt-dma.h"
 
 #define DMAINFO			0x0f00
+#define DRIVER_NAME		"arm-dma350"
 
 #define DMA_BUILDCFG0		0xb0
 #define DMA_CFG_DATA_WIDTH	GENMASK(18, 16)
@@ -142,6 +143,9 @@
 #define LINK_LINKADDR		BIT(30)
 #define LINK_LINKADDRHI		BIT(31)
 
+/* DMA NONSECURE CONTROL REGISTER */
+#define DMANSECCTRL		0x20c
+#define INTREN_ANYCHINTR_EN	BIT(0)
 
 enum ch_ctrl_donetype {
 	CH_CTRL_DONETYPE_NONE = 0,
@@ -192,6 +196,7 @@ struct d350_chan {
 
 struct d350 {
 	struct dma_device dma;
+	void __iomem *base;
 	int nchan;
 	int nreq;
 	struct d350_chan channels[] __counted_by(nchan);
@@ -461,18 +466,40 @@ static void d350_issue_pending(struct dma_chan *chan)
 	spin_unlock_irqrestore(&dch->vc.lock, flags);
 }
 
-static irqreturn_t d350_irq(int irq, void *data)
+static void d350_handle_chan_irq(struct d350_chan *dch, struct device *dev,
+				 int chan_id, u32 ch_status)
 {
-	struct d350_chan *dch = data;
-	struct device *dev = dch->vc.chan.device->dev;
-	struct virt_dma_desc *vd = &dch->desc->vd;
-	u32 ch_status;
+	struct virt_dma_desc *vd;
+	bool intr_done = ch_status & CH_STAT_INTR_DONE;
+	bool intr_err = ch_status & CH_STAT_INTR_ERR;
 
-	ch_status = readl(dch->base + CH_STATUS);
-	if (!ch_status)
-		return IRQ_NONE;
+	if (!intr_done && !intr_err) {
+		if (chan_id >= 0)
+			dev_warn(dev, "Channel %d unexpected IRQ: 0x%08x\n",
+				 chan_id, ch_status);
+		else
+			dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status);
+		writel_relaxed(ch_status, dch->base + CH_STATUS);
+		return;
+	}
+
+	writel_relaxed(ch_status, dch->base + CH_STATUS);
+
+	spin_lock(&dch->vc.lock);
+	if (!dch->desc) {
+		if (chan_id >= 0)
+			dev_warn(dev,
+				 "Channel %d IRQ without active descriptor: 0x%08x\n",
+				 chan_id, ch_status);
+		else
+			dev_warn(dev, "IRQ without active descriptor: 0x%08x\n",
+				 ch_status);
+		spin_unlock(&dch->vc.lock);
+		return;
+	}
 
-	if (ch_status & CH_STAT_INTR_ERR) {
+	vd = &dch->desc->vd;
+	if (intr_err) {
 		u32 errinfo = readl_relaxed(dch->base + CH_ERRINFO);
 
 		if (errinfo & (CH_ERRINFO_AXIRDPOISERR | CH_ERRINFO_AXIRDRESPERR))
@@ -483,14 +510,10 @@ static irqreturn_t d350_irq(int irq, void *data)
 			vd->tx_result.result = DMA_TRANS_ABORTED;
 
 		vd->tx_result.residue = d350_get_residue(dch);
-	} else if (!(ch_status & CH_STAT_INTR_DONE)) {
-		dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status);
 	}
-	writel_relaxed(ch_status, dch->base + CH_STATUS);
 
-	spin_lock(&dch->vc.lock);
 	vchan_cookie_complete(vd);
-	if (ch_status & CH_STAT_INTR_DONE) {
+	if (intr_done) {
 		dch->status = DMA_COMPLETE;
 		dch->residue = 0;
 		d350_start_next(dch);
@@ -499,6 +522,44 @@ static irqreturn_t d350_irq(int irq, void *data)
 		dch->residue = vd->tx_result.residue;
 	}
 	spin_unlock(&dch->vc.lock);
+}
+
+static irqreturn_t d350_global_irq(int irq, void *data)
+{
+	struct d350 *dmac = (struct d350 *)data;
+	irqreturn_t ret = IRQ_NONE;
+	int i;
+
+	(void)irq;
+
+	for (i = 0; i < dmac->nchan; i++) {
+		struct d350_chan *dch = &dmac->channels[i];
+		u32 ch_status;
+
+		ch_status = readl(dch->base + CH_STATUS);
+		if (!ch_status)
+			continue;
+
+		ret = IRQ_HANDLED;
+		d350_handle_chan_irq(dch, dmac->dma.dev, i, ch_status);
+	}
+
+	return ret;
+}
+
+static irqreturn_t d350_channel_irq(int irq, void *data)
+{
+	struct d350_chan *dch = data;
+	struct device *dev = dch->vc.chan.device->dev;
+	u32 ch_status;
+
+	(void)irq;
+
+	ch_status = readl(dch->base + CH_STATUS);
+	if (!ch_status)
+		return IRQ_NONE;
+
+	d350_handle_chan_irq(dch, dev, -1, ch_status);
 
 	return IRQ_HANDLED;
 }
@@ -506,10 +567,18 @@ static irqreturn_t d350_irq(int irq, void *data)
 static int d350_alloc_chan_resources(struct dma_chan *chan)
 {
 	struct d350_chan *dch = to_d350_chan(chan);
-	int ret = request_irq(dch->irq, d350_irq, IRQF_SHARED,
-			      dev_name(&dch->vc.chan.dev->device), dch);
-	if (!ret)
-		writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN);
+	int ret = 0;
+
+	if (dch->irq >= 0) {
+		ret = request_irq(dch->irq, d350_channel_irq, IRQF_SHARED,
+				  dev_name(&dch->vc.chan.dev->device), dch);
+		if (ret) {
+			dev_err(chan->device->dev, "Failed to request IRQ %d\n", dch->irq);
+			return ret;
+		}
+	}
+
+	writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN);
 
 	return ret;
 }
@@ -519,18 +588,21 @@ static void d350_free_chan_resources(struct dma_chan *chan)
 	struct d350_chan *dch = to_d350_chan(chan);
 
 	writel_relaxed(0, dch->base + CH_INTREN);
-	free_irq(dch->irq, dch);
+	if (dch->irq >= 0) {
+		free_irq(dch->irq, dch);
+		dch->irq = -EINVAL;
+	}
 	vchan_free_chan_resources(&dch->vc);
 }
 
 static int d350_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	struct d350 *dmac;
+	struct d350 *dmac = NULL;
 	void __iomem *base;
 	u32 reg;
-	int ret, nchan, dw, aw, r, p;
-	bool coherent, memset;
+	int ret, nchan, dw, aw, r, p, irq_count;
+	bool coherent, memset, combined_irq;
 
 	base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(base))
@@ -556,6 +628,7 @@ static int d350_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	dmac->nchan = nchan;
+	dmac->base = base;
 
 	reg = readl_relaxed(base + DMAINFO + DMA_BUILDCFG1);
 	dmac->nreq = FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg);
@@ -582,12 +655,46 @@ static int d350_probe(struct platform_device *pdev)
 	dmac->dma.device_issue_pending = d350_issue_pending;
 	INIT_LIST_HEAD(&dmac->dma.channels);
 
+	irq_count = platform_irq_count(pdev);
+	if (irq_count < 0)
+		return dev_err_probe(dev, irq_count,
+				     "Failed to count interrupts\n");
+
+	if (irq_count == 1) {
+		combined_irq = true;
+	} else if (irq_count >= nchan) {
+		combined_irq = false;
+	} else {
+		return dev_err_probe(dev, -EINVAL,
+				     "Invalid IRQ count %d for %d channels\n",
+				     irq_count, nchan);
+	}
+
+	if (combined_irq) {
+		int host_irq = platform_get_irq(pdev, 0);
+
+		if (host_irq < 0)
+			return dev_err_probe(dev, host_irq,
+					     "Failed to get IRQ\n");
+
+		ret = devm_request_irq(&pdev->dev, host_irq, d350_global_irq,
+				       IRQF_SHARED, DRIVER_NAME, dmac);
+		if (ret)
+			return dev_err_probe(
+				dev, ret,
+				"Failed to request the combined IRQ %d\n",
+				host_irq);
+		/* Combined Non-Secure Channel Interrupt Enable */
+		writel_relaxed(INTREN_ANYCHINTR_EN, dmac->base + DMANSECCTRL);
+	}
+
 	/* Would be nice to have per-channel caps for this... */
 	memset = true;
 	for (int i = 0; i < nchan; i++) {
 		struct d350_chan *dch = &dmac->channels[i];
 
 		dch->base = base + DMACH(i);
+		dch->irq = -EINVAL;
 		writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD);
 
 		reg = readl_relaxed(dch->base + CH_BUILDCFG1);
@@ -595,10 +702,15 @@ static int d350_probe(struct platform_device *pdev)
 			dev_warn(dev, "No command link support on channel %d\n", i);
 			continue;
 		}
-		dch->irq = platform_get_irq(pdev, i);
-		if (dch->irq < 0)
-			return dev_err_probe(dev, dch->irq,
-					     "Failed to get IRQ for channel %d\n", i);
+
+		if (!combined_irq) {
+			dch->irq = platform_get_irq(pdev, i);
+			if (dch->irq < 0)
+				return dev_err_probe(
+					dev, dch->irq,
+					"Failed to get IRQ for channel %d\n",
+					i);
+		}
 
 		dch->has_wrap = FIELD_GET(CH_CFG_HAS_WRAP, reg);
 		dch->has_trig = FIELD_GET(CH_CFG_HAS_TRIGIN, reg) &
@@ -640,6 +752,7 @@ static void d350_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id d350_of_match[] __maybe_unused = {
+	{ .compatible = "cix,sky1-dma-350" },
 	{ .compatible = "arm,dma-350" },
 	{}
 };
-- 
2.34.1

[PATCH v3 3/3] arm64: dts: cix: add DT nodes for DMA

[Jun Guo]

Add the device tree node for the dma controller of the CIX SKY1 SoC.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
Link: https://lore.kernel.org/r/20251216123026.3519923-4-jun.guo@cixtech.com
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 210739beac6d..1185c99d8d9d 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -480,6 +480,13 @@ iomuxc: pinctrl@4170000 {
 			reg = <0x0 0x04170000 0x0 0x1000>;
 		};
 
+		fch_dmac: dma-controller@4190000 {
+			compatible = "cix,sky1-dma-350", "arm,dma-350";
+			reg = <0x0 0x4190000 0x0 0x10000>;
+			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+			#dma-cells = <1>;
+		};
+
 		mbox_ap2se: mailbox@5060000 {
 			compatible = "cix,sky1-mbox";
 			reg = <0x0 0x05060000 0x0 0x10000>;
-- 
2.34.1

Re: [PATCH v3 3/3] arm64: dts: cix: add DT nodes for DMA

[Krzysztof Kozlowski]

On Thu, Mar 19, 2026 at 06:17:23PM +0800, Jun Guo wrote:
> Add the device tree node for the dma controller of the CIX SKY1 SoC.
> 
> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> Link: https://lore.kernel.org/r/20251216123026.3519923-4-jun.guo@cixtech.com

How useful is this link? It points to exactly same code, so what does it
tell?

Drop all Links from your patches and read the docs how they are used.

Best regards,
Krzysztof

Re: [PATCH v3 3/3] arm64: dts: cix: add DT nodes for DMA

[Jun Guo]

On 3/20/2026 5:13 PM, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On Thu, Mar 19, 2026 at 06:17:23PM +0800, Jun Guo wrote:
>> Add the device tree node for the dma controller of the CIX SKY1 SoC.
>>
>> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
>> Link: https://lore.kernel.org/r/20251216123026.3519923-4-jun.guo@cixtech.com
> 
> How useful is this link? It points to exactly same code, so what does it
> tell?
> 
> Drop all Links from your patches and read the docs how they are used.
> 
Thank you for the reminder. I will fix these links in the next version
of the patch.
> Best regards,
> Krzysztof
> 

Best regards,
Jun