[PATCH v3] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[PATCH v3] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[MidG971]

The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
This chip is currently modeled only as a fixed regulator
(vcc3v3_pi6c_03), with no clock output representation.

The PI6C20100 is a clock generator, not a power supply. Model it
properly as a gated-fixed-clock, following the pattern established
for the Rock 5 ITX and other boards with similar PCIe clock buffer
chips.

The regulator node is kept as-is since it controls the power supply
to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
references this regulator as its vdd-supply and provides a proper
100MHz clock output. The pcie3x2 node is updated to include the
pipe and reference clocks, matching the approach used in
rk3588-rock-5-itx.dts.

Assisted-by: Claude:claude-3-opus
Signed-off-by: MidG971 <midgy971@gmail.com>
---

Changes since v2 [1]:
 - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
 - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
   override (Shawn, referencing David's patch [2])

Changes since v1 [3]:
 - Drop phy-supply approach entirely (Jonas, Shawn)
 - Model PI6C20100 as gated-fixed-clock instead
 - Wire reference clock to pcie3x2 controller
 - Follow pattern from rk3588-rock-5-itx.dts

[1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
[2] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
[3] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/

 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
index c5f67dd6dfd9..1a2b3c4d5e6f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
@@ -56,7 +56,16 @@
 		};
 	};

-	/* pi6c pcie clock generator */
+	/* PI6C20100 PCIe reference clock buffer (100MHz) */
+	pcie30_refclk: pcie-clock-generator {
+		compatible = "gated-fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "pcie30_refclk";
+		vdd-supply = <&vcc3v3_pi6c_03>;
+	};
+
+	/* PI6C20100 power supply - active-high GPIO0_D4 */
 	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -553,6 +562,15 @@
 };

 &pcie3x2 {
+	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+		 <&cru CLK_PCIE30X2_AUX_NDFT>,
+		 <&cru CLK_PCIE30X2_PIPE_DFT>,
+		 <&pcie30_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk", "aux",
+		      "pipe", "ref";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie30x2m1_pins>;
 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
--
2.39.5

Re: [PATCH v3] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Shawn Lin]

在 2026/03/19 星期四 18:22, MidG971 写道:
> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> This chip is currently modeled only as a fixed regulator
> (vcc3v3_pi6c_03), with no clock output representation.
> 
> The PI6C20100 is a clock generator, not a power supply. Model it
> properly as a gated-fixed-clock, following the pattern established
> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> chips.
> 
> The regulator node is kept as-is since it controls the power supply
> to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
> references this regulator as its vdd-supply and provides a proper
> 100MHz clock output. The pcie3x2 node is updated to include the
> pipe and reference clocks, matching the approach used in
> rk3588-rock-5-itx.dts.

Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

> 
> Assisted-by: Claude:claude-3-opus
> Signed-off-by: MidG971 <midgy971@gmail.com>
> ---
> 
> Changes since v2 [1]:
>   - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
>   - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
>     override (Shawn, referencing David's patch [2])
> 
> Changes since v1 [3]:
>   - Drop phy-supply approach entirely (Jonas, Shawn)
>   - Model PI6C20100 as gated-fixed-clock instead
>   - Wire reference clock to pcie3x2 controller
>   - Follow pattern from rk3588-rock-5-itx.dts
> 
> [1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
> [2] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
> [3] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/
> 
>   arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
>   1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> index c5f67dd6dfd9..1a2b3c4d5e6f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> @@ -56,7 +56,16 @@
>   		};
>   	};
> 
> -	/* pi6c pcie clock generator */
> +	/* PI6C20100 PCIe reference clock buffer (100MHz) */
> +	pcie30_refclk: pcie-clock-generator {
> +		compatible = "gated-fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "pcie30_refclk";
> +		vdd-supply = <&vcc3v3_pi6c_03>;
> +	};
> +
> +	/* PI6C20100 power supply - active-high GPIO0_D4 */
>   	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
>   		compatible = "regulator-fixed";
>   		enable-active-high;
> @@ -553,6 +562,15 @@
>   };
> 
>   &pcie3x2 {
> +	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> +		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> +		 <&cru CLK_PCIE30X2_AUX_NDFT>,
> +		 <&cru CLK_PCIE30X2_PIPE_DFT>,
> +		 <&pcie30_refclk>;
> +	clock-names = "aclk_mst", "aclk_slv",
> +		      "aclk_dbi", "pclk", "aux",
> +		      "pipe", "ref";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&pcie30x2m1_pins>;
>   	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
> --
> 2.39.5
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
> 

Re: [PATCH v3] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Jonas Karlman]

Hi,

On 3/19/2026 11:22 AM, MidG971 wrote:
> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> This chip is currently modeled only as a fixed regulator
> (vcc3v3_pi6c_03), with no clock output representation.
> 
> The PI6C20100 is a clock generator, not a power supply. Model it
> properly as a gated-fixed-clock, following the pattern established
> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> chips.
> 
> The regulator node is kept as-is since it controls the power supply
> to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
> references this regulator as its vdd-supply and provides a proper
> 100MHz clock output. The pcie3x2 node is updated to include the
> pipe and reference clocks, matching the approach used in
> rk3588-rock-5-itx.dts.
> 
> Assisted-by: Claude:claude-3-opus
> Signed-off-by: MidG971 <midgy971@gmail.com>

Typically you should use your real name in SoB line, kernel docs state:

  using a known identity (sorry, no anonymous contributions.)

https://docs.kernel.org/process/submitting-patches.html

> ---
> 
> Changes since v2 [1]:
>  - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
>  - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
>    override (Shawn, referencing David's patch [2])
> 
> Changes since v1 [3]:
>  - Drop phy-supply approach entirely (Jonas, Shawn)
>  - Model PI6C20100 as gated-fixed-clock instead
>  - Wire reference clock to pcie3x2 controller
>  - Follow pattern from rk3588-rock-5-itx.dts
> 
> [1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
> [2] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
> [3] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/
> 
>  arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> index c5f67dd6dfd9..1a2b3c4d5e6f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
> @@ -56,7 +56,16 @@
>  		};
>  	};
> 
> -	/* pi6c pcie clock generator */
> +	/* PI6C20100 PCIe reference clock buffer (100MHz) */
> +	pcie30_refclk: pcie-clock-generator {
> +		compatible = "gated-fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "pcie30_refclk";
> +		vdd-supply = <&vcc3v3_pi6c_03>;

The vcc3v3_pi6c_03 regulator should also be removed in this patch,
as you state in the commit message, it is not a power supply.

Please convert to use enable-gpios prop.

Regards,
Jonas

> +	};
> +
> +	/* PI6C20100 power supply - active-high GPIO0_D4 */
>  	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
>  		compatible = "regulator-fixed";
>  		enable-active-high;
> @@ -553,6 +562,15 @@
>  };
> 
>  &pcie3x2 {
> +	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> +		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> +		 <&cru CLK_PCIE30X2_AUX_NDFT>,
> +		 <&cru CLK_PCIE30X2_PIPE_DFT>,
> +		 <&pcie30_refclk>;
> +	clock-names = "aclk_mst", "aclk_slv",
> +		      "aclk_dbi", "pclk", "aux",
> +		      "pipe", "ref";
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pcie30x2m1_pins>;
>  	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
> --
> 2.39.5
> 

Re: [PATCH v3] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Jonas Karlman]

Hi again,

On 3/19/2026 2:19 PM, Jonas Karlman wrote:
> Hi,
> 
> On 3/19/2026 11:22 AM, MidG971 wrote:
>> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
>> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
>> This chip is currently modeled only as a fixed regulator
>> (vcc3v3_pi6c_03), with no clock output representation.
>>
>> The PI6C20100 is a clock generator, not a power supply. Model it
>> properly as a gated-fixed-clock, following the pattern established
>> for the Rock 5 ITX and other boards with similar PCIe clock buffer
>> chips.
>>
>> The regulator node is kept as-is since it controls the power supply
>> to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
>> references this regulator as its vdd-supply and provides a proper
>> 100MHz clock output. The pcie3x2 node is updated to include the
>> pipe and reference clocks, matching the approach used in
>> rk3588-rock-5-itx.dts.
>>
>> Assisted-by: Claude:claude-3-opus
>> Signed-off-by: MidG971 <midgy971@gmail.com>
> 
> Typically you should use your real name in SoB line, kernel docs state:
> 
>   using a known identity (sorry, no anonymous contributions.)
> 
> https://docs.kernel.org/process/submitting-patches.html
> 
>> ---
>>
>> Changes since v2 [1]:
>>  - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
>>  - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
>>    override (Shawn, referencing David's patch [2])
>>
>> Changes since v1 [3]:
>>  - Drop phy-supply approach entirely (Jonas, Shawn)
>>  - Model PI6C20100 as gated-fixed-clock instead
>>  - Wire reference clock to pcie3x2 controller
>>  - Follow pattern from rk3588-rock-5-itx.dts
>>
>> [1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
>> [2] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
>> [3] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/
>>
>>  arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
>>  1 file changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> index c5f67dd6dfd9..1a2b3c4d5e6f 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>> @@ -56,7 +56,16 @@
>>  		};
>>  	};
>>
>> -	/* pi6c pcie clock generator */
>> +	/* PI6C20100 PCIe reference clock buffer (100MHz) */
>> +	pcie30_refclk: pcie-clock-generator {
>> +		compatible = "gated-fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <100000000>;
>> +		clock-output-names = "pcie30_refclk";
>> +		vdd-supply = <&vcc3v3_pi6c_03>;
> 
> The vcc3v3_pi6c_03 regulator should also be removed in this patch,
> as you state in the commit message, it is not a power supply.
> 
> Please convert to use enable-gpios prop.

I looked at wrong schematics, please disregard this comment :-)

Regards.
Jonas

> 
> Regards,
> Jonas
> 
>> +	};
>> +
>> +	/* PI6C20100 power supply - active-high GPIO0_D4 */
>>  	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
>>  		compatible = "regulator-fixed";
>>  		enable-active-high;
>> @@ -553,6 +562,15 @@
>>  };
>>
>>  &pcie3x2 {
>> +	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
>> +		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
>> +		 <&cru CLK_PCIE30X2_AUX_NDFT>,
>> +		 <&cru CLK_PCIE30X2_PIPE_DFT>,
>> +		 <&pcie30_refclk>;
>> +	clock-names = "aclk_mst", "aclk_slv",
>> +		      "aclk_dbi", "pclk", "aux",
>> +		      "pipe", "ref";
>>  	pinctrl-names = "default";
>>  	pinctrl-0 = <&pcie30x2m1_pins>;
>>  	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
>> --
>> 2.39.5
>>
> 

Re: [PATCH v3] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Krzysztof Kozlowski]

On 19/03/2026 11:22, MidG971 wrote:
> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> This chip is currently modeled only as a fixed regulator
> (vcc3v3_pi6c_03), with no clock output representation.
> 
> The PI6C20100 is a clock generator, not a power supply. Model it
> properly as a gated-fixed-clock, following the pattern established
> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> chips.
> 
> The regulator node is kept as-is since it controls the power supply
> to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
> references this regulator as its vdd-supply and provides a proper
> 100MHz clock output. The pcie3x2 node is updated to include the
> pipe and reference clocks, matching the approach used in
> rk3588-rock-5-itx.dts.
> 
> Assisted-by: Claude:claude-3-opus
> Signed-off-by: MidG971 <midgy971@gmail.com>

Anonymous contributions are not accepted. You must use your full name or
known to us identity (nickname is not a "known identity").

Best regards,
Krzysztof

Re: [PATCH v3] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock

[Jonas Karlman]

On 3/19/2026 2:29 PM, Jonas Karlman wrote:
> Hi again,
> 
> On 3/19/2026 2:19 PM, Jonas Karlman wrote:
>> Hi,
>>
>> On 3/19/2026 11:22 AM, MidG971 wrote:
>>> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
>>> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
>>> This chip is currently modeled only as a fixed regulator
>>> (vcc3v3_pi6c_03), with no clock output representation.
>>>
>>> The PI6C20100 is a clock generator, not a power supply. Model it
>>> properly as a gated-fixed-clock, following the pattern established
>>> for the Rock 5 ITX and other boards with similar PCIe clock buffer
>>> chips.
>>>
>>> The regulator node is kept as-is since it controls the power supply
>>> to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
>>> references this regulator as its vdd-supply and provides a proper
>>> 100MHz clock output. The pcie3x2 node is updated to include the
>>> pipe and reference clocks, matching the approach used in
>>> rk3588-rock-5-itx.dts.
>>>
>>> Assisted-by: Claude:claude-3-opus
>>> Signed-off-by: MidG971 <midgy971@gmail.com>
>>
>> Typically you should use your real name in SoB line, kernel docs state:
>>
>>   using a known identity (sorry, no anonymous contributions.)
>>
>> https://docs.kernel.org/process/submitting-patches.html
>>
>>> ---
>>>
>>> Changes since v2 [1]:
>>>  - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
>>>  - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
>>>    override (Shawn, referencing David's patch [2])
>>>
>>> Changes since v1 [3]:
>>>  - Drop phy-supply approach entirely (Jonas, Shawn)
>>>  - Model PI6C20100 as gated-fixed-clock instead
>>>  - Wire reference clock to pcie3x2 controller
>>>  - Follow pattern from rk3588-rock-5-itx.dts
>>>
>>> [1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
>>> [2] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
>>> [3] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/
>>>
>>>  arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
>>>  1 file changed, 20 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>>> index c5f67dd6dfd9..1a2b3c4d5e6f 100644
>>> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>>> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
>>> @@ -56,7 +56,16 @@
>>>  		};
>>>  	};
>>>
>>> -	/* pi6c pcie clock generator */
>>> +	/* PI6C20100 PCIe reference clock buffer (100MHz) */

The 100MHz part is redundant, clock-frequency already describe this.

>>> +	pcie30_refclk: pcie-clock-generator {
>>> +		compatible = "gated-fixed-clock";
>>> +		#clock-cells = <0>;
>>> +		clock-frequency = <100000000>;
>>> +		clock-output-names = "pcie30_refclk";
>>> +		vdd-supply = <&vcc3v3_pi6c_03>;
>>
>> The vcc3v3_pi6c_03 regulator should also be removed in this patch,
>> as you state in the commit message, it is not a power supply.
>>
>> Please convert to use enable-gpios prop.
> 
> I looked at wrong schematics, please disregard this comment :-)
> 
> Regards.
> Jonas
> 
>>
>> Regards,
>> Jonas
>>
>>> +	};
>>> +
>>> +	/* PI6C20100 power supply - active-high GPIO0_D4 */

The active-high and pin part is redundant, already described with
enable-active-high and gpios props.

>>>  	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {

The regulator-always-on and possible also the boot-on should be removed
here now that we have a proper description of the ref clock.

Removing boot-on may cause NVMe boot issue for U-Boot, but that should
probably be addressed with a proper gated-fixed-clock driver in U-Boot.

Regards,
Jonas

>>>  		compatible = "regulator-fixed";
>>>  		enable-active-high;
>>> @@ -553,6 +562,15 @@
>>>  };
>>>
>>>  &pcie3x2 {
>>> +	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
>>> +		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
>>> +		 <&cru CLK_PCIE30X2_AUX_NDFT>,
>>> +		 <&cru CLK_PCIE30X2_PIPE_DFT>,
>>> +		 <&pcie30_refclk>;
>>> +	clock-names = "aclk_mst", "aclk_slv",
>>> +		      "aclk_dbi", "pclk", "aux",
>>> +		      "pipe", "ref";
>>>  	pinctrl-names = "default";
>>>  	pinctrl-0 = <&pcie30x2m1_pins>;
>>>  	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
>>> --
>>> 2.39.5
>>>
>>
>