* [PATCH v7 1/5] dt-bindings: PCI: imx6q-pcie: Change maxItems of clocks and clock-names to 6
2026-03-13 8:34 [PATCH v7 0/5] Add i.MX943 PCIe supports Richard Zhu
@ 2026-03-13 8:34 ` Richard Zhu
2026-03-13 8:34 ` [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings Richard Zhu
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Richard Zhu @ 2026-03-13 8:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu, Krzysztof Kozlowski
Previous commit 1352f58d7c8d ("dt-bindings: PCI: pci-imx6: Add external
reference clock input") was incomplete.
The constraints for "clocks" and "clock-names" still enforce an incorrect
number of items. Update maxItems for both properties to 6 to match the
actual hardware configuration.
Fixes: 1352f58d7c8d ("dt-bindings: PCI: pci-imx6: Add external reference clock input")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml | 4 ++--
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
index cddbe21f99f2..0488c942092d 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
@@ -17,11 +17,11 @@ description:
properties:
clocks:
minItems: 3
- maxItems: 5
+ maxItems: 6
clock-names:
minItems: 3
- maxItems: 5
+ maxItems: 6
num-lanes:
const: 1
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 12a01f7a5744..21dda8066014 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -40,7 +40,8 @@ properties:
- description: PCIe PHY clock.
- description: Additional required clock entry for imx6sx-pcie,
imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
- - description: PCIe reference clock.
+ - description: PCIe internal reference clock.
+ - description: PCIe additional external reference clock.
clock-names:
minItems: 3
--
2.37.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings
2026-03-13 8:34 [PATCH v7 0/5] Add i.MX943 PCIe supports Richard Zhu
2026-03-13 8:34 ` [PATCH v7 1/5] dt-bindings: PCI: imx6q-pcie: Change maxItems of clocks and clock-names to 6 Richard Zhu
@ 2026-03-13 8:34 ` Richard Zhu
2026-03-22 23:10 ` Rob Herring
2026-03-13 8:34 ` [PATCH v7 3/5] arm64: dts: imx94: add pcie0 and pcie0-ep supports Richard Zhu
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Richard Zhu @ 2026-03-13 8:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu
Add i.MX94 and i.MX943 PCIe compatible strings and fallback to
i.MX95 PCIe compatible string.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
.../bindings/pci/fsl,imx6q-pcie-ep.yaml | 20 +++++++++----
.../bindings/pci/fsl,imx6q-pcie.yaml | 28 ++++++++++++-------
2 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
index 0b3526de1d62..b3b1ece6681e 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -18,12 +18,20 @@ description: |+
properties:
compatible:
- enum:
- - fsl,imx8mm-pcie-ep
- - fsl,imx8mq-pcie-ep
- - fsl,imx8mp-pcie-ep
- - fsl,imx8q-pcie-ep
- - fsl,imx95-pcie-ep
+ oneOf:
+ - enum:
+ - fsl,imx8mm-pcie-ep
+ - fsl,imx8mp-pcie-ep
+ - fsl,imx8mq-pcie-ep
+ - fsl,imx8q-pcie-ep
+ - fsl,imx94-pcie-ep
+ - fsl,imx943-pcie-ep
+ - fsl,imx95-pcie-ep
+ - items:
+ - enum:
+ - fsl,imx94-pcie-ep
+ - fsl,imx943-pcie-ep
+ - const: fsl,imx95-pcie-ep
clocks:
minItems: 3
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 21dda8066014..fd5f7ff9c4a4 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -21,16 +21,24 @@ description: |+
properties:
compatible:
- enum:
- - fsl,imx6q-pcie
- - fsl,imx6sx-pcie
- - fsl,imx6qp-pcie
- - fsl,imx7d-pcie
- - fsl,imx8mq-pcie
- - fsl,imx8mm-pcie
- - fsl,imx8mp-pcie
- - fsl,imx95-pcie
- - fsl,imx8q-pcie
+ oneOf:
+ - enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6sx-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ - fsl,imx8mm-pcie
+ - fsl,imx8mp-pcie
+ - fsl,imx8mq-pcie
+ - fsl,imx8q-pcie
+ - fsl,imx94-pcie
+ - fsl,imx943-pcie
+ - fsl,imx95-pcie
+ - items:
+ - enum:
+ - fsl,imx94-pcie
+ - fsl,imx943-pcie
+ - const: fsl,imx95-pcie
clocks:
minItems: 3
--
2.37.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings
2026-03-13 8:34 ` [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings Richard Zhu
@ 2026-03-22 23:10 ` Rob Herring
2026-03-23 2:23 ` Hongxing Zhu
0 siblings, 1 reply; 9+ messages in thread
From: Rob Herring @ 2026-03-22 23:10 UTC (permalink / raw)
To: Richard Zhu
Cc: krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam, linux-pci,
linux-arm-kernel, devicetree, imx, linux-kernel
On Fri, Mar 13, 2026 at 04:34:40PM +0800, Richard Zhu wrote:
> Add i.MX94 and i.MX943 PCIe compatible strings and fallback to
> i.MX95 PCIe compatible string.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 20 +++++++++----
> .../bindings/pci/fsl,imx6q-pcie.yaml | 28 ++++++++++++-------
> 2 files changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> index 0b3526de1d62..b3b1ece6681e 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> @@ -18,12 +18,20 @@ description: |+
>
> properties:
> compatible:
> - enum:
> - - fsl,imx8mm-pcie-ep
> - - fsl,imx8mq-pcie-ep
> - - fsl,imx8mp-pcie-ep
> - - fsl,imx8q-pcie-ep
> - - fsl,imx95-pcie-ep
> + oneOf:
> + - enum:
> + - fsl,imx8mm-pcie-ep
> + - fsl,imx8mp-pcie-ep
> + - fsl,imx8mq-pcie-ep
> + - fsl,imx8q-pcie-ep
> + - fsl,imx94-pcie-ep
> + - fsl,imx943-pcie-ep
These should be dropped if they are compatible with imx95.
> + - fsl,imx95-pcie-ep
> + - items:
> + - enum:
> + - fsl,imx94-pcie-ep
> + - fsl,imx943-pcie-ep
> + - const: fsl,imx95-pcie-ep
>
> clocks:
> minItems: 3
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index 21dda8066014..fd5f7ff9c4a4 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -21,16 +21,24 @@ description: |+
>
> properties:
> compatible:
> - enum:
> - - fsl,imx6q-pcie
> - - fsl,imx6sx-pcie
> - - fsl,imx6qp-pcie
> - - fsl,imx7d-pcie
> - - fsl,imx8mq-pcie
> - - fsl,imx8mm-pcie
> - - fsl,imx8mp-pcie
> - - fsl,imx95-pcie
> - - fsl,imx8q-pcie
> + oneOf:
> + - enum:
> + - fsl,imx6q-pcie
> + - fsl,imx6sx-pcie
> + - fsl,imx6qp-pcie
> + - fsl,imx7d-pcie
> + - fsl,imx8mm-pcie
> + - fsl,imx8mp-pcie
> + - fsl,imx8mq-pcie
> + - fsl,imx8q-pcie
> + - fsl,imx94-pcie
> + - fsl,imx943-pcie
> + - fsl,imx95-pcie
> + - items:
> + - enum:
> + - fsl,imx94-pcie
> + - fsl,imx943-pcie
> + - const: fsl,imx95-pcie
>
> clocks:
> minItems: 3
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings
2026-03-22 23:10 ` Rob Herring
@ 2026-03-23 2:23 ` Hongxing Zhu
2026-03-23 18:30 ` Frank Li
0 siblings, 1 reply; 9+ messages in thread
From: Hongxing Zhu @ 2026-03-23 2:23 UTC (permalink / raw)
To: Rob Herring
Cc: krzk+dt@kernel.org, conor+dt@kernel.org, bhelgaas@google.com,
Frank Li, l.stach@pengutronix.de, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2026年3月23日 7:10
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: krzk+dt@kernel.org; conor+dt@kernel.org; bhelgaas@google.com; Frank
> Li <frank.li@nxp.com>; l.stach@pengutronix.de; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and
> i.MX943 PCIe compatible strings
>
> On Fri, Mar 13, 2026 at 04:34:40PM +0800, Richard Zhu wrote:
> > Add i.MX94 and i.MX943 PCIe compatible strings and fallback to
> > i.MX95 PCIe compatible string.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> > .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 20 +++++++++----
> > .../bindings/pci/fsl,imx6q-pcie.yaml | 28 ++++++++++++-------
> > 2 files changed, 32 insertions(+), 16 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > index 0b3526de1d62..b3b1ece6681e 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > @@ -18,12 +18,20 @@ description: |+
> >
> > properties:
> > compatible:
> > - enum:
> > - - fsl,imx8mm-pcie-ep
> > - - fsl,imx8mq-pcie-ep
> > - - fsl,imx8mp-pcie-ep
> > - - fsl,imx8q-pcie-ep
> > - - fsl,imx95-pcie-ep
> > + oneOf:
> > + - enum:
> > + - fsl,imx8mm-pcie-ep
> > + - fsl,imx8mp-pcie-ep
> > + - fsl,imx8mq-pcie-ep
> > + - fsl,imx8q-pcie-ep
>
> > + - fsl,imx94-pcie-ep
> > + - fsl,imx943-pcie-ep
>
> These should be dropped if they are compatible with imx95.
Okay, these two would be dropped later.
>
> > + - fsl,imx95-pcie-ep
> > + - items:
> > + - enum:
> > + - fsl,imx94-pcie-ep
> > + - fsl,imx943-pcie-ep
> > + - const: fsl,imx95-pcie-ep
> >
> > clocks:
> > minItems: 3
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index 21dda8066014..fd5f7ff9c4a4 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -21,16 +21,24 @@ description: |+
> >
> > properties:
> > compatible:
> > - enum:
> > - - fsl,imx6q-pcie
> > - - fsl,imx6sx-pcie
> > - - fsl,imx6qp-pcie
> > - - fsl,imx7d-pcie
> > - - fsl,imx8mq-pcie
> > - - fsl,imx8mm-pcie
> > - - fsl,imx8mp-pcie
> > - - fsl,imx95-pcie
> > - - fsl,imx8q-pcie
> > + oneOf:
> > + - enum:
> > + - fsl,imx6q-pcie
> > + - fsl,imx6sx-pcie
> > + - fsl,imx6qp-pcie
> > + - fsl,imx7d-pcie
> > + - fsl,imx8mm-pcie
> > + - fsl,imx8mp-pcie
> > + - fsl,imx8mq-pcie
> > + - fsl,imx8q-pcie
> > + - fsl,imx94-pcie
> > + - fsl,imx943-pcie
Did these two shall be dropped either?
Thanks.
Best Regards
Richard Zhu
> > + - fsl,imx95-pcie
> > + - items:
> > + - enum:
> > + - fsl,imx94-pcie
> > + - fsl,imx943-pcie
> > + - const: fsl,imx95-pcie
> >
> > clocks:
> > minItems: 3
> > --
> > 2.37.1
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings
2026-03-23 2:23 ` Hongxing Zhu
@ 2026-03-23 18:30 ` Frank Li
0 siblings, 0 replies; 9+ messages in thread
From: Frank Li @ 2026-03-23 18:30 UTC (permalink / raw)
To: Hongxing Zhu
Cc: Rob Herring, krzk+dt@kernel.org, conor+dt@kernel.org,
bhelgaas@google.com, l.stach@pengutronix.de,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org
On Mon, Mar 23, 2026 at 02:23:20AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: 2026年3月23日 7:10
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > Cc: krzk+dt@kernel.org; conor+dt@kernel.org; bhelgaas@google.com; Frank
> > Li <frank.li@nxp.com>; l.stach@pengutronix.de; lpieralisi@kernel.org;
> > kwilczynski@kernel.org; mani@kernel.org; s.hauer@pengutronix.de;
> > kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> > imx@lists.linux.dev; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and
> > i.MX943 PCIe compatible strings
> >
> > > + - fsl,imx8mm-pcie
> > > + - fsl,imx8mp-pcie
> > > + - fsl,imx8mq-pcie
> > > + - fsl,imx8q-pcie
> > > + - fsl,imx94-pcie
> > > + - fsl,imx943-pcie
> Did these two shall be dropped either?
Yes, drop because you use fallback "fsl,imx94-pcie", "fsl,imx95-pcie", so
doesn't allow single "fsl,imx94-pcie".
Frank
>
> Thanks.
> Best Regards
> Richard Zhu
> > > + - fsl,imx95-pcie
> > > + - items:
> > > + - enum:
> > > + - fsl,imx94-pcie
> > > + - fsl,imx943-pcie
> > > + - const: fsl,imx95-pcie
> > >
> > > clocks:
> > > minItems: 3
> > > --
> > > 2.37.1
> > >
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v7 3/5] arm64: dts: imx94: add pcie0 and pcie0-ep supports
2026-03-13 8:34 [PATCH v7 0/5] Add i.MX943 PCIe supports Richard Zhu
2026-03-13 8:34 ` [PATCH v7 1/5] dt-bindings: PCI: imx6q-pcie: Change maxItems of clocks and clock-names to 6 Richard Zhu
2026-03-13 8:34 ` [PATCH v7 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings Richard Zhu
@ 2026-03-13 8:34 ` Richard Zhu
2026-03-13 8:34 ` [PATCH v7 4/5] arm64: dts: imx943: add pcie1 and pcie1-ep supports Richard Zhu
2026-03-13 8:34 ` [PATCH v7 5/5] arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support Richard Zhu
4 siblings, 0 replies; 9+ messages in thread
From: Richard Zhu @ 2026-03-13 8:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu
Add pcie0 and pcie0-ep supports.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx94.dtsi | 88 ++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index d2f31c8caf6e..2d8b870554bf 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -66,6 +66,13 @@ sai4_mclk: clock-sai4-mclk1 {
clock-output-names = "sai4_mclk";
};
+ clk_sys100m: clock-sys100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "clk_sys100m";
+ };
+
firmware {
scmi {
compatible = "arm,scmi";
@@ -1223,6 +1230,87 @@ wdog3: watchdog@49220000 {
};
};
+ hsio_blk_ctl: syscon@4c0100c0 {
+ compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
+ reg = <0x0 0x4c0100c0 0x0 0x1>;
+ #clock-cells = <1>;
+ clocks = <&clk_sys100m>;
+ power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
+ };
+
+ pcie0: pcie@4c300000 {
+ compatible = "fsl,imx94-pcie", "fsl,imx95-pcie";
+ reg = <0 0x4c300000 0 0x10000>,
+ <0 0x60100000 0 0xfe00000>,
+ <0 0x4c360000 0 0x10000>,
+ <0 0x4c340000 0 0x4000>;
+ reg-names = "dbi", "config", "atu", "app";
+ ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
+ <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ msi-map = <0x0 &its 0x10 0x1>,
+ <0x100 &its 0x11 0x7>;
+ msi-map-mask = <0x1ff>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ num-viewport = <8>;
+ interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX94_CLK_HSIO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
+ <&hsio_blk_ctl 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
+ assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+ power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
+ fsl,max-link-speed = <3>;
+ status = "disabled";
+ };
+
+ pcie0_ep: pcie-ep@4c300000 {
+ compatible = "fsl,imx94-pcie-ep", "fsl,imx95-pcie-ep";
+ reg = <0 0x4c300000 0 0x10000>,
+ <0 0x4c360000 0 0x1000>,
+ <0 0x4c320000 0 0x1000>,
+ <0 0x4c340000 0 0x4000>,
+ <0 0x4c370000 0 0x10000>,
+ <0x9 0 1 0>;
+ reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ clocks = <&scmi_clk IMX94_CLK_HSIO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+ assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+ msi-map = <0x0 &its 0x10 0x1>;
+ power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
+ status = "disabled";
+ };
+
netc_blk_ctrl: system-controller@4ceb0000 {
compatible = "nxp,imx94-netc-blk-ctrl";
reg = <0x0 0x4ceb0000 0x0 0x10000>,
--
2.37.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v7 4/5] arm64: dts: imx943: add pcie1 and pcie1-ep supports
2026-03-13 8:34 [PATCH v7 0/5] Add i.MX943 PCIe supports Richard Zhu
` (2 preceding siblings ...)
2026-03-13 8:34 ` [PATCH v7 3/5] arm64: dts: imx94: add pcie0 and pcie0-ep supports Richard Zhu
@ 2026-03-13 8:34 ` Richard Zhu
2026-03-13 8:34 ` [PATCH v7 5/5] arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support Richard Zhu
4 siblings, 0 replies; 9+ messages in thread
From: Richard Zhu @ 2026-03-13 8:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu
Add pcie1 and pcie1-ep supports.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx943.dtsi | 75 +++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 45b8da758e87..8575134176f5 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
@@ -145,4 +145,79 @@ l3_cache: l3-cache {
cache-unified;
};
};
+
+ soc {
+ pcie1: pcie@4c380000 {
+ compatible = "fsl,imx943-pcie", "fsl,imx95-pcie";
+ reg = <0 0x4c380000 0 0x10000>,
+ <8 0x80100000 0 0xfe00000>,
+ <0 0x4c3e0000 0 0x10000>,
+ <0 0x4c3c0000 0 0x4000>;
+ reg-names = "dbi", "config", "atu", "app";
+ ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
+ <0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <3>;
+ msi-map = <0x0 &its 0x98 0x1>,
+ <0x100 &its 0x99 0x7>;
+ msi-map-mask = <0x1ff>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ num-viewport = <8>;
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX94_CLK_HSIO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
+ <&hsio_blk_ctl 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
+ assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+ power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
+ fsl,max-link-speed = <3>;
+ status = "disabled";
+ };
+
+ pcie1_ep: pcie-ep@4c380000 {
+ compatible = "fsl,imx943-pcie-ep", "fsl,imx95-pcie-ep";
+ reg = <0 0x4c380000 0 0x10000>,
+ <0 0x4c3e0000 0 0x1000>,
+ <0 0x4c3a0000 0 0x1000>,
+ <0 0x4c3c0000 0 0x4000>,
+ <0 0x4c3f0000 0 0x10000>,
+ <0xa 0 1 0>;
+ reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ clocks = <&scmi_clk IMX94_CLK_HSIO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+ assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+ msi-map = <0x0 &its 0x98 0x1>;
+ power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
+ status = "disabled";
+ };
+ };
};
--
2.37.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v7 5/5] arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support
2026-03-13 8:34 [PATCH v7 0/5] Add i.MX943 PCIe supports Richard Zhu
` (3 preceding siblings ...)
2026-03-13 8:34 ` [PATCH v7 4/5] arm64: dts: imx943: add pcie1 and pcie1-ep supports Richard Zhu
@ 2026-03-13 8:34 ` Richard Zhu
4 siblings, 0 replies; 9+ messages in thread
From: Richard Zhu @ 2026-03-13 8:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu
Add pcie[0,1] and pcie-ep[0,1] support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 4 +
arch/arm64/boot/dts/freescale/imx943-evk.dts | 82 ++++++++++++++++++++
2 files changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a6fe56bb93aa..e0d5148441c6 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -465,6 +465,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
+imx943-evk-pcie0-ep-dtbs += imx943-evk.dtb imx-pcie0-ep.dtbo
+imx943-evk-pcie1-ep-dtbs += imx943-evk.dtb imx-pcie1-ep.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx943-evk-pcie0-ep.dtb imx943-evk-pcie1-ep.dtb
+
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index c8ceabe3d923..f69c0b60b039 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -50,6 +50,20 @@ chosen {
stdout-path = &lpuart1;
};
+ pcie_ref_clk: clock-pcie-ref {
+ compatible = "gpio-gate-clock";
+ clocks = <&xtal25m>;
+ #clock-cells = <0>;
+ enable-gpios = <&pca9670_i2c3 7 GPIO_ACTIVE_LOW>;
+ };
+
+ xtal25m: clock-xtal25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "xtal_25MHz";
+ };
+
dmic: dmic {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
@@ -71,6 +85,15 @@ reg_m2_pwr: regulator-m2-pwr {
startup-delay-us = <5000>;
};
+ reg_slot_pwr: regulator-slot-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIe slot-power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pcal6416_i2c3_u46 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_m2_wlan: regulator-wlan {
compatible = "regulator-fixed";
regulator-name = "WLAN_EN";
@@ -653,6 +676,18 @@ IMX94_PAD_GPIO_IO28__LPI2C6_SCL 0x40000b9e
>;
};
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x4000031e
+ >;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <
+ IMX94_PAD_GPIO_IO23__PCIE2_CLKREQ_B 0x4000031e
+ >;
+ };
+
pinctrl_pdm: pdmgrp {
fsl,pins = <
IMX94_PAD_PDM_CLK__PDM_CLK 0x31e
@@ -821,6 +856,53 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe
};
};
+&pcie0 {
+ pinctrl-0 = <&pinctrl_pcie0>;
+ pinctrl-names = "default";
+ clocks = <&scmi_clk IMX94_CLK_HSIO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
+ <&hsio_blk_ctl 0>,
+ <&pcie_ref_clk>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
+ "ref", "extref";
+ reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>;
+ vpcie3v3aux-supply = <®_m2_wlan>;
+ supports-clkreq;
+ status = "okay";
+};
+
+&pcie0_ep {
+ pinctrl-0 = <&pinctrl_pcie0>;
+ pinctrl-names = "default";
+ vpcie-supply = <®_m2_wlan>;
+ status = "disabled";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pinctrl_pcie1>;
+ pinctrl-names = "default";
+ clocks = <&scmi_clk IMX94_CLK_HSIO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
+ <&hsio_blk_ctl 0>,
+ <&pcie_ref_clk>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
+ "ref", "extref";
+ reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>;
+ vpcie3v3aux-supply = <®_slot_pwr>;
+ status = "okay";
+};
+
+&pcie1_ep {
+ pinctrl-0 = <&pinctrl_pcie1>;
+ pinctrl-names = "default";
+ vpcie-supply = <®_slot_pwr>;
+ status = "disabled";
+};
+
&usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
--
2.37.1
^ permalink raw reply related [flat|nested] 9+ messages in thread