From: Marc Kleine-Budde <mkl@pengutronix.de>
To: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
Cc: Vincent Mailhol <mailhol@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
linux-can@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
NXP S32 Linux Team <s32@nxp.com>,
Christophe Lizzi <clizzi@redhat.com>,
Alberto Ruiz <aruizrui@redhat.com>,
Enric Balletbo <eballetb@redhat.com>,
Eric Chanudet <echanude@redhat.com>
Subject: Re: [PATCH v3 1/6] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms
Date: Tue, 24 Mar 2026 12:56:48 +0100 [thread overview]
Message-ID: <20260324-psychedelic-idealistic-dormouse-95b03c-mkl@pengutronix.de> (raw)
In-Reply-To: <20260323135827.2129371-2-ciprianmarian.costea@oss.nxp.com>
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On 23.03.2026 14:58:22, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> On platforms with multiple IRQ lines (S32G2, MCF5441X), all lines are
> registered to the same flexcan_irq() handler. Since these are distinct IRQ
> numbers, they can be dispatched concurrently on different CPUs. Both
> instances then read the same iflag and ESR registers unconditionally,
> leading to duplicate frame processing.
>
> Fix this by splitting the monolithic handler into focused parts:
> - flexcan_do_mb(): processes mailbox events
> - flexcan_do_state(): processes device state change events
> - flexcan_do_berr(): processes bus error events
>
> Introduce dedicated IRQ handlers for multi-IRQ platforms:
> - flexcan_irq_mb(): mailbox-only, used for mb-0, mb-1 IRQ lines
> - flexcan_irq_boff(): state-change-only, used for boff/state IRQ line
> - flexcan_irq_berr(): bus-error-only, used for berr IRQ line
>
> The combined flexcan_irq() handler is preserved for single-IRQ
> platforms with no functional change.
Thanks for implementing this.
Can you take care of the S32G2 which has 2 mailbox IRQs, too? Please in
a separate patch.
My idea was to take the "irq" argument of the IRQ handler and the quirks
and figure out if you are the first or second mailbox IRQ handler.
Convert these
| struct flexcan_priv {
| [...]
| u64 rx_mask;
| u64 tx_mask;
| [...]
| }
into a struct and put an array of 2 of these structs into "struct
flexcan_priv". Use correct mask array depending on IRQ handler.
regards,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung Nürnberg | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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next prev parent reply other threads:[~2026-03-24 11:57 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-23 13:58 [PATCH v3 0/6] can: flexcan: Add NXP S32N79 SoC support Ciprian Costea
2026-03-23 13:58 ` [PATCH v3 1/6] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms Ciprian Costea
2026-03-24 11:56 ` Marc Kleine-Budde [this message]
2026-03-24 12:30 ` Ciprian Marian Costea
2026-03-24 13:44 ` Marc Kleine-Budde
2026-03-23 13:58 ` [PATCH v3 2/6] dt-bindings: can: fsl,flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-03-23 19:35 ` Conor Dooley
2026-03-23 13:58 ` [PATCH v3 3/6] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk Ciprian Costea
2026-03-23 13:58 ` [PATCH v3 4/6] can: flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-03-23 13:58 ` [PATCH v3 5/6] arm64: dts: s32n79: add FlexCAN nodes Ciprian Costea
2026-03-23 13:58 ` [PATCH v3 6/6] arm64: dts: s32n79: enable FlexCAN devices Ciprian Costea
2026-03-24 11:58 ` [PATCH v3 0/6] can: flexcan: Add NXP S32N79 SoC support Marc Kleine-Budde
2026-03-24 12:18 ` Ciprian Marian Costea
2026-03-24 13:46 ` Marc Kleine-Budde
2026-03-25 12:45 ` Ciprian Marian Costea
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