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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm609925f8f.18.2026.03.25.08.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2026 08:42:11 -0700 (PDT) Date: Wed, 25 Mar 2026 15:42:10 +0000 From: David Laight To: Catalin Marinas Cc: Ankur Arora , Andrew Morton , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, bpf@vger.kernel.org, arnd@arndb.de, will@kernel.org, peterz@infradead.org, mark.rutland@arm.com, harisokn@amazon.com, cl@gentwo.org, ast@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, memxor@gmail.com, zhenglifeng1@huawei.com, xueshuai@linux.alibaba.com, rdunlap@infradead.org, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, konrad.wilk@oracle.com Subject: Re: [PATCH v10 00/12] barrier: Add smp_cond_load_{relaxed,acquire}_timeout() Message-ID: <20260325154210.79a621df@pumpkin> In-Reply-To: References: <20260316013651.3225328-1-ankur.a.arora@oracle.com> <20260315184925.b6f93386e918ca79614843e3@linux-foundation.org> <874imftol4.fsf@oracle.com> <20260316233712.7cbfac27@pumpkin> <87ms07rlp9.fsf@oracle.com> <20260317091705.5a64fc56@pumpkin> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260325_084215_172106_B2FB83C9 X-CRM114-Status: GOOD ( 25.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 25 Mar 2026 13:53:50 +0000 Catalin Marinas wrote: > On Tue, Mar 17, 2026 at 09:17:05AM +0000, David Laight wrote: > > On Mon, 16 Mar 2026 23:53:22 -0700 > > Ankur Arora wrote: > > > David Laight writes: > > > > On arm64 I think you could use explicit sev and wfe - but that will wake all > > > > 'sleeping' cpu; and you may not want the 'thundering herd'. > > > > > > Wouldn't we still have the same narrow window where the CPU disregards the IPI? > > > > You need a 'sevl' in the interrupt exit path. > > No need to, see the rule below in > https://developer.arm.com/documentation/ddi0487/maa/2983-beijhbbd: > > R_XRZRK > The Event Register for a PE is set by any of the following: > [...] > - An exception return. > It is a shame the pages for the SEV and WFE instructions don't mention that. And the copy I found doesn't have working hyperlinks to any other sections. (Not even references to related instructions...) You do need to at least comment that the "msr s0_3_c1_c0_0, %[ecycles]" is actually WFET. Is that using an absolute cycle count? If so does it work if the time has already passed? If it is absolute do you need to recalculate it every time around the loop? __delay_cycles() contains guard(preempt_notrace()). I haven't looked what that does but is it needed here since preemption is disabled? Looking at the code I think the "sevl; wfe" pair should be higher up. If they were before the evaluation of the condition then an IPI that set need_resched() just after it was tested would cause a wakeup. Clearly that won't help if the condition does anything that executes 'wfe' and won't sleep if it sets the event - but I suspect they are unlikely. I also wonder how long it takes the cpu to leave any low power state. We definitely found that was an issue on some x86 cpu and had to both disable the lowest low power state and completely rework some wakeup code that really wanted a 'thundering herd' rather than the very gentle 'bring each cpu out of low power one at a time' that cv_broadcast() gave it. David